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1// SPDX-License-Identifier: GPL-2.0+
2/* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
4 *
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
7 */
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/platform_device.h>
13#include <linux/sys_soc.h>
14#include <linux/fsl/mc.h>
15
16#include "compat.h"
17#include "debugfs.h"
18#include "regs.h"
19#include "intern.h"
20#include "jr.h"
21#include "desc_constr.h"
22#include "ctrl.h"
23
24bool caam_dpaa2;
25EXPORT_SYMBOL(caam_dpaa2);
26
27#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
28#include "qi.h"
29#endif
30
31/*
32 * Descriptor to instantiate RNG State Handle 0 in normal mode and
33 * load the JDKEK, TDKEK and TDSK registers
34 */
35static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
36{
37 u32 *jump_cmd, op_flags;
38
39 init_job_desc(desc, 0);
40
41 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
42 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
43 OP_ALG_PR_ON;
44
45 /* INIT RNG in non-test mode */
46 append_operation(desc, op_flags);
47
48 if (!handle && do_sk) {
49 /*
50 * For SH0, Secure Keys must be generated as well
51 */
52
53 /* wait for done */
54 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
55 set_jump_tgt_here(desc, jump_cmd);
56
57 /*
58 * load 1 to clear written reg:
59 * resets the done interrupt and returns the RNG to idle.
60 */
61 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
62
63 /* Initialize State Handle */
64 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
65 OP_ALG_AAI_RNG4_SK);
66 }
67
68 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
69}
70
71/* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
72static void build_deinstantiation_desc(u32 *desc, int handle)
73{
74 init_job_desc(desc, 0);
75
76 /* Uninstantiate State Handle 0 */
77 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
78 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
79
80 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
81}
82
83#ifdef CONFIG_OF
84static const struct of_device_id imx8m_machine_match[] = {
85 { .compatible = "fsl,imx8mm", },
86 { .compatible = "fsl,imx8mn", },
87 { .compatible = "fsl,imx8mp", },
88 { .compatible = "fsl,imx8mq", },
89 { .compatible = "fsl,imx8ulp", },
90 { }
91};
92#endif
93
94/*
95 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
96 * the software (no JR/QI used).
97 * @ctrldev - pointer to device
98 * @status - descriptor status, after being run
99 *
100 * Return: - 0 if no error occurred
101 * - -ENODEV if the DECO couldn't be acquired
102 * - -EAGAIN if an error occurred while executing the descriptor
103 */
104static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
105 u32 *status)
106{
107 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
108 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
109 struct caam_deco __iomem *deco = ctrlpriv->deco;
110 unsigned int timeout = 100000;
111 u32 deco_dbg_reg, deco_state, flags;
112 int i;
113
114
115 if (ctrlpriv->virt_en == 1 ||
116 /*
117 * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1
118 * and the following steps should be performed regardless
119 */
120 of_match_node(imx8m_machine_match, of_root)) {
121 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
122
123 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
124 --timeout)
125 cpu_relax();
126
127 timeout = 100000;
128 }
129
130 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
131
132 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
133 --timeout)
134 cpu_relax();
135
136 if (!timeout) {
137 dev_err(ctrldev, "failed to acquire DECO 0\n");
138 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
139 return -ENODEV;
140 }
141
142 for (i = 0; i < desc_len(desc); i++)
143 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
144
145 flags = DECO_JQCR_WHL;
146 /*
147 * If the descriptor length is longer than 4 words, then the
148 * FOUR bit in JRCTRL register must be set.
149 */
150 if (desc_len(desc) >= 4)
151 flags |= DECO_JQCR_FOUR;
152
153 /* Instruct the DECO to execute it */
154 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
155
156 timeout = 10000000;
157 do {
158 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
159
160 if (ctrlpriv->era < 10)
161 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
162 DESC_DBG_DECO_STAT_SHIFT;
163 else
164 deco_state = (rd_reg32(&deco->dbg_exec) &
165 DESC_DER_DECO_STAT_MASK) >>
166 DESC_DER_DECO_STAT_SHIFT;
167
168 /*
169 * If an error occurred in the descriptor, then
170 * the DECO status field will be set to 0x0D
171 */
172 if (deco_state == DECO_STAT_HOST_ERR)
173 break;
174
175 cpu_relax();
176 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
177
178 *status = rd_reg32(&deco->op_status_hi) &
179 DECO_OP_STATUS_HI_ERR_MASK;
180
181 if (ctrlpriv->virt_en == 1)
182 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
183
184 /* Mark the DECO as free */
185 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
186
187 if (!timeout)
188 return -EAGAIN;
189
190 return 0;
191}
192
193/*
194 * deinstantiate_rng - builds and executes a descriptor on DECO0,
195 * which deinitializes the RNG block.
196 * @ctrldev - pointer to device
197 * @state_handle_mask - bitmask containing the instantiation status
198 * for the RNG4 state handles which exist in
199 * the RNG4 block: 1 if it's been instantiated
200 *
201 * Return: - 0 if no error occurred
202 * - -ENOMEM if there isn't enough memory to allocate the descriptor
203 * - -ENODEV if DECO0 couldn't be acquired
204 * - -EAGAIN if an error occurred when executing the descriptor
205 */
206static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
207{
208 u32 *desc, status;
209 int sh_idx, ret = 0;
210
211 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
212 if (!desc)
213 return -ENOMEM;
214
215 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
216 /*
217 * If the corresponding bit is set, then it means the state
218 * handle was initialized by us, and thus it needs to be
219 * deinitialized as well
220 */
221 if ((1 << sh_idx) & state_handle_mask) {
222 /*
223 * Create the descriptor for deinstantating this state
224 * handle
225 */
226 build_deinstantiation_desc(desc, sh_idx);
227
228 /* Try to run it through DECO0 */
229 ret = run_descriptor_deco0(ctrldev, desc, &status);
230
231 if (ret ||
232 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
233 dev_err(ctrldev,
234 "Failed to deinstantiate RNG4 SH%d\n",
235 sh_idx);
236 break;
237 }
238 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
239 }
240 }
241
242 kfree(desc);
243
244 return ret;
245}
246
247static void devm_deinstantiate_rng(void *data)
248{
249 struct device *ctrldev = data;
250 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
251
252 /*
253 * De-initialize RNG state handles initialized by this driver.
254 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
255 */
256 if (ctrlpriv->rng4_sh_init)
257 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
258}
259
260/*
261 * instantiate_rng - builds and executes a descriptor on DECO0,
262 * which initializes the RNG block.
263 * @ctrldev - pointer to device
264 * @state_handle_mask - bitmask containing the instantiation status
265 * for the RNG4 state handles which exist in
266 * the RNG4 block: 1 if it's been instantiated
267 * by an external entry, 0 otherwise.
268 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
269 * Caution: this can be done only once; if the keys need to be
270 * regenerated, a POR is required
271 *
272 * Return: - 0 if no error occurred
273 * - -ENOMEM if there isn't enough memory to allocate the descriptor
274 * - -ENODEV if DECO0 couldn't be acquired
275 * - -EAGAIN if an error occurred when executing the descriptor
276 * f.i. there was a RNG hardware error due to not "good enough"
277 * entropy being acquired.
278 */
279static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
280 int gen_sk)
281{
282 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
283 struct caam_ctrl __iomem *ctrl;
284 u32 *desc, status = 0, rdsta_val;
285 int ret = 0, sh_idx;
286
287 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
288 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
289 if (!desc)
290 return -ENOMEM;
291
292 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
293 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
294 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
295 const u32 rdsta_mask = rdsta_if | rdsta_pr;
296
297 /* Clear the contents before using the descriptor */
298 memset(desc, 0x00, CAAM_CMD_SZ * 7);
299
300 /*
301 * If the corresponding bit is set, this state handle
302 * was initialized by somebody else, so it's left alone.
303 */
304 if (rdsta_if & state_handle_mask) {
305 if (rdsta_pr & state_handle_mask)
306 continue;
307
308 dev_info(ctrldev,
309 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
310 sh_idx);
311
312 ret = deinstantiate_rng(ctrldev, rdsta_if);
313 if (ret)
314 break;
315 }
316
317 /* Create the descriptor for instantiating RNG State Handle */
318 build_instantiation_desc(desc, sh_idx, gen_sk);
319
320 /* Try to run it through DECO0 */
321 ret = run_descriptor_deco0(ctrldev, desc, &status);
322
323 /*
324 * If ret is not 0, or descriptor status is not 0, then
325 * something went wrong. No need to try the next state
326 * handle (if available), bail out here.
327 * Also, if for some reason, the State Handle didn't get
328 * instantiated although the descriptor has finished
329 * without any error (HW optimizations for later
330 * CAAM eras), then try again.
331 */
332 if (ret)
333 break;
334
335 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
336 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
337 (rdsta_val & rdsta_mask) != rdsta_mask) {
338 ret = -EAGAIN;
339 break;
340 }
341
342 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
343 }
344
345 kfree(desc);
346
347 if (ret)
348 return ret;
349
350 return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
351}
352
353/*
354 * kick_trng - sets the various parameters for enabling the initialization
355 * of the RNG4 block in CAAM
356 * @dev - pointer to the controller device
357 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
358 */
359static void kick_trng(struct device *dev, int ent_delay)
360{
361 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
362 struct caam_ctrl __iomem *ctrl;
363 struct rng4tst __iomem *r4tst;
364 u32 val, rtsdctl;
365
366 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
367 r4tst = &ctrl->r4tst[0];
368
369 /*
370 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
371 * properly invalidate the entropy in the entropy register and
372 * force re-generation.
373 */
374 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
375
376 /*
377 * Performance-wise, it does not make sense to
378 * set the delay to a value that is lower
379 * than the last one that worked (i.e. the state handles
380 * were instantiated properly).
381 */
382 rtsdctl = rd_reg32(&r4tst->rtsdctl);
383 val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT;
384 if (ent_delay > val) {
385 val = ent_delay;
386 /* min. freq. count, equal to 1/4 of the entropy sample length */
387 wr_reg32(&r4tst->rtfrqmin, val >> 2);
388 /* disable maximum frequency count */
389 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
390 }
391
392 wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |
393 RTSDCTL_SAMP_SIZE_VAL);
394
395 /*
396 * To avoid reprogramming the self-test parameters over and over again,
397 * use RTSDCTL[SAMP_SIZE] as an indicator.
398 */
399 if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) {
400 wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
401 wr_reg32(&r4tst->rtpkrrng, 570);
402 wr_reg32(&r4tst->rtpkrmax, 1600);
403 wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
404 wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);
405 wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);
406 wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);
407 wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);
408 wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);
409 wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);
410 }
411
412 /*
413 * select raw sampling in both entropy shifter
414 * and statistical checker; ; put RNG4 into run mode
415 */
416 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
417 RTMCTL_SAMP_MODE_RAW_ES_SC);
418}
419
420static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
421{
422 static const struct {
423 u16 ip_id;
424 u8 maj_rev;
425 u8 era;
426 } id[] = {
427 {0x0A10, 1, 1},
428 {0x0A10, 2, 2},
429 {0x0A12, 1, 3},
430 {0x0A14, 1, 3},
431 {0x0A14, 2, 4},
432 {0x0A16, 1, 4},
433 {0x0A10, 3, 4},
434 {0x0A11, 1, 4},
435 {0x0A18, 1, 4},
436 {0x0A11, 2, 5},
437 {0x0A12, 2, 5},
438 {0x0A13, 1, 5},
439 {0x0A1C, 1, 5}
440 };
441 u32 ccbvid, id_ms;
442 u8 maj_rev, era;
443 u16 ip_id;
444 int i;
445
446 ccbvid = rd_reg32(&perfmon->ccb_id);
447 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
448 if (era) /* This is '0' prior to CAAM ERA-6 */
449 return era;
450
451 id_ms = rd_reg32(&perfmon->caam_id_ms);
452 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
453 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
454
455 for (i = 0; i < ARRAY_SIZE(id); i++)
456 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
457 return id[i].era;
458
459 return -ENOTSUPP;
460}
461
462/**
463 * caam_get_era() - Return the ERA of the SEC on SoC, based
464 * on "sec-era" optional property in the DTS. This property is updated
465 * by u-boot.
466 * In case this property is not passed an attempt to retrieve the CAAM
467 * era via register reads will be made.
468 *
469 * @perfmon: Performance Monitor Registers
470 */
471static int caam_get_era(struct caam_perfmon __iomem *perfmon)
472{
473 struct device_node *caam_node;
474 int ret;
475 u32 prop;
476
477 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
478 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
479 of_node_put(caam_node);
480
481 if (!ret)
482 return prop;
483 else
484 return caam_get_era_from_hw(perfmon);
485}
486
487/*
488 * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
489 * have an issue wherein AXI bus transactions may not occur in the correct
490 * order. This isn't a problem running single descriptors, but can be if
491 * running multiple concurrent descriptors. Reworking the driver to throttle
492 * to single requests is impractical, thus the workaround is to limit the AXI
493 * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
494 * from occurring.
495 */
496static void handle_imx6_err005766(u32 __iomem *mcr)
497{
498 if (of_machine_is_compatible("fsl,imx6q") ||
499 of_machine_is_compatible("fsl,imx6dl") ||
500 of_machine_is_compatible("fsl,imx6qp"))
501 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
502 1 << MCFGR_AXIPIPE_SHIFT);
503}
504
505static const struct of_device_id caam_match[] = {
506 {
507 .compatible = "fsl,sec-v4.0",
508 },
509 {
510 .compatible = "fsl,sec4.0",
511 },
512 {},
513};
514MODULE_DEVICE_TABLE(of, caam_match);
515
516struct caam_imx_data {
517 bool page0_access;
518 const struct clk_bulk_data *clks;
519 int num_clks;
520};
521
522static const struct clk_bulk_data caam_imx6_clks[] = {
523 { .id = "ipg" },
524 { .id = "mem" },
525 { .id = "aclk" },
526 { .id = "emi_slow" },
527};
528
529static const struct caam_imx_data caam_imx6_data = {
530 .page0_access = true,
531 .clks = caam_imx6_clks,
532 .num_clks = ARRAY_SIZE(caam_imx6_clks),
533};
534
535static const struct clk_bulk_data caam_imx7_clks[] = {
536 { .id = "ipg" },
537 { .id = "aclk" },
538};
539
540static const struct caam_imx_data caam_imx7_data = {
541 .page0_access = true,
542 .clks = caam_imx7_clks,
543 .num_clks = ARRAY_SIZE(caam_imx7_clks),
544};
545
546static const struct clk_bulk_data caam_imx6ul_clks[] = {
547 { .id = "ipg" },
548 { .id = "mem" },
549 { .id = "aclk" },
550};
551
552static const struct caam_imx_data caam_imx6ul_data = {
553 .page0_access = true,
554 .clks = caam_imx6ul_clks,
555 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
556};
557
558static const struct clk_bulk_data caam_vf610_clks[] = {
559 { .id = "ipg" },
560};
561
562static const struct caam_imx_data caam_vf610_data = {
563 .page0_access = true,
564 .clks = caam_vf610_clks,
565 .num_clks = ARRAY_SIZE(caam_vf610_clks),
566};
567
568static const struct caam_imx_data caam_imx8ulp_data;
569
570static const struct soc_device_attribute caam_imx_soc_table[] = {
571 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
572 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
573 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
574 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
575 { .soc_id = "i.MX8ULP", .data = &caam_imx8ulp_data },
576 { .soc_id = "i.MX8Q*", .data = &caam_imx8ulp_data },
577 { .soc_id = "VF*", .data = &caam_vf610_data },
578 { .family = "Freescale i.MX" },
579 { /* sentinel */ }
580};
581
582static void disable_clocks(void *data)
583{
584 struct caam_drv_private *ctrlpriv = data;
585
586 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
587}
588
589static int init_clocks(struct device *dev, const struct caam_imx_data *data)
590{
591 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
592 int ret;
593
594 ctrlpriv->num_clks = data->num_clks;
595 ctrlpriv->clks = devm_kmemdup_array(dev, data->clks,
596 data->num_clks, sizeof(*data->clks),
597 GFP_KERNEL);
598 if (!ctrlpriv->clks)
599 return -ENOMEM;
600
601 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
602 if (ret) {
603 dev_err(dev,
604 "Failed to request all necessary clocks\n");
605 return ret;
606 }
607
608 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
609 if (ret) {
610 dev_err(dev,
611 "Failed to prepare/enable all necessary clocks\n");
612 return ret;
613 }
614
615 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
616}
617
618static void caam_remove_debugfs(void *root)
619{
620 debugfs_remove_recursive(root);
621}
622
623#ifdef CONFIG_FSL_MC_BUS
624static bool check_version(struct fsl_mc_version *mc_version, u32 major,
625 u32 minor, u32 revision)
626{
627 if (mc_version->major > major)
628 return true;
629
630 if (mc_version->major == major) {
631 if (mc_version->minor > minor)
632 return true;
633
634 if (mc_version->minor == minor &&
635 mc_version->revision > revision)
636 return true;
637 }
638
639 return false;
640}
641#endif
642
643static bool needs_entropy_delay_adjustment(void)
644{
645 if (of_machine_is_compatible("fsl,imx6sx"))
646 return true;
647 return false;
648}
649
650static int caam_ctrl_rng_init(struct device *dev)
651{
652 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
653 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
654 int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
655 u8 rng_vid;
656
657 if (ctrlpriv->era < 10) {
658 struct caam_perfmon __iomem *perfmon;
659
660 perfmon = ctrlpriv->total_jobrs ?
661 (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
662 (struct caam_perfmon __iomem *)&ctrl->perfmon;
663
664 rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
665 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
666 } else {
667 struct version_regs __iomem *vreg;
668
669 vreg = ctrlpriv->total_jobrs ?
670 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
671 (struct version_regs __iomem *)&ctrl->vreg;
672
673 rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
674 CHA_VER_VID_SHIFT;
675 }
676
677 /*
678 * If SEC has RNG version >= 4 and RNG state handle has not been
679 * already instantiated, do RNG instantiation
680 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
681 */
682 if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) {
683 ctrlpriv->rng4_sh_init =
684 rd_reg32(&ctrl->r4tst[0].rdsta);
685 /*
686 * If the secure keys (TDKEK, JDKEK, TDSK), were already
687 * generated, signal this to the function that is instantiating
688 * the state handles. An error would occur if RNG4 attempts
689 * to regenerate these keys before the next POR.
690 */
691 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
692 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
693 do {
694 int inst_handles =
695 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
696 /*
697 * If either SH were instantiated by somebody else
698 * (e.g. u-boot) then it is assumed that the entropy
699 * parameters are properly set and thus the function
700 * setting these (kick_trng(...)) is skipped.
701 * Also, if a handle was instantiated, do not change
702 * the TRNG parameters.
703 */
704 if (needs_entropy_delay_adjustment())
705 ent_delay = 12000;
706 if (!inst_handles) {
707 dev_info(dev,
708 "Entropy delay = %u\n",
709 ent_delay);
710 kick_trng(dev, ent_delay);
711 ent_delay = ent_delay * 2;
712 }
713 /*
714 * if instantiate_rng(...) fails, the loop will rerun
715 * and the kick_trng(...) function will modify the
716 * upper and lower limits of the entropy sampling
717 * interval, leading to a successful initialization of
718 * the RNG.
719 */
720 ret = instantiate_rng(dev, inst_handles,
721 gen_sk);
722 /*
723 * Entropy delay is determined via TRNG characterization.
724 * TRNG characterization is run across different voltages
725 * and temperatures.
726 * If worst case value for ent_dly is identified,
727 * the loop can be skipped for that platform.
728 */
729 if (needs_entropy_delay_adjustment())
730 break;
731 if (ret == -EAGAIN)
732 /*
733 * if here, the loop will rerun,
734 * so don't hog the CPU
735 */
736 cpu_relax();
737 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
738 if (ret) {
739 dev_err(dev, "failed to instantiate RNG");
740 return ret;
741 }
742 /*
743 * Set handles initialized by this module as the complement of
744 * the already initialized ones
745 */
746 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
747
748 /* Enable RDB bit so that RNG works faster */
749 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
750 }
751
752 return 0;
753}
754
755/* Indicate if the internal state of the CAAM is lost during PM */
756static int caam_off_during_pm(void)
757{
758 bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") ||
759 of_machine_is_compatible("fsl,imx6qp") ||
760 of_machine_is_compatible("fsl,imx6dl");
761
762 return not_off_during_pm ? 0 : 1;
763}
764
765static void caam_state_save(struct device *dev)
766{
767 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
768 struct caam_ctl_state *state = &ctrlpriv->state;
769 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
770 u32 deco_inst, jr_inst;
771 int i;
772
773 state->mcr = rd_reg32(&ctrl->mcr);
774 state->scfgr = rd_reg32(&ctrl->scfgr);
775
776 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
777 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
778 for (i = 0; i < deco_inst; i++) {
779 state->deco_mid[i].liodn_ms =
780 rd_reg32(&ctrl->deco_mid[i].liodn_ms);
781 state->deco_mid[i].liodn_ls =
782 rd_reg32(&ctrl->deco_mid[i].liodn_ls);
783 }
784
785 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
786 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
787 for (i = 0; i < jr_inst; i++) {
788 state->jr_mid[i].liodn_ms =
789 rd_reg32(&ctrl->jr_mid[i].liodn_ms);
790 state->jr_mid[i].liodn_ls =
791 rd_reg32(&ctrl->jr_mid[i].liodn_ls);
792 }
793}
794
795static void caam_state_restore(const struct device *dev)
796{
797 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
798 const struct caam_ctl_state *state = &ctrlpriv->state;
799 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
800 u32 deco_inst, jr_inst;
801 int i;
802
803 wr_reg32(&ctrl->mcr, state->mcr);
804 wr_reg32(&ctrl->scfgr, state->scfgr);
805
806 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
807 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
808 for (i = 0; i < deco_inst; i++) {
809 wr_reg32(&ctrl->deco_mid[i].liodn_ms,
810 state->deco_mid[i].liodn_ms);
811 wr_reg32(&ctrl->deco_mid[i].liodn_ls,
812 state->deco_mid[i].liodn_ls);
813 }
814
815 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
816 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
817 for (i = 0; i < jr_inst; i++) {
818 wr_reg32(&ctrl->jr_mid[i].liodn_ms,
819 state->jr_mid[i].liodn_ms);
820 wr_reg32(&ctrl->jr_mid[i].liodn_ls,
821 state->jr_mid[i].liodn_ls);
822 }
823
824 if (ctrlpriv->virt_en == 1)
825 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
826 JRSTART_JR1_START | JRSTART_JR2_START |
827 JRSTART_JR3_START);
828}
829
830static int caam_ctrl_suspend(struct device *dev)
831{
832 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
833
834 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->no_page0)
835 caam_state_save(dev);
836
837 return 0;
838}
839
840static int caam_ctrl_resume(struct device *dev)
841{
842 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
843 int ret = 0;
844
845 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->no_page0) {
846 caam_state_restore(dev);
847
848 /* HW and rng will be reset so deinstantiation can be removed */
849 devm_remove_action(dev, devm_deinstantiate_rng, dev);
850 ret = caam_ctrl_rng_init(dev);
851 }
852
853 return ret;
854}
855
856static DEFINE_SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume);
857
858/* Probe routine for CAAM top (controller) level */
859static int caam_probe(struct platform_device *pdev)
860{
861 int ret, ring;
862 u64 caam_id;
863 const struct soc_device_attribute *imx_soc_match;
864 struct device *dev;
865 struct device_node *nprop, *np;
866 struct caam_ctrl __iomem *ctrl;
867 struct caam_drv_private *ctrlpriv;
868 struct caam_perfmon __iomem *perfmon;
869 struct dentry *dfs_root;
870 u32 scfgr, comp_params;
871 int pg_size;
872 int BLOCK_OFFSET = 0;
873 bool reg_access = true;
874 const struct caam_imx_data *imx_soc_data;
875
876 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
877 if (!ctrlpriv)
878 return -ENOMEM;
879
880 dev = &pdev->dev;
881 dev_set_drvdata(dev, ctrlpriv);
882 nprop = pdev->dev.of_node;
883
884 imx_soc_match = soc_device_match(caam_imx_soc_table);
885 if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root))
886 return -EPROBE_DEFER;
887
888 caam_imx = (bool)imx_soc_match;
889
890 ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm();
891
892 if (imx_soc_match) {
893 /*
894 * Until Layerscape and i.MX OP-TEE get in sync,
895 * only i.MX OP-TEE use cases disallow access to
896 * caam page 0 (controller) registers.
897 */
898 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
899 ctrlpriv->optee_en = !!np;
900 of_node_put(np);
901
902 reg_access = !ctrlpriv->optee_en;
903
904 if (!imx_soc_match->data) {
905 dev_err(dev, "No clock data provided for i.MX SoC");
906 return -EINVAL;
907 }
908
909 imx_soc_data = imx_soc_match->data;
910 reg_access = reg_access && imx_soc_data->page0_access;
911 ctrlpriv->no_page0 = !reg_access;
912 /*
913 * CAAM clocks cannot be controlled from kernel.
914 */
915 if (!imx_soc_data->num_clks)
916 goto iomap_ctrl;
917
918 ret = init_clocks(dev, imx_soc_match->data);
919 if (ret)
920 return ret;
921 }
922
923iomap_ctrl:
924 /* Get configuration properties from device tree */
925 /* First, get register page */
926 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
927 ret = PTR_ERR_OR_ZERO(ctrl);
928 if (ret) {
929 dev_err(dev, "caam: of_iomap() failed\n");
930 return ret;
931 }
932
933 ring = 0;
934 for_each_available_child_of_node(nprop, np)
935 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
936 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
937 u32 reg;
938
939 if (of_property_read_u32_index(np, "reg", 0, &reg)) {
940 dev_err(dev, "%s read reg property error\n",
941 np->full_name);
942 continue;
943 }
944
945 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
946 ((__force uint8_t *)ctrl + reg);
947
948 ctrlpriv->total_jobrs++;
949 ring++;
950 }
951
952 /*
953 * Wherever possible, instead of accessing registers from the global page,
954 * use the alias registers in the first (cf. DT nodes order)
955 * job ring's page.
956 */
957 perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
958 (struct caam_perfmon __iomem *)&ctrl->perfmon;
959
960 caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
961 (CSTA_PLEND | CSTA_ALT_PLEND));
962 comp_params = rd_reg32(&perfmon->comp_parms_ms);
963 if (reg_access && comp_params & CTPR_MS_PS &&
964 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
965 caam_ptr_sz = sizeof(u64);
966 else
967 caam_ptr_sz = sizeof(u32);
968 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
969 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
970
971#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
972 /* If (DPAA 1.x) QI present, check whether dependencies are available */
973 if (ctrlpriv->qi_present && !caam_dpaa2) {
974 ret = qman_is_probed();
975 if (!ret) {
976 return -EPROBE_DEFER;
977 } else if (ret < 0) {
978 dev_err(dev, "failing probe due to qman probe error\n");
979 return -ENODEV;
980 }
981
982 ret = qman_portals_probed();
983 if (!ret) {
984 return -EPROBE_DEFER;
985 } else if (ret < 0) {
986 dev_err(dev, "failing probe due to qman portals probe error\n");
987 return -ENODEV;
988 }
989 }
990#endif
991
992 /* Allocating the BLOCK_OFFSET based on the supported page size on
993 * the platform
994 */
995 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
996 if (pg_size == 0)
997 BLOCK_OFFSET = PG_SIZE_4K;
998 else
999 BLOCK_OFFSET = PG_SIZE_64K;
1000
1001 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
1002 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
1003 ((__force uint8_t *)ctrl +
1004 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
1005 );
1006 ctrlpriv->deco = (struct caam_deco __iomem __force *)
1007 ((__force uint8_t *)ctrl +
1008 BLOCK_OFFSET * DECO_BLOCK_NUMBER
1009 );
1010
1011 /* Get the IRQ of the controller (for security violations only) */
1012 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
1013 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
1014 ctrlpriv->mc_en = !!np;
1015 of_node_put(np);
1016
1017#ifdef CONFIG_FSL_MC_BUS
1018 if (ctrlpriv->mc_en) {
1019 struct fsl_mc_version *mc_version;
1020
1021 mc_version = fsl_mc_get_version();
1022 if (mc_version)
1023 ctrlpriv->pr_support = check_version(mc_version, 10, 20,
1024 0);
1025 else
1026 return -EPROBE_DEFER;
1027 }
1028#endif
1029
1030 if (!reg_access)
1031 goto set_dma_mask;
1032
1033 /*
1034 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
1035 * long pointers in master configuration register.
1036 * In case of SoCs with Management Complex, MC f/w performs
1037 * the configuration.
1038 */
1039 if (!ctrlpriv->mc_en)
1040 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
1041 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
1042 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
1043
1044 handle_imx6_err005766(&ctrl->mcr);
1045
1046 /*
1047 * Read the Compile Time parameters and SCFGR to determine
1048 * if virtualization is enabled for this platform
1049 */
1050 scfgr = rd_reg32(&ctrl->scfgr);
1051
1052 ctrlpriv->virt_en = 0;
1053 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
1054 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
1055 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
1056 */
1057 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
1058 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
1059 (scfgr & SCFGR_VIRT_EN)))
1060 ctrlpriv->virt_en = 1;
1061 } else {
1062 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
1063 if (comp_params & CTPR_MS_VIRT_EN_POR)
1064 ctrlpriv->virt_en = 1;
1065 }
1066
1067 if (ctrlpriv->virt_en == 1)
1068 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
1069 JRSTART_JR1_START | JRSTART_JR2_START |
1070 JRSTART_JR3_START);
1071
1072set_dma_mask:
1073 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
1074 if (ret) {
1075 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
1076 return ret;
1077 }
1078
1079 ctrlpriv->era = caam_get_era(perfmon);
1080 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
1081
1082 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
1083 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1084 ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
1085 dfs_root);
1086 if (ret)
1087 return ret;
1088 }
1089
1090 caam_debugfs_init(ctrlpriv, perfmon, dfs_root);
1091
1092 /* Check to see if (DPAA 1.x) QI present. If so, enable */
1093 if (ctrlpriv->qi_present && !caam_dpaa2) {
1094 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
1095 ((__force uint8_t *)ctrl +
1096 BLOCK_OFFSET * QI_BLOCK_NUMBER
1097 );
1098 /* This is all that's required to physically enable QI */
1099 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
1100
1101 /* If QMAN driver is present, init CAAM-QI backend */
1102#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
1103 ret = caam_qi_init(pdev);
1104 if (ret)
1105 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
1106#endif
1107 }
1108
1109 /* If no QI and no rings specified, quit and go home */
1110 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
1111 dev_err(dev, "no queues configured, terminating\n");
1112 return -ENOMEM;
1113 }
1114
1115 comp_params = rd_reg32(&perfmon->comp_parms_ls);
1116 ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);
1117
1118 /*
1119 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,
1120 * but fail when actually using it due to missing AES support, so
1121 * check both here.
1122 */
1123 if (ctrlpriv->era < 10) {
1124 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1125 (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);
1126 } else {
1127 struct version_regs __iomem *vreg;
1128
1129 vreg = ctrlpriv->total_jobrs ?
1130 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
1131 (struct version_regs __iomem *)&ctrl->vreg;
1132
1133 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1134 (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);
1135 }
1136
1137 if (reg_access) {
1138 ret = caam_ctrl_rng_init(dev);
1139 if (ret)
1140 return ret;
1141 }
1142
1143 caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
1144 (u64)rd_reg32(&perfmon->caam_id_ls);
1145
1146 /* Report "alive" for developer to see */
1147 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
1148 ctrlpriv->era);
1149 dev_info(dev, "job rings = %d, qi = %d\n",
1150 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
1151
1152 ret = devm_of_platform_populate(dev);
1153 if (ret)
1154 dev_err(dev, "JR platform devices creation error\n");
1155
1156 return ret;
1157}
1158
1159static struct platform_driver caam_driver = {
1160 .driver = {
1161 .name = "caam",
1162 .of_match_table = caam_match,
1163 .pm = pm_ptr(&caam_ctrl_pm_ops),
1164 },
1165 .probe = caam_probe,
1166};
1167
1168module_platform_driver(caam_driver);
1169
1170MODULE_LICENSE("GPL");
1171MODULE_DESCRIPTION("FSL CAAM request backend");
1172MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");