| 1 | |
| 2 | |
| 3 | * AMD Platform Security Processor (PSP) interface
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| 4 | *
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| 5 | * Copyright (C) 2016,2019 Advanced Micro Devices, Inc.
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| 6 | *
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| 7 | * Author: Brijesh Singh <[email protected]>
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| 8 |
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| 9 |
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| 10 | #include <linux/kernel.h>
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| 11 | #include <linux/irqreturn.h>
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| 12 | #include <linux/mutex.h>
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| 13 | #include <linux/bitfield.h>
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| 14 | #include <linux/delay.h>
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| 15 |
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| 16 | #include "sp-dev.h"
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| 17 | #include "psp-dev.h"
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| 18 | #include "sev-dev.h"
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| 19 | #include "tee-dev.h"
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| 20 | #include "sfs.h"
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| 21 | #include "platform-access.h"
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| 22 | #include "dbc.h"
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| 23 | #include "hsti.h"
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| 24 |
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| 25 | struct psp_device *psp_master;
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| 26 |
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| 27 | #define PSP_C2PMSG_17_CMDRESP_CMD GENMASK(19, 16)
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| 28 |
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| 29 | static int psp_mailbox_poll(const void __iomem *cmdresp_reg, unsigned int *cmdresp,
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| 30 | unsigned int timeout_msecs)
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| 31 | {
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| 32 | while (true) {
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| 33 | *cmdresp = ioread32(cmdresp_reg);
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| 34 | if (FIELD_GET(PSP_CMDRESP_RESP, *cmdresp))
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| 35 | return 0;
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| 36 |
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| 37 | if (!timeout_msecs--)
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| 38 | break;
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| 39 |
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| 40 | usleep_range(1000, 1100);
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| 41 | }
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| 42 |
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| 43 | return -ETIMEDOUT;
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| 44 | }
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| 45 |
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| 46 | int psp_mailbox_command(struct psp_device *psp, enum psp_cmd cmd, void *cmdbuff,
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| 47 | unsigned int timeout_msecs, unsigned int *cmdresp)
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| 48 | {
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| 49 | void __iomem *cmdresp_reg, *cmdbuff_lo_reg, *cmdbuff_hi_reg;
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| 50 | int ret;
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| 51 |
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| 52 | if (!psp || !psp->vdata || !psp->vdata->cmdresp_reg ||
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| 53 | !psp->vdata->cmdbuff_addr_lo_reg || !psp->vdata->cmdbuff_addr_hi_reg)
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| 54 | return -ENODEV;
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| 55 |
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| 56 | cmdresp_reg = psp->io_regs + psp->vdata->cmdresp_reg;
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| 57 | cmdbuff_lo_reg = psp->io_regs + psp->vdata->cmdbuff_addr_lo_reg;
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| 58 | cmdbuff_hi_reg = psp->io_regs + psp->vdata->cmdbuff_addr_hi_reg;
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| 59 |
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| 60 | mutex_lock(&psp->mailbox_mutex);
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| 61 |
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| 62 |
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| 63 | ret = -EBUSY;
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| 64 | if (psp_mailbox_poll(cmdresp_reg, cmdresp, 0))
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| 65 | goto unlock;
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| 66 |
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| 67 | if (cmdbuff) {
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| 68 | iowrite32(lower_32_bits(__psp_pa(cmdbuff)), cmdbuff_lo_reg);
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| 69 | iowrite32(upper_32_bits(__psp_pa(cmdbuff)), cmdbuff_hi_reg);
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| 70 | }
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| 71 |
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| 72 | *cmdresp = FIELD_PREP(PSP_C2PMSG_17_CMDRESP_CMD, cmd);
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| 73 | iowrite32(*cmdresp, cmdresp_reg);
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| 74 |
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| 75 | ret = psp_mailbox_poll(cmdresp_reg, cmdresp, timeout_msecs);
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| 76 |
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| 77 | unlock:
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| 78 | mutex_unlock(&psp->mailbox_mutex);
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| 79 |
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| 80 | return ret;
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| 81 | }
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| 82 |
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| 83 | int psp_extended_mailbox_cmd(struct psp_device *psp, unsigned int timeout_msecs,
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| 84 | struct psp_ext_request *req)
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| 85 | {
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| 86 | unsigned int reg;
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| 87 | int ret;
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| 88 |
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| 89 | print_hex_dump_debug("->psp ", DUMP_PREFIX_OFFSET, 16, 2, req,
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| 90 | req->header.payload_size, false);
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| 91 |
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| 92 | ret = psp_mailbox_command(psp, PSP_CMD_TEE_EXTENDED_CMD, (void *)req,
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| 93 | timeout_msecs, ®);
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| 94 | if (ret) {
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| 95 | return ret;
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| 96 | } else if (FIELD_GET(PSP_CMDRESP_STS, reg)) {
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| 97 | req->header.status = FIELD_GET(PSP_CMDRESP_STS, reg);
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| 98 | return -EIO;
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| 99 | }
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| 100 |
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| 101 | print_hex_dump_debug("<-psp ", DUMP_PREFIX_OFFSET, 16, 2, req,
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| 102 | req->header.payload_size, false);
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| 103 |
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| 104 | return 0;
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| 105 | }
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| 106 |
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| 107 | static struct psp_device *psp_alloc_struct(struct sp_device *sp)
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| 108 | {
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| 109 | struct device *dev = sp->dev;
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| 110 | struct psp_device *psp;
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| 111 |
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| 112 | psp = devm_kzalloc(dev, sizeof(*psp), GFP_KERNEL);
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| 113 | if (!psp)
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| 114 | return NULL;
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| 115 |
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| 116 | psp->dev = dev;
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| 117 | psp->sp = sp;
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| 118 |
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| 119 | snprintf(psp->name, sizeof(psp->name), "psp-%u", sp->ord);
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| 120 |
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| 121 | return psp;
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| 122 | }
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| 123 |
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| 124 | static irqreturn_t psp_irq_handler(int irq, void *data)
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| 125 | {
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| 126 | struct psp_device *psp = data;
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| 127 | unsigned int status;
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| 128 |
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| 129 |
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| 130 | status = ioread32(psp->io_regs + psp->vdata->intsts_reg);
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| 131 |
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| 132 |
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| 133 | iowrite32(status, psp->io_regs + psp->vdata->intsts_reg);
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| 134 |
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| 135 |
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| 136 | if (status) {
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| 137 | if (psp->sev_irq_handler)
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| 138 | psp->sev_irq_handler(irq, psp->sev_irq_data, status);
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| 139 | }
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| 140 |
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| 141 | return IRQ_HANDLED;
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| 142 | }
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| 143 |
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| 144 | static unsigned int psp_get_capability(struct psp_device *psp)
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| 145 | {
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| 146 | unsigned int val = ioread32(psp->io_regs + psp->vdata->feature_reg);
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| 147 |
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| 148 | |
| 149 | * Check for a access to the registers. If this read returns
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| 150 | * 0xffffffff, it's likely that the system is running a broken
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| 151 | * BIOS which disallows access to the device. Stop here and
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| 152 | * fail the PSP initialization (but not the load, as the CCP
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| 153 | * could get properly initialized).
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| 154 |
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| 155 | if (val == 0xffffffff) {
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| 156 | dev_notice(psp->dev, "psp: unable to access the device: you might be running a broken BIOS.\n");
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| 157 | return -ENODEV;
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| 158 | }
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| 159 | psp->capability.raw = val;
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| 160 |
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| 161 | return 0;
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| 162 | }
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| 163 |
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| 164 | static int psp_check_sev_support(struct psp_device *psp)
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| 165 | {
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| 166 |
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| 167 | if (!psp->capability.sev) {
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| 168 | dev_dbg(psp->dev, "psp does not support SEV\n");
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| 169 | return -ENODEV;
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| 170 | }
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| 171 |
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| 172 | return 0;
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| 173 | }
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| 174 |
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| 175 | static int psp_check_tee_support(struct psp_device *psp)
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| 176 | {
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| 177 |
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| 178 | if (!psp->capability.tee) {
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| 179 | dev_dbg(psp->dev, "psp does not support TEE\n");
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| 180 | return -ENODEV;
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| 181 | }
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| 182 |
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| 183 | return 0;
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| 184 | }
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| 185 |
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| 186 | static int psp_check_sfs_support(struct psp_device *psp)
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| 187 | {
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| 188 |
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| 189 | if (!psp->capability.sfs) {
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| 190 | dev_dbg(psp->dev, "psp does not support SFS\n");
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| 191 | return -ENODEV;
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| 192 | }
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| 193 |
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| 194 | return 0;
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| 195 | }
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| 196 |
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| 197 | static int psp_init(struct psp_device *psp)
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| 198 | {
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| 199 | int ret;
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| 200 |
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| 201 | if (!psp_check_sev_support(psp)) {
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| 202 | ret = sev_dev_init(psp);
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| 203 | if (ret)
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| 204 | return ret;
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| 205 | }
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| 206 |
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| 207 | if (!psp_check_tee_support(psp)) {
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| 208 | ret = tee_dev_init(psp);
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| 209 | if (ret)
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| 210 | return ret;
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| 211 | }
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| 212 |
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| 213 | if (!psp_check_sfs_support(psp)) {
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| 214 | ret = sfs_dev_init(psp);
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| 215 | if (ret)
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| 216 | return ret;
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| 217 | }
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| 218 |
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| 219 | if (psp->vdata->platform_access) {
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| 220 | ret = platform_access_dev_init(psp);
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| 221 | if (ret)
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| 222 | return ret;
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| 223 | }
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| 224 |
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| 225 |
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| 226 | if (PSP_FEATURE(psp, DBC) ||
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| 227 | psp->capability.dbc_thru_ext) {
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| 228 | ret = dbc_dev_init(psp);
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| 229 | if (ret)
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| 230 | return ret;
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| 231 | }
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| 232 |
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| 233 |
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| 234 | ret = psp_init_hsti(psp);
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| 235 | if (ret)
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| 236 | return ret;
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| 237 |
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| 238 | return 0;
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| 239 | }
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| 240 |
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| 241 | int psp_dev_init(struct sp_device *sp)
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| 242 | {
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| 243 | struct device *dev = sp->dev;
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| 244 | struct psp_device *psp;
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| 245 | int ret;
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| 246 |
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| 247 | ret = -ENOMEM;
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| 248 | psp = psp_alloc_struct(sp);
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| 249 | if (!psp)
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| 250 | goto e_err;
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| 251 |
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| 252 | sp->psp_data = psp;
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| 253 |
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| 254 | psp->vdata = (struct psp_vdata *)sp->dev_vdata->psp_vdata;
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| 255 | if (!psp->vdata) {
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| 256 | ret = -ENODEV;
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| 257 | dev_err(dev, "missing driver data\n");
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| 258 | goto e_err;
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| 259 | }
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| 260 |
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| 261 | psp->io_regs = sp->io_map;
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| 262 | mutex_init(&psp->mailbox_mutex);
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| 263 |
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| 264 | ret = psp_get_capability(psp);
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| 265 | if (ret)
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| 266 | goto e_disable;
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| 267 |
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| 268 |
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| 269 | iowrite32(0, psp->io_regs + psp->vdata->inten_reg);
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| 270 | iowrite32(-1, psp->io_regs + psp->vdata->intsts_reg);
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| 271 |
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| 272 |
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| 273 | ret = sp_request_psp_irq(psp->sp, psp_irq_handler, psp->name, psp);
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| 274 | if (ret) {
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| 275 | dev_err(dev, "psp: unable to allocate an IRQ\n");
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| 276 | goto e_err;
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| 277 | }
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| 278 |
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| 279 |
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| 280 | if (psp->sp->set_psp_master_device)
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| 281 | psp->sp->set_psp_master_device(psp->sp);
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| 282 |
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| 283 | ret = psp_init(psp);
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| 284 | if (ret)
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| 285 | goto e_irq;
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| 286 |
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| 287 |
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| 288 | iowrite32(-1, psp->io_regs + psp->vdata->inten_reg);
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| 289 |
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| 290 | dev_notice(dev, "psp enabled\n");
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| 291 |
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| 292 | return 0;
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| 293 |
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| 294 | e_irq:
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| 295 | if (sp->clear_psp_master_device)
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| 296 | sp->clear_psp_master_device(sp);
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| 297 |
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| 298 | sp_free_psp_irq(psp->sp, psp);
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| 299 | e_err:
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| 300 | sp->psp_data = NULL;
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| 301 |
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| 302 | dev_notice(dev, "psp initialization failed\n");
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| 303 |
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| 304 | return ret;
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| 305 |
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| 306 | e_disable:
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| 307 | sp->psp_data = NULL;
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| 308 |
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| 309 | return ret;
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| 310 | }
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| 311 |
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| 312 | void psp_dev_destroy(struct sp_device *sp)
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| 313 | {
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| 314 | struct psp_device *psp = sp->psp_data;
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| 315 |
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| 316 | if (!psp)
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| 317 | return;
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| 318 |
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| 319 | dbc_dev_destroy(psp);
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| 320 |
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| 321 | platform_access_dev_destroy(psp);
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| 322 |
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| 323 | sfs_dev_destroy(psp);
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| 324 |
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| 325 | tee_dev_destroy(psp);
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| 326 |
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| 327 | sev_dev_destroy(psp);
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| 328 |
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| 329 | sp_free_psp_irq(sp, psp);
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| 330 |
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| 331 | if (sp->clear_psp_master_device)
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| 332 | sp->clear_psp_master_device(sp);
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| 333 | }
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| 334 |
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| 335 | void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
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| 336 | void *data)
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| 337 | {
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| 338 | psp->sev_irq_data = data;
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| 339 | psp->sev_irq_handler = handler;
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| 340 | }
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| 341 |
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| 342 | void psp_clear_sev_irq_handler(struct psp_device *psp)
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| 343 | {
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| 344 | psp_set_sev_irq_handler(psp, NULL, NULL);
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| 345 | }
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| 346 |
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| 347 | struct psp_device *psp_get_master_device(void)
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| 348 | {
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| 349 | struct sp_device *sp = sp_get_psp_master_device();
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| 350 |
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| 351 | return sp ? sp->psp_data : NULL;
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| 352 | }
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| 353 |
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| 354 | int psp_restore(struct sp_device *sp)
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| 355 | {
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| 356 | struct psp_device *psp = sp->psp_data;
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| 357 | int ret = 0;
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| 358 |
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| 359 | if (psp->tee_data)
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| 360 | ret = tee_restore(psp);
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| 361 |
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| 362 | return ret;
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| 363 | }
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| 364 |
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| 365 | void psp_pci_init(void)
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| 366 | {
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| 367 | psp_master = psp_get_master_device();
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| 368 |
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| 369 | if (!psp_master)
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| 370 | return;
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| 371 |
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| 372 | sev_pci_init();
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| 373 | }
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| 374 |
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| 375 | void psp_pci_exit(void)
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| 376 | {
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| 377 | if (!psp_master)
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| 378 | return;
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| 379 |
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| 380 | sev_pci_exit();
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| 381 | }
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