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1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
3 * Freescale SEC (talitos) device register and descriptor header defines
4 *
5 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
6 */
7
8#define TALITOS_TIMEOUT 100000
9#define TALITOS1_MAX_DATA_LEN 32768
10#define TALITOS2_MAX_DATA_LEN 65535
11
12#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
13#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
14#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
15
16/* descriptor pointer entry */
17struct talitos_ptr {
18 union {
19 struct { /* SEC2 format */
20 __be16 len; /* length */
21 u8 j_extent; /* jump to sg link table and/or extent*/
22 u8 eptr; /* extended address */
23 };
24 struct { /* SEC1 format */
25 __be16 res;
26 __be16 len1; /* length */
27 };
28 };
29 __be32 ptr; /* address */
30};
31
32/* descriptor */
33struct talitos_desc {
34 __be32 hdr; /* header high bits */
35 union {
36 __be32 hdr_lo; /* header low bits */
37 __be32 hdr1; /* header for SEC1 */
38 };
39 struct talitos_ptr ptr[7]; /* ptr/len pair array */
40 __be32 next_desc; /* next descriptor (SEC1) */
41};
42
43#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
44
45/*
46 * talitos_edesc - s/w-extended descriptor
47 * @bufsl: scatterlist buffer
48 * @src: pointer to input scatterlist
49 * @first: first descriptor of a chain
50 * @last: last descriptor of a chain
51 *
52 * @src_nents: number of segments in input scatterlist
53 * @dst_nents: number of segments in output scatterlist
54 * @iv_dma: dma address of iv for checking continuity and link table
55 * @dma_len: length of dma mapped link_tbl space
56 * @dma_link_tbl: bus physical address of link_tbl/buf
57 * @next_desc: next descriptor
58 * @desc: h/w descriptor
59 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
60 * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
61 *
62 * if decrypting (with authcheck), or either one of src_nents or dst_nents
63 * is greater than 1, an integrity check value is concatenated to the end
64 * of link_tbl data
65 */
66struct talitos_edesc {
67 struct scatterlist bufsl[2];
68 struct scatterlist *src;
69 int first;
70 int last;
71
72 int src_nents;
73 int dst_nents;
74 dma_addr_t iv_dma;
75 int dma_len;
76 dma_addr_t dma_link_tbl;
77 struct talitos_edesc *next_desc;
78 struct talitos_desc desc;
79 union {
80 DECLARE_FLEX_ARRAY(struct talitos_ptr, link_tbl);
81 DECLARE_FLEX_ARRAY(u8, buf);
82 };
83};
84
85/**
86 * talitos_request - descriptor submission request
87 * @desc: descriptor pointer (kernel virtual)
88 * @dma_desc: descriptor's physical bus address
89 * @callback: whom to call when descriptor processing is done
90 * @context: caller context (optional)
91 */
92struct talitos_request {
93 struct talitos_desc *desc;
94 dma_addr_t dma_desc;
95 void (*callback) (struct device *dev, struct talitos_desc *desc,
96 void *context, int error);
97 void *context;
98};
99
100/* per-channel fifo management */
101struct talitos_channel {
102 void __iomem *reg;
103
104 /* request fifo */
105 struct talitos_request *fifo;
106
107 /* number of requests pending in channel h/w fifo */
108 atomic_t submit_count ____cacheline_aligned;
109
110 /* request submission (head) lock */
111 spinlock_t head_lock ____cacheline_aligned;
112 /* index to next free descriptor request */
113 int head;
114
115 /* request release (tail) lock */
116 spinlock_t tail_lock ____cacheline_aligned;
117 /* index to next in-progress/done descriptor request */
118 int tail;
119};
120
121struct talitos_private {
122 struct device *dev;
123 struct platform_device *ofdev;
124 void __iomem *reg;
125 void __iomem *reg_deu;
126 void __iomem *reg_aesu;
127 void __iomem *reg_mdeu;
128 void __iomem *reg_afeu;
129 void __iomem *reg_rngu;
130 void __iomem *reg_pkeu;
131 void __iomem *reg_keu;
132 void __iomem *reg_crcu;
133 int irq[2];
134
135 /* SEC global registers lock */
136 spinlock_t reg_lock ____cacheline_aligned;
137
138 /* SEC version geometry (from device tree node) */
139 unsigned int num_channels;
140 unsigned int chfifo_len;
141 unsigned int exec_units;
142 unsigned int desc_types;
143
144 /* SEC Compatibility info */
145 unsigned long features;
146
147 /*
148 * length of the request fifo
149 * fifo_len is chfifo_len rounded up to next power of 2
150 * so we can use bitwise ops to wrap
151 */
152 unsigned int fifo_len;
153
154 /* next channel to be assigned next incoming descriptor */
155 atomic_t last_chan ____cacheline_aligned;
156
157 /* request callback tasklet */
158 struct tasklet_struct done_task[2];
159
160 /* list of registered algorithms */
161 struct list_head alg_list;
162
163 /* hwrng device */
164 struct hwrng rng;
165 bool rng_registered;
166
167 struct talitos_channel chan[] __counted_by(num_channels);
168
169};
170
171/* .features flag */
172#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
173#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
174#define TALITOS_FTR_SHA224_HWINIT 0x00000004
175#define TALITOS_FTR_HMAC_OK 0x00000008
176#define TALITOS_FTR_SEC1 0x00000010
177
178/*
179 * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
180 * defined, we check the features which are set according to the device tree.
181 * Otherwise, we answer true or false directly
182 */
183static inline bool has_ftr_sec1(struct talitos_private *priv)
184{
185 if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) &&
186 IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2))
187 return priv->features & TALITOS_FTR_SEC1;
188
189 return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
190}
191
192/*
193 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
194 */
195
196#define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16))
197#define ISR2_FORMAT(x) (((x) << 4) | (x))
198
199/* global register offset addresses */
200#define TALITOS_MCR 0x1030 /* master control register */
201#define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
202#define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
203#define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
204#define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
205#define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */
206#define TALITOS2_MCR_SWR 0x1 /* s/w reset */
207#define TALITOS_MCR_LO 0x1034
208#define TALITOS_IMR 0x1008 /* interrupt mask register */
209/* enable channel IRQs */
210#define TALITOS1_IMR_INIT ISR1_FORMAT(0xf)
211#define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
212/* enable channel IRQs */
213#define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000)
214#define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
215#define TALITOS_IMR_LO 0x100C
216#define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */
217#define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
218#define TALITOS_ISR 0x1010 /* interrupt status register */
219#define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */
220#define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */
221#define TALITOS1_ISR_CH_0_ERR (2 << 28) /* ch 0 errors mask */
222#define TALITOS1_ISR_CH_0_DONE (1 << 28) /* ch 0 done mask */
223#define TALITOS1_ISR_TEA_ERR 0x00000040
224#define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */
225#define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */
226#define TALITOS2_ISR_CH_0_ERR 2 /* ch 0 errors mask */
227#define TALITOS2_ISR_CH_0_DONE 1 /* ch 0 done mask */
228#define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
229#define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
230#define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
231#define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
232#define TALITOS_ISR_LO 0x1014
233#define TALITOS_ICR 0x1018 /* interrupt clear register */
234#define TALITOS_ICR_LO 0x101C
235
236/* channel register address stride */
237#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
238#define TALITOS1_CH_STRIDE 0x1000
239#define TALITOS2_CH_STRIDE 0x100
240
241/* channel configuration register */
242#define TALITOS_CCCR 0x8
243#define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */
244#define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */
245#define TALITOS_CCCR_LO 0xc
246#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
247#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
248#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
249#define TALITOS_CCCR_LO_NE 0x8 /* fetch next descriptor enab. */
250#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
251#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
252#define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
253
254/* CCPSR: channel pointer status register */
255#define TALITOS_CCPSR 0x10
256#define TALITOS_CCPSR_LO 0x14
257#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
258#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
259#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
260#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
261#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
262#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
263#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
264#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
265#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
266#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
267#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
268#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
269
270/* channel fetch fifo register */
271#define TALITOS_FF 0x48
272#define TALITOS_FF_LO 0x4c
273
274/* current descriptor pointer register */
275#define TALITOS_CDPR 0x40
276#define TALITOS_CDPR_LO 0x44
277
278/* descriptor buffer register */
279#define TALITOS_DESCBUF 0x80
280#define TALITOS_DESCBUF_LO 0x84
281
282/* gather link table */
283#define TALITOS_GATHER 0xc0
284#define TALITOS_GATHER_LO 0xc4
285
286/* scatter link table */
287#define TALITOS_SCATTER 0xe0
288#define TALITOS_SCATTER_LO 0xe4
289
290/* execution unit registers base */
291#define TALITOS2_DEU 0x2000
292#define TALITOS2_AESU 0x4000
293#define TALITOS2_MDEU 0x6000
294#define TALITOS2_AFEU 0x8000
295#define TALITOS2_RNGU 0xa000
296#define TALITOS2_PKEU 0xc000
297#define TALITOS2_KEU 0xe000
298#define TALITOS2_CRCU 0xf000
299
300#define TALITOS12_AESU 0x4000
301#define TALITOS12_DEU 0x5000
302#define TALITOS12_MDEU 0x6000
303
304#define TALITOS10_AFEU 0x8000
305#define TALITOS10_DEU 0xa000
306#define TALITOS10_MDEU 0xc000
307#define TALITOS10_RNGU 0xe000
308#define TALITOS10_PKEU 0x10000
309#define TALITOS10_AESU 0x12000
310
311/* execution unit interrupt status registers */
312#define TALITOS_EUDSR 0x10 /* data size */
313#define TALITOS_EUDSR_LO 0x14
314#define TALITOS_EURCR 0x18 /* reset control*/
315#define TALITOS_EURCR_LO 0x1c
316#define TALITOS_EUSR 0x28 /* rng status */
317#define TALITOS_EUSR_LO 0x2c
318#define TALITOS_EUISR 0x30
319#define TALITOS_EUISR_LO 0x34
320#define TALITOS_EUICR 0x38 /* int. control */
321#define TALITOS_EUICR_LO 0x3c
322#define TALITOS_EU_FIFO 0x800 /* output FIFO */
323#define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */
324/* DES unit */
325#define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */
326/* message digest unit */
327#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
328/* random number unit */
329#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
330#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
331#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
332
333#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
334#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
335
336/*
337 * talitos descriptor header (hdr) bits
338 */
339
340/* written back when done */
341#define DESC_HDR_DONE cpu_to_be32(0xff000000)
342#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
343#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
344#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
345
346/* primary execution unit select */
347#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
348#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
349#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
350#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
351#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
352#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
353#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
354#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
355#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
356#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
357
358/* primary execution unit mode (MODE0) and derivatives */
359#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
360#define DESC_HDR_MODE0_AESU_MASK cpu_to_be32(0x00600000)
361#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
362#define DESC_HDR_MODE0_AESU_CTR cpu_to_be32(0x00600000)
363#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
364#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
365#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
366#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
367#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
368#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
369#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
370#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
371#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
372#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
373#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
374#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
375#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
376 DESC_HDR_MODE0_MDEU_HMAC)
377#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
378 DESC_HDR_MODE0_MDEU_HMAC)
379#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
380 DESC_HDR_MODE0_MDEU_HMAC)
381
382/* secondary execution unit select (SEL1) */
383#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
384#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
385#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
386#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
387
388/* secondary execution unit mode (MODE1) and derivatives */
389#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
390#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
391#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
392#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
393#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
394#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
395#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
396#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
397#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
398#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
399#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
400 DESC_HDR_MODE1_MDEU_HMAC)
401#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
402 DESC_HDR_MODE1_MDEU_HMAC)
403#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
404 DESC_HDR_MODE1_MDEU_HMAC)
405#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
406 DESC_HDR_MODE1_MDEU_HMAC)
407#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
408 DESC_HDR_MODE1_MDEU_HMAC)
409#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
410 DESC_HDR_MODE1_MDEU_HMAC)
411
412/* direction of overall data flow (DIR) */
413#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
414
415/* request done notification (DN) */
416#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
417
418/* descriptor types */
419#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
420#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
421#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
422#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
423
424/* link table extent field bits */
425#define DESC_PTR_LNKTBL_JUMP 0x80
426#define DESC_PTR_LNKTBL_RET 0x02
427#define DESC_PTR_LNKTBL_NEXT 0x01