| 1 |
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| 2 | |
| 3 | * rt8973a.h
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| 4 | *
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| 5 | * Copyright (c) 2014 Samsung Electronics Co., Ltd
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| 6 |
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| 7 |
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| 8 | #ifndef __LINUX_EXTCON_RT8973A_H
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| 9 | #define __LINUX_EXTCON_RT8973A_H
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| 10 |
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| 11 | enum rt8973a_types {
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| 12 | TYPE_RT8973A,
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| 13 | };
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| 14 |
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| 15 |
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| 16 | enum rt8973A_reg {
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| 17 | RT8973A_REG_DEVICE_ID = 0x1,
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| 18 | RT8973A_REG_CONTROL1,
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| 19 | RT8973A_REG_INT1,
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| 20 | RT8973A_REG_INT2,
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| 21 | RT8973A_REG_INTM1,
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| 22 | RT8973A_REG_INTM2,
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| 23 | RT8973A_REG_ADC,
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| 24 | RT8973A_REG_RSVD_1,
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| 25 | RT8973A_REG_RSVD_2,
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| 26 | RT8973A_REG_DEV1,
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| 27 | RT8973A_REG_DEV2,
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| 28 | RT8973A_REG_RSVD_3,
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| 29 | RT8973A_REG_RSVD_4,
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| 30 | RT8973A_REG_RSVD_5,
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| 31 | RT8973A_REG_RSVD_6,
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| 32 | RT8973A_REG_RSVD_7,
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| 33 | RT8973A_REG_RSVD_8,
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| 34 | RT8973A_REG_RSVD_9,
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| 35 | RT8973A_REG_MANUAL_SW1,
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| 36 | RT8973A_REG_MANUAL_SW2,
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| 37 | RT8973A_REG_RSVD_10,
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| 38 | RT8973A_REG_RSVD_11,
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| 39 | RT8973A_REG_RSVD_12,
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| 40 | RT8973A_REG_RSVD_13,
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| 41 | RT8973A_REG_RSVD_14,
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| 42 | RT8973A_REG_RSVD_15,
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| 43 | RT8973A_REG_RESET,
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| 44 |
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| 45 | RT8973A_REG_END,
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| 46 | };
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| 47 |
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| 48 |
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| 49 | #define RT8973A_REG_DEVICE_ID_VENDOR_SHIFT 0
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| 50 | #define RT8973A_REG_DEVICE_ID_VERSION_SHIFT 3
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| 51 | #define RT8973A_REG_DEVICE_ID_VENDOR_MASK (0x7 << RT8973A_REG_DEVICE_ID_VENDOR_SHIFT)
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| 52 | #define RT8973A_REG_DEVICE_ID_VERSION_MASK (0x1f << RT8973A_REG_DEVICE_ID_VERSION_SHIFT)
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| 53 |
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| 54 | #define RT8973A_REG_CONTROL1_INTM_SHIFT 0
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| 55 | #define RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT 2
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| 56 | #define RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT 3
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| 57 | #define RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT 4
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| 58 | #define RT8973A_REG_CONTROL1_CHGTYP_SHIFT 5
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| 59 | #define RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT 6
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| 60 | #define RT8973A_REG_CONTROL1_ADC_EN_SHIFT 7
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| 61 | #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT)
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| 62 | #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT)
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| 63 | #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT)
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| 64 | #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT)
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| 65 | #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT)
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| 66 | #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT)
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| 67 | #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT)
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| 68 |
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| 69 | #define RT9873A_REG_INTM1_ATTACH_SHIFT 0
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| 70 | #define RT9873A_REG_INTM1_DETACH_SHIFT 1
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| 71 | #define RT9873A_REG_INTM1_CHGDET_SHIFT 2
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| 72 | #define RT9873A_REG_INTM1_DCD_T_SHIFT 3
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| 73 | #define RT9873A_REG_INTM1_OVP_SHIFT 4
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| 74 | #define RT9873A_REG_INTM1_CONNECT_SHIFT 5
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| 75 | #define RT9873A_REG_INTM1_ADC_CHG_SHIFT 6
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| 76 | #define RT9873A_REG_INTM1_OTP_SHIFT 7
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| 77 | #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT)
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| 78 | #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIFT)
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| 79 | #define RT9873A_REG_INTM1_CHGDET_MASK (0x1 << RT9873A_REG_INTM1_CHGDET_SHIFT)
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| 80 | #define RT9873A_REG_INTM1_DCD_T_MASK (0x1 << RT9873A_REG_INTM1_DCD_T_SHIFT)
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| 81 | #define RT9873A_REG_INTM1_OVP_MASK (0x1 << RT9873A_REG_INTM1_OVP_SHIFT)
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| 82 | #define RT9873A_REG_INTM1_CONNECT_MASK (0x1 << RT9873A_REG_INTM1_CONNECT_SHIFT)
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| 83 | #define RT9873A_REG_INTM1_ADC_CHG_MASK (0x1 << RT9873A_REG_INTM1_ADC_CHG_SHIFT)
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| 84 | #define RT9873A_REG_INTM1_OTP_MASK (0x1 << RT9873A_REG_INTM1_OTP_SHIFT)
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| 85 |
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| 86 | #define RT9873A_REG_INTM2_UVLO_SHIFT 1
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| 87 | #define RT9873A_REG_INTM2_POR_SHIFT 2
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| 88 | #define RT9873A_REG_INTM2_OTP_FET_SHIFT 3
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| 89 | #define RT9873A_REG_INTM2_OVP_FET_SHIFT 4
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| 90 | #define RT9873A_REG_INTM2_OCP_LATCH_SHIFT 5
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| 91 | #define RT9873A_REG_INTM2_OCP_SHIFT 6
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| 92 | #define RT9873A_REG_INTM2_OVP_OCP_SHIFT 7
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| 93 | #define RT9873A_REG_INTM2_UVLO_MASK (0x1 << RT9873A_REG_INTM2_UVLO_SHIFT)
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| 94 | #define RT9873A_REG_INTM2_POR_MASK (0x1 << RT9873A_REG_INTM2_POR_SHIFT)
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| 95 | #define RT9873A_REG_INTM2_OTP_FET_MASK (0x1 << RT9873A_REG_INTM2_OTP_FET_SHIFT)
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| 96 | #define RT9873A_REG_INTM2_OVP_FET_MASK (0x1 << RT9873A_REG_INTM2_OVP_FET_SHIFT)
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| 97 | #define RT9873A_REG_INTM2_OCP_LATCH_MASK (0x1 << RT9873A_REG_INTM2_OCP_LATCH_SHIFT)
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| 98 | #define RT9873A_REG_INTM2_OCP_MASK (0x1 << RT9873A_REG_INTM2_OCP_SHIFT)
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| 99 | #define RT9873A_REG_INTM2_OVP_OCP_MASK (0x1 << RT9873A_REG_INTM2_OVP_OCP_SHIFT)
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| 100 |
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| 101 | #define RT8973A_REG_ADC_SHIFT 0
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| 102 | #define RT8973A_REG_ADC_MASK (0x1f << RT8973A_REG_ADC_SHIFT)
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| 103 |
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| 104 | #define RT8973A_REG_DEV1_OTG_SHIFT 0
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| 105 | #define RT8973A_REG_DEV1_SDP_SHIFT 2
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| 106 | #define RT8973A_REG_DEV1_UART_SHIFT 3
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| 107 | #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT 4
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| 108 | #define RT8973A_REG_DEV1_CDPORT_SHIFT 5
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| 109 | #define RT8973A_REG_DEV1_DCPORT_SHIFT 6
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| 110 | #define RT8973A_REG_DEV1_OTG_MASK (0x1 << RT8973A_REG_DEV1_OTG_SHIFT)
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| 111 | #define RT8973A_REG_DEV1_SDP_MASK (0x1 << RT8973A_REG_DEV1_SDP_SHIFT)
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| 112 | #define RT8973A_REG_DEV1_UART_MASK (0x1 << RT8973A_REG_DEV1_UART_SHIFT)
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| 113 | #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK (0x1 << RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT)
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| 114 | #define RT8973A_REG_DEV1_CDPORT_MASK (0x1 << RT8973A_REG_DEV1_CDPORT_SHIFT)
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| 115 | #define RT8973A_REG_DEV1_DCPORT_MASK (0x1 << RT8973A_REG_DEV1_DCPORT_SHIFT)
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| 116 | #define RT8973A_REG_DEV1_USB_MASK (RT8973A_REG_DEV1_SDP_MASK \
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| 117 | | RT8973A_REG_DEV1_CDPORT_MASK)
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| 118 |
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| 119 | #define RT8973A_REG_DEV2_JIG_USB_ON_SHIFT 0
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| 120 | #define RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT 1
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| 121 | #define RT8973A_REG_DEV2_JIG_UART_ON_SHIFT 2
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| 122 | #define RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT 3
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| 123 | #define RT8973A_REG_DEV2_JIG_USB_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_ON_SHIFT)
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| 124 | #define RT8973A_REG_DEV2_JIG_USB_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT)
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| 125 | #define RT8973A_REG_DEV2_JIG_UART_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_ON_SHIFT)
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| 126 | #define RT8973A_REG_DEV2_JIG_UART_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT)
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| 127 |
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| 128 | #define RT8973A_REG_MANUAL_SW1_DP_SHIFT 2
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| 129 | #define RT8973A_REG_MANUAL_SW1_DM_SHIFT 5
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| 130 | #define RT8973A_REG_MANUAL_SW1_DP_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DP_SHIFT)
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| 131 | #define RT8973A_REG_MANUAL_SW1_DM_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DM_SHIFT)
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| 132 | #define DM_DP_CON_SWITCH_OPEN 0x0
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| 133 | #define DM_DP_CON_SWITCH_USB 0x1
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| 134 | #define DM_DP_CON_SWITCH_UART 0x3
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| 135 | #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
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| 136 | | (DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
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| 137 | #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
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| 138 | | (DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
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| 139 | #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
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| 140 | | (DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
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| 141 |
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| 142 | #define RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT 0
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| 143 | #define RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT 2
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| 144 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT 3
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| 145 | #define RT8973A_REG_MANUAL_SW2_FET_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT)
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| 146 | #define RT8973A_REG_MANUAL_SW2_JIG_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT)
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| 147 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK (0x1 << RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT)
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| 148 | #define RT8973A_REG_MANUAL_SW2_FET_ON 0
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| 149 | #define RT8973A_REG_MANUAL_SW2_FET_OFF 0x1
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| 150 | #define RT8973A_REG_MANUAL_SW2_JIG_OFF 0
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| 151 | #define RT8973A_REG_MANUAL_SW2_JIG_ON 0x1
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| 152 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_ON 0
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| 153 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF 0x1
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| 154 |
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| 155 | #define RT8973A_REG_RESET_SHIFT 0
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| 156 | #define RT8973A_REG_RESET_MASK (0x1 << RT8973A_REG_RESET_SHIFT)
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| 157 | #define RT8973A_REG_RESET 0x1
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| 158 |
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| 159 |
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| 160 | enum rt8973a_irq {
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| 161 |
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| 162 | RT8973A_INT1_ATTACH,
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| 163 | RT8973A_INT1_DETACH,
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| 164 | RT8973A_INT1_CHGDET,
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| 165 | RT8973A_INT1_DCD_T,
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| 166 | RT8973A_INT1_OVP,
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| 167 | RT8973A_INT1_CONNECT,
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| 168 | RT8973A_INT1_ADC_CHG,
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| 169 | RT8973A_INT1_OTP,
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| 170 |
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| 171 |
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| 172 | RT8973A_INT2_UVLO,
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| 173 | RT8973A_INT2_POR,
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| 174 | RT8973A_INT2_OTP_FET,
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| 175 | RT8973A_INT2_OVP_FET,
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| 176 | RT8973A_INT2_OCP_LATCH,
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| 177 | RT8973A_INT2_OCP,
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| 178 | RT8973A_INT2_OVP_OCP,
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| 179 |
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| 180 | RT8973A_NUM,
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| 181 | };
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| 182 |
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| 183 | #define RT8973A_INT1_ATTACH_MASK BIT(0)
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| 184 | #define RT8973A_INT1_DETACH_MASK BIT(1)
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| 185 | #define RT8973A_INT1_CHGDET_MASK BIT(2)
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| 186 | #define RT8973A_INT1_DCD_T_MASK BIT(3)
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| 187 | #define RT8973A_INT1_OVP_MASK BIT(4)
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| 188 | #define RT8973A_INT1_CONNECT_MASK BIT(5)
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| 189 | #define RT8973A_INT1_ADC_CHG_MASK BIT(6)
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| 190 | #define RT8973A_INT1_OTP_MASK BIT(7)
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| 191 | #define RT8973A_INT2_UVLOT_MASK BIT(0)
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| 192 | #define RT8973A_INT2_POR_MASK BIT(1)
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| 193 | #define RT8973A_INT2_OTP_FET_MASK BIT(2)
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| 194 | #define RT8973A_INT2_OVP_FET_MASK BIT(3)
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| 195 | #define RT8973A_INT2_OCP_LATCH_MASK BIT(4)
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| 196 | #define RT8973A_INT2_OCP_MASK BIT(5)
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| 197 | #define RT8973A_INT2_OVP_OCP_MASK BIT(6)
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| 198 |
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| 199 | #endif
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