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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#include "amdgpu_ctx.h"
38
39#include <linux/atomic.h>
40#include <linux/wait.h>
41#include <linux/list.h>
42#include <linux/kref.h>
43#include <linux/rbtree.h>
44#include <linux/hashtable.h>
45#include <linux/dma-fence.h>
46#include <linux/pci.h>
47#include <linux/xarray.h>
48
49#include <drm/ttm/ttm_bo.h>
50#include <drm/ttm/ttm_placement.h>
51
52#include <drm/amdgpu_drm.h>
53#include <drm/drm_gem.h>
54#include <drm/drm_ioctl.h>
55
56#include <kgd_kfd_interface.h>
57#include "dm_pp_interface.h"
58#include "kgd_pp_interface.h"
59
60#include "amd_shared.h"
61#include "amdgpu_utils.h"
62#include "amdgpu_mode.h"
63#include "amdgpu_ih.h"
64#include "amdgpu_irq.h"
65#include "amdgpu_ucode.h"
66#include "amdgpu_ttm.h"
67#include "amdgpu_psp.h"
68#include "amdgpu_gds.h"
69#include "amdgpu_sync.h"
70#include "amdgpu_ring.h"
71#include "amdgpu_vm.h"
72#include "amdgpu_dpm.h"
73#include "amdgpu_acp.h"
74#include "amdgpu_uvd.h"
75#include "amdgpu_vce.h"
76#include "amdgpu_vcn.h"
77#include "amdgpu_jpeg.h"
78#include "amdgpu_vpe.h"
79#include "amdgpu_umsch_mm.h"
80#include "amdgpu_gmc.h"
81#include "amdgpu_gfx.h"
82#include "amdgpu_sdma.h"
83#include "amdgpu_lsdma.h"
84#include "amdgpu_nbio.h"
85#include "amdgpu_reg_access.h"
86#include "amdgpu_hdp.h"
87#include "amdgpu_dm.h"
88#include "amdgpu_virt.h"
89#include "amdgpu_csa.h"
90#include "amdgpu_mes_ctx.h"
91#include "amdgpu_gart.h"
92#include "amdgpu_debugfs.h"
93#include "amdgpu_job.h"
94#include "amdgpu_bo_list.h"
95#include "amdgpu_gem.h"
96#include "amdgpu_doorbell.h"
97#include "amdgpu_amdkfd.h"
98#include "amdgpu_discovery.h"
99#include "amdgpu_umc.h"
100#include "amdgpu_mmhub.h"
101#include "amdgpu_gfxhub.h"
102#include "amdgpu_df.h"
103#include "amdgpu_smuio.h"
104#include "amdgpu_fdinfo.h"
105#include "amdgpu_mca.h"
106#include "amdgpu_ras.h"
107#include "amdgpu_lockdep.h"
108#include "amdgpu_cper.h"
109#include "amdgpu_xcp.h"
110#include "amdgpu_seq64.h"
111#include "amdgpu_reg_state.h"
112#include "amdgpu_userq.h"
113#include "amdgpu_eviction_fence.h"
114#include "amdgpu_wb.h"
115#include "amdgpu_ip.h"
116#include "amdgpu_mes.h"
117#include "amdgpu_sa.h"
118#include "amdgpu_acpi.h"
119#if defined(CONFIG_DRM_AMD_ISP)
120#include "amdgpu_isp.h"
121#endif
122
123#define MAX_GPU_INSTANCE 64
124
125#define GFX_SLICE_PERIOD_MS 250
126
127struct amdgpu_gpu_instance {
128 struct amdgpu_device *adev;
129 int mgpu_fan_enabled;
130};
131
132struct amdgpu_mgpu_info {
133 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
134 struct mutex mutex;
135 uint32_t num_gpu;
136 uint32_t num_dgpu;
137 uint32_t num_apu;
138};
139
140struct amdgpu_hwip_reg_entry {
141 u32 hwip;
142 u32 inst;
143 u32 seg;
144 u32 reg_offset;
145 const char *reg_name;
146};
147
148struct amdgpu_watchdog_timer {
149 bool timeout_fatal_disable;
150 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
151};
152
153#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
154
155/*
156 * Modules parameters.
157 */
158extern int amdgpu_modeset;
159extern unsigned int amdgpu_vram_limit;
160extern int amdgpu_vis_vram_limit;
161extern int amdgpu_gart_size;
162extern int amdgpu_gtt_size;
163extern int amdgpu_moverate;
164extern int amdgpu_audio;
165extern int amdgpu_disp_priority;
166extern int amdgpu_hw_i2c;
167extern int amdgpu_pcie_gen2;
168extern int amdgpu_msi;
169extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
170extern int amdgpu_dpm;
171extern int amdgpu_fw_load_type;
172extern int amdgpu_aspm;
173extern int amdgpu_runtime_pm;
174extern uint amdgpu_ip_block_mask;
175extern int amdgpu_bapm;
176extern int amdgpu_deep_color;
177extern int amdgpu_vm_size;
178extern int amdgpu_vm_block_size;
179extern int amdgpu_vm_fragment_size;
180extern int amdgpu_vm_fault_stop;
181extern int amdgpu_vm_debug;
182extern int amdgpu_vm_update_mode;
183extern int amdgpu_exp_hw_support;
184extern int amdgpu_dc;
185extern int amdgpu_sched_jobs;
186extern int amdgpu_sched_hw_submission;
187extern uint amdgpu_pcie_gen_cap;
188extern uint amdgpu_pcie_lane_cap;
189extern u64 amdgpu_cg_mask;
190extern uint amdgpu_pg_mask;
191extern uint amdgpu_sdma_phase_quantum;
192extern char *amdgpu_disable_cu;
193extern char *amdgpu_virtual_display;
194extern uint amdgpu_pp_feature_mask;
195extern uint amdgpu_force_long_training;
196extern int amdgpu_lbpw;
197extern int amdgpu_compute_multipipe;
198extern int amdgpu_gpu_recovery;
199extern int amdgpu_emu_mode;
200extern uint amdgpu_smu_memory_pool_size;
201extern int amdgpu_smu_pptable_id;
202extern uint amdgpu_dc_feature_mask;
203extern uint amdgpu_freesync_vid_mode;
204extern uint amdgpu_dc_debug_mask;
205extern uint amdgpu_dc_visual_confirm;
206extern int amdgpu_dm_abm_level;
207extern int amdgpu_backlight;
208extern int amdgpu_damage_clips;
209extern struct amdgpu_mgpu_info mgpu_info;
210extern int amdgpu_ras_enable;
211extern uint amdgpu_ras_mask;
212extern int amdgpu_bad_page_threshold;
213extern bool amdgpu_ignore_bad_page_threshold;
214extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
215extern int amdgpu_async_gfx_ring;
216extern int amdgpu_mcbp;
217extern int amdgpu_discovery;
218extern int amdgpu_mes_log_enable;
219extern int amdgpu_uni_mes;
220extern int amdgpu_noretry;
221extern int amdgpu_force_asic_type;
222extern int amdgpu_smartshift_bias;
223extern int amdgpu_use_xgmi_p2p;
224extern int amdgpu_mtype_local;
225extern int amdgpu_enforce_isolation;
226extern uint amdgpu_debug_mask;
227#ifdef CONFIG_HSA_AMD
228extern int sched_policy;
229extern bool debug_evictions;
230extern bool no_system_mem_limit;
231extern int halt_if_hws_hang;
232extern uint amdgpu_svm_default_granularity;
233#else
234static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
235static const bool __maybe_unused debug_evictions; /* = false */
236static const bool __maybe_unused no_system_mem_limit;
237static const int __maybe_unused halt_if_hws_hang;
238#endif
239#ifdef CONFIG_HSA_AMD_P2P
240extern bool pcie_p2p;
241#endif
242
243extern int amdgpu_tmz;
244extern int amdgpu_reset_method;
245
246#ifdef CONFIG_DRM_AMDGPU_SI
247extern int amdgpu_si_support;
248#endif
249#ifdef CONFIG_DRM_AMDGPU_CIK
250extern int amdgpu_cik_support;
251#endif
252extern int amdgpu_num_kcq;
253
254#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
255#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)
256extern int amdgpu_vcnfw_log;
257extern int amdgpu_sg_display;
258extern int amdgpu_umsch_mm;
259extern int amdgpu_seamless;
260extern int amdgpu_umsch_mm_fwlog;
261
262extern int amdgpu_user_partt_mode;
263extern int amdgpu_agp;
264extern int amdgpu_rebar;
265
266extern int amdgpu_wbrf;
267extern int amdgpu_user_queue;
268extern int amdgpu_ptl;
269
270extern uint amdgpu_hdmi_hpd_debounce_delay_ms;
271
272#define AMDGPU_SG_THRESHOLD (256*1024*1024)
273#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
274#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
275#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
276#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
277#define AMDGPUFB_CONN_LIMIT 4
278#define AMDGPU_BIOS_NUM_SCRATCH 16
279
280#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
281
282/* hard reset data */
283#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
284
285/* reset flags */
286#define AMDGPU_RESET_GFX (1 << 0)
287#define AMDGPU_RESET_COMPUTE (1 << 1)
288#define AMDGPU_RESET_DMA (1 << 2)
289#define AMDGPU_RESET_CP (1 << 3)
290#define AMDGPU_RESET_GRBM (1 << 4)
291#define AMDGPU_RESET_DMA1 (1 << 5)
292#define AMDGPU_RESET_RLC (1 << 6)
293#define AMDGPU_RESET_SEM (1 << 7)
294#define AMDGPU_RESET_IH (1 << 8)
295#define AMDGPU_RESET_VMC (1 << 9)
296#define AMDGPU_RESET_MC (1 << 10)
297#define AMDGPU_RESET_DISPLAY (1 << 11)
298#define AMDGPU_RESET_UVD (1 << 12)
299#define AMDGPU_RESET_VCE (1 << 13)
300#define AMDGPU_RESET_VCE1 (1 << 14)
301
302/* reset mask */
303#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */
304#define AMDGPU_RESET_TYPE_SOFT_RECOVERY (1 << 1) /* soft recovery, eg. kill shaders */
305#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
306#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
307#define AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET (1 << 4) /* soft-resets an IP block */
308
309/* max cursor sizes (in pixels) */
310#define CIK_CURSOR_WIDTH 128
311#define CIK_CURSOR_HEIGHT 128
312
313/* smart shift bias level limits */
314#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
315#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
316
317/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
318#define AMDGPU_SWCTF_EXTRA_DELAY 50
319
320struct amdgpu_xcp_mgr;
321struct amdgpu_device;
322struct amdgpu_irq_src;
323struct amdgpu_fpriv;
324struct amdgpu_bo_va_mapping;
325struct kfd_vm_fault_info;
326struct amdgpu_hive_info;
327struct amdgpu_reset_context;
328struct amdgpu_reset_control;
329struct amdgpu_coredump_info;
330struct amdgpu_video_codecs;
331
332enum amdgpu_cp_irq {
333 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
334 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
343
344 AMDGPU_CP_IRQ_LAST
345};
346
347enum amdgpu_thermal_irq {
348 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
349 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
350
351 AMDGPU_THERMAL_IRQ_LAST
352};
353
354enum amdgpu_kiq_irq {
355 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
356 AMDGPU_CP_KIQ_IRQ_LAST
357};
358#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
359#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
360#define MAX_KIQ_REG_TRY 1000
361
362/*
363 * BIOS.
364 */
365bool amdgpu_get_bios(struct amdgpu_device *adev);
366bool amdgpu_read_bios(struct amdgpu_device *adev);
367bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
368 u8 *bios, u32 length_bytes);
369void amdgpu_bios_release(struct amdgpu_device *adev);
370/*
371 * Clocks
372 */
373
374#define AMDGPU_MAX_PPLL 3
375
376struct amdgpu_clock {
377 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
378 struct amdgpu_pll spll;
379 struct amdgpu_pll mpll;
380 /* 10 Khz units */
381 uint32_t default_mclk;
382 uint32_t default_sclk;
383 uint32_t default_dispclk;
384 uint32_t dp_extclk;
385 uint32_t max_pixel_clock;
386};
387
388/*
389 * IRQS.
390 */
391
392struct amdgpu_flip_work {
393 struct delayed_work flip_work;
394 struct work_struct unpin_work;
395 struct amdgpu_device *adev;
396 int crtc_id;
397 u32 target_vblank;
398 uint64_t base;
399 struct drm_pending_vblank_event *event;
400 struct amdgpu_bo *old_abo;
401 unsigned shared_count;
402 struct dma_fence **shared;
403 struct dma_fence_cb cb;
404 bool async;
405};
406
407/*
408 * file private structure
409 */
410
411struct amdgpu_fpriv {
412 struct amdgpu_vm vm;
413 struct amdgpu_bo_va *prt_va;
414 struct amdgpu_bo_va *csa_va;
415 struct amdgpu_bo_va *seq64_va;
416 struct xarray bo_list_handles;
417 struct amdgpu_ctx_mgr ctx_mgr;
418 struct amdgpu_userq_mgr userq_mgr;
419
420 /* Eviction fence infra */
421 struct amdgpu_eviction_fence_mgr evf_mgr;
422
423 /** GPU partition selection */
424 uint32_t xcp_id;
425};
426
427int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
428
429/*
430 * Benchmarking
431 */
432int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
433
434/*
435 * ASIC specific functions.
436 */
437struct amdgpu_asic_funcs {
438 bool (*read_disabled_bios)(struct amdgpu_device *adev);
439 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
440 u8 *bios, u32 length_bytes);
441 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
442 u32 sh_num, u32 reg_offset, u32 *value);
443 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
444 int (*reset)(struct amdgpu_device *adev);
445 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
446 /* get the reference clock */
447 u32 (*get_xclk)(struct amdgpu_device *adev);
448 /* MM block clocks */
449 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
450 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
451 /* static power management */
452 int (*get_pcie_lanes)(struct amdgpu_device *adev);
453 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
454 /* get config memsize register */
455 u32 (*get_config_memsize)(struct amdgpu_device *adev);
456 /* flush hdp write queue */
457 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
458 /* invalidate hdp read cache */
459 void (*invalidate_hdp)(struct amdgpu_device *adev,
460 struct amdgpu_ring *ring);
461 /* initialize doorbell layout for specific asic*/
462 void (*init_doorbell_index)(struct amdgpu_device *adev);
463 /* PCIe bandwidth usage */
464 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
465 uint64_t *count1);
466 /* do we need to reset the asic at init time (e.g., kexec) */
467 bool (*need_reset_on_init)(struct amdgpu_device *adev);
468 /* PCIe replay counter */
469 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
470 /* device supports BACO */
471 int (*supports_baco)(struct amdgpu_device *adev);
472 /* pre asic_init quirks */
473 void (*pre_asic_init)(struct amdgpu_device *adev);
474 /* enter/exit umd stable pstate */
475 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
476 /* query video codecs */
477 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
478 const struct amdgpu_video_codecs **codecs);
479 /* encode "> 32bits" smn addressing */
480 u64 (*encode_ext_smn_addressing)(int ext_id);
481
482 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
483 enum amdgpu_reg_state reg_state, void *buf,
484 size_t max_size);
485};
486
487/*
488 * IOCTL.
489 */
490int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
491 struct drm_file *filp);
492
493int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
494int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
495 struct drm_file *filp);
496int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
497int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
498 struct drm_file *filp);
499
500/* VRAM scratch page for HDP bug, default vram page */
501struct amdgpu_mem_scratch {
502 struct amdgpu_bo *robj;
503 uint32_t *ptr;
504 u64 gpu_addr;
505};
506
507/*
508 * CGS
509 */
510struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
511void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
512
513/*
514 * Core structure, functions and helpers.
515 */
516struct amdgpu_mmio_remap {
517 u32 reg_offset;
518 resource_size_t bus_addr;
519 struct amdgpu_bo *bo;
520};
521
522enum amdgpu_uid_type {
523 AMDGPU_UID_TYPE_XCD,
524 AMDGPU_UID_TYPE_AID,
525 AMDGPU_UID_TYPE_SOC,
526 AMDGPU_UID_TYPE_MID,
527 AMDGPU_UID_TYPE_MAX
528};
529
530#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */
531
532struct amdgpu_uid {
533 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX];
534 struct amdgpu_device *adev;
535};
536
537struct amd_powerplay {
538 void *pp_handle;
539 const struct amd_pm_funcs *pp_funcs;
540};
541
542/* polaris10 kickers */
543#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
544 ((rid == 0xE3) || \
545 (rid == 0xE4) || \
546 (rid == 0xE5) || \
547 (rid == 0xE7) || \
548 (rid == 0xEF))) || \
549 ((did == 0x6FDF) && \
550 ((rid == 0xE7) || \
551 (rid == 0xEF) || \
552 (rid == 0xFF))))
553
554#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
555 ((rid == 0xE1) || \
556 (rid == 0xF7)))
557
558/* polaris11 kickers */
559#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
560 ((rid == 0xE0) || \
561 (rid == 0xE5))) || \
562 ((did == 0x67FF) && \
563 ((rid == 0xCF) || \
564 (rid == 0xEF) || \
565 (rid == 0xFF))))
566
567#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
568 ((rid == 0xE2)))
569
570/* polaris12 kickers */
571#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
572 ((rid == 0xC0) || \
573 (rid == 0xC1) || \
574 (rid == 0xC3) || \
575 (rid == 0xC7))) || \
576 ((did == 0x6981) && \
577 ((rid == 0x00) || \
578 (rid == 0x01) || \
579 (rid == 0x10))))
580
581struct amdgpu_pcie_reset_ctx {
582 bool in_link_reset;
583 bool occurs_dpc;
584 bool audio_suspended;
585 struct pci_dev *swus;
586 struct pci_saved_state *swus_pcistate;
587 struct pci_saved_state *swds_pcistate;
588};
589
590/*
591 * Custom Init levels could be defined for different situations where a full
592 * initialization of all hardware blocks are not expected. Sample cases are
593 * custom init sequences after resume after S0i3/S3, reset on initialization,
594 * partial reset of blocks etc. Presently, this defines only two levels. Levels
595 * are described in corresponding struct definitions - amdgpu_init_default,
596 * amdgpu_init_minimal_xgmi.
597 */
598enum amdgpu_init_lvl_id {
599 AMDGPU_INIT_LEVEL_DEFAULT,
600 AMDGPU_INIT_LEVEL_MINIMAL_XGMI,
601 AMDGPU_INIT_LEVEL_RESET_RECOVERY,
602};
603
604struct amdgpu_init_level {
605 enum amdgpu_init_lvl_id level;
606 uint32_t hwini_ip_block_mask;
607};
608
609#define AMDGPU_RESET_MAGIC_NUM 64
610#define AMDGPU_MAX_DF_PERFMONS 4
611struct amdgpu_reset_domain;
612struct amdgpu_fru_info;
613
614enum amdgpu_enforce_isolation_mode {
615 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0,
616 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1,
617 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2,
618 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
619};
620
621struct amdgpu_device {
622 struct device *dev;
623 struct pci_dev *pdev;
624 /* The two ends of the physical PCIe link outside the device. */
625 struct pci_dev *link_dev;
626 struct pci_dev *link_partner;
627 struct drm_device ddev;
628
629#ifdef CONFIG_DRM_AMD_ACP
630 struct amdgpu_acp acp;
631#endif
632 struct amdgpu_hive_info *hive;
633 struct amdgpu_xcp_mgr *xcp_mgr;
634 /* ASIC */
635 enum amd_asic_type asic_type;
636 uint32_t family;
637 uint32_t rev_id;
638 uint32_t external_rev_id;
639 unsigned long flags;
640 unsigned long apu_flags;
641 int usec_timeout;
642 const struct amdgpu_asic_funcs *asic_funcs;
643 bool shutdown;
644 bool need_swiotlb;
645 bool accel_working;
646 struct notifier_block acpi_nb;
647 struct notifier_block pm_nb;
648 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
649 struct debugfs_blob_wrapper debugfs_vbios_blob;
650 struct mutex srbm_mutex;
651 /* GRBM index mutex. Protects concurrent access to GRBM index */
652 struct mutex grbm_idx_mutex;
653 struct dev_pm_domain vga_pm_domain;
654 bool have_disp_power_ref;
655 bool have_atomics_support;
656 bool is_sw_smu;
657
658 /* BIOS */
659 bool is_atom_fw;
660 uint8_t *bios;
661 uint32_t bios_size;
662 uint32_t bios_scratch_reg_offset;
663 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
664
665 /* Register/doorbell mmio */
666 resource_size_t rmmio_base;
667 resource_size_t rmmio_size;
668 void __iomem *rmmio;
669 /* protects concurrent MM_INDEX/DATA based register access */
670 spinlock_t mmio_idx_lock;
671 struct amdgpu_mmio_remap rmmio_remap;
672 /* Indirect register access blocks */
673 struct amdgpu_reg_access reg;
674 struct amdgpu_doorbell doorbell;
675
676 /* clock/pll info */
677 struct amdgpu_clock clock;
678
679 /* MC */
680 struct amdgpu_gmc gmc;
681 struct amdgpu_gart gart;
682 dma_addr_t dummy_page_addr;
683 struct amdgpu_vm_manager vm_manager;
684 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
685 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
686
687 /* memory management */
688 struct amdgpu_mman mman;
689 struct amdgpu_mem_scratch mem_scratch;
690 struct amdgpu_wb wb;
691 atomic64_t num_bytes_moved;
692 atomic64_t num_evictions;
693 atomic64_t num_vram_cpu_page_faults;
694 atomic_t gpu_reset_counter;
695 atomic_t vram_lost_counter;
696
697 /* data for buffer migration throttling */
698 struct {
699 spinlock_t lock;
700 s64 last_update_us;
701 s64 accum_us; /* accumulated microseconds */
702 s64 accum_us_vis; /* for visible VRAM */
703 u32 log2_max_MBps;
704 } mm_stats;
705
706 /* discovery*/
707 struct amdgpu_discovery_info discovery;
708
709 /* display */
710 bool enable_virtual_display;
711 struct amdgpu_vkms_output *amdgpu_vkms_output;
712 struct amdgpu_mode_info mode_info;
713 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
714 struct delayed_work hotplug_work;
715 struct amdgpu_irq_src crtc_irq;
716 struct amdgpu_irq_src vline0_irq;
717 struct amdgpu_irq_src vupdate_irq;
718 struct amdgpu_irq_src pageflip_irq;
719 struct amdgpu_irq_src hpd_irq;
720 struct amdgpu_irq_src dmub_trace_irq;
721 struct amdgpu_irq_src dmub_outbox_irq;
722
723 /* rings */
724 u64 fence_context;
725 unsigned num_rings;
726 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
727 struct dma_fence __rcu *gang_submit;
728 bool ib_pool_ready;
729 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
730 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
731
732 /* interrupts */
733 struct amdgpu_irq irq;
734
735 /* powerplay */
736 struct amd_powerplay powerplay;
737 struct amdgpu_pm pm;
738 u64 cg_flags;
739 u32 pg_flags;
740
741 /* nbio */
742 struct amdgpu_nbio nbio;
743
744 /* hdp */
745 struct amdgpu_hdp hdp;
746
747 /* smuio */
748 struct amdgpu_smuio smuio;
749
750 /* mmhub */
751 struct amdgpu_mmhub mmhub;
752
753 /* gfxhub */
754 struct amdgpu_gfxhub gfxhub;
755
756 /* gfx */
757 struct amdgpu_gfx gfx;
758
759 /* sdma */
760 struct amdgpu_sdma sdma;
761
762 /* lsdma */
763 struct amdgpu_lsdma lsdma;
764
765 /* uvd */
766 struct amdgpu_uvd uvd;
767
768 /* vce */
769 struct amdgpu_vce vce;
770
771 /* vcn */
772 struct amdgpu_vcn vcn;
773
774 /* jpeg */
775 struct amdgpu_jpeg jpeg;
776
777 /* vpe */
778 struct amdgpu_vpe vpe;
779
780 /* umsch */
781 struct amdgpu_umsch_mm umsch_mm;
782 bool enable_umsch_mm;
783
784 /* firmwares */
785 struct amdgpu_firmware firmware;
786
787 /* PSP */
788 struct psp_context psp;
789
790 /* GDS */
791 struct amdgpu_gds gds;
792
793 /* for userq and VM fences */
794 struct amdgpu_seq64 seq64;
795
796 /* UMC */
797 struct amdgpu_umc umc;
798
799 /* display related functionality */
800 struct amdgpu_display_manager dm;
801
802#if defined(CONFIG_DRM_AMD_ISP)
803 /* isp */
804 struct amdgpu_isp isp;
805#endif
806
807 /* mes */
808 bool enable_mes;
809 bool enable_mes_kiq;
810 bool enable_uni_mes;
811 struct amdgpu_mes mes;
812 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
813 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM];
814
815 /**
816 * @userq_doorbell_xa: Global user queue map (doorbell index → queue)
817 * Key: doorbell_index (unique global identifier for the queue)
818 * Value: struct amdgpu_usermode_queue
819 */
820 struct xarray userq_doorbell_xa;
821
822 /* df */
823 struct amdgpu_df df;
824
825 /* MCA */
826 struct amdgpu_mca mca;
827
828 /* CPER */
829 struct amdgpu_cper cper;
830
831 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
832 uint32_t harvest_ip_mask;
833 int num_ip_blocks;
834 struct mutex mn_lock;
835 DECLARE_HASHTABLE(mn_hash, 7);
836
837 /* tracking pinned memory */
838 atomic64_t vram_pin_size;
839 atomic64_t visible_pin_size;
840 atomic64_t gart_pin_size;
841
842 /* soc15 register offset based on ip, instance and segment */
843 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
844 struct amdgpu_ip_map_info ip_map;
845
846 /* delayed work_func for deferring clockgating during resume */
847 struct delayed_work delayed_init_work;
848
849 struct amdgpu_virt virt;
850
851 /* record hw reset is performed */
852 bool has_hw_reset;
853 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
854
855 /* s3/s4 mask */
856 bool in_suspend;
857 bool in_s3;
858 bool in_s4;
859 bool in_s0ix;
860 suspend_state_t last_suspend_state;
861
862 enum pp_mp1_state mp1_state;
863 struct amdgpu_doorbell_index doorbell_index;
864
865 struct mutex notifier_lock;
866
867 int asic_reset_res;
868 struct work_struct xgmi_reset_work;
869 struct list_head reset_list;
870
871 long gfx_timeout;
872 long sdma_timeout;
873 long video_timeout;
874 long compute_timeout;
875 long psp_timeout;
876
877 uint64_t unique_id;
878 uint8_t unitid;
879 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
880
881 /* enable runtime pm on the device */
882 bool in_runpm;
883 bool has_pr3;
884
885 bool ucode_sysfs_en;
886
887 struct amdgpu_fru_info *fru_info;
888 atomic_t throttling_logging_enabled;
889 struct ratelimit_state throttling_logging_rs;
890 uint32_t ras_hw_enabled;
891 uint32_t ras_enabled;
892 bool ras_default_ecc_enabled;
893
894 bool no_hw_access;
895 struct pci_saved_state *pci_state;
896 pci_channel_state_t pci_channel_state;
897
898 struct amdgpu_pcie_reset_ctx pcie_reset_ctx;
899
900 /* Track auto wait count on s_barrier settings */
901 bool barrier_has_auto_waitcnt;
902
903 struct amdgpu_reset_control *reset_cntl;
904 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
905
906 bool ram_is_direct_mapped;
907
908 struct list_head ras_list;
909
910 struct amdgpu_reset_domain *reset_domain;
911
912#ifdef CONFIG_DEV_COREDUMP
913 struct amdgpu_coredump_info *coredump;
914 struct work_struct coredump_work;
915#endif
916
917 struct mutex benchmark_mutex;
918
919 bool scpm_enabled;
920 uint32_t scpm_status;
921
922 struct work_struct reset_work;
923
924 bool dc_enabled;
925 /* Mask of active clusters */
926 uint32_t aid_mask;
927
928 /* Debug */
929 bool debug_vm;
930 bool debug_largebar;
931 bool debug_disable_soft_recovery;
932 bool debug_use_vram_fw_buf;
933 bool debug_exp_resets;
934 bool debug_disable_gpu_ring_reset;
935 bool debug_vm_userptr;
936 bool debug_disable_ce_logs;
937 bool debug_enable_ce_cs;
938 bool debug_hibernation_thaw_resume_gpu;
939 bool debug_disable_ip_block_soft_reset;
940
941 /* Protection for the following isolation structure */
942 struct mutex enforce_isolation_mutex;
943 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP];
944 struct amdgpu_isolation {
945 void *owner;
946 struct dma_fence *spearhead;
947 struct amdgpu_sync active;
948 struct amdgpu_sync prev;
949 } isolation[MAX_XCP];
950
951 struct amdgpu_init_level *init_lvl;
952
953 /* This flag is used to determine how VRAM allocations are handled for APUs
954 * in KFD: VRAM or GTT.
955 */
956 bool apu_prefer_gtt;
957
958 bool userq_halt_for_enforce_isolation;
959 struct amdgpu_uid *uid_info;
960
961 struct amdgpu_uma_carveout_info uma_info;
962
963 /* KFD
964 * Must be last --ends in a flexible-array member.
965 */
966 struct amdgpu_kfd_dev kfd;
967};
968
969static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
970 uint8_t ip, uint8_t inst)
971{
972 /* This considers only major/minor/rev and ignores
973 * subrevision/variant fields.
974 */
975 return adev->ip_versions[ip][inst] & ~0xFFU;
976}
977
978static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
979 uint8_t ip, uint8_t inst)
980{
981 /* This returns full version - major/minor/rev/variant/subrevision */
982 return adev->ip_versions[ip][inst];
983}
984
985static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
986{
987 return container_of(ddev, struct amdgpu_device, ddev);
988}
989
990static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
991{
992 return &adev->ddev;
993}
994
995static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
996{
997 return container_of(bdev, struct amdgpu_device, mman.bdev);
998}
999
1000static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev)
1001{
1002 return !!adev->aid_mask;
1003}
1004
1005int amdgpu_device_init(struct amdgpu_device *adev,
1006 uint32_t flags);
1007void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1008void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1009
1010int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1011
1012void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1013 void *buf, size_t size, bool write);
1014size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1015 void *buf, size_t size, bool write);
1016
1017void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1018 void *buf, size_t size, bool write);
1019u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1020bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,
1021 enum amd_asic_type asic_type);
1022bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1023
1024void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1025
1026int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1027 struct amdgpu_reset_context *reset_context);
1028
1029int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1030 struct amdgpu_reset_context *reset_context);
1031
1032int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context);
1033
1034int emu_soc_asic_init(struct amdgpu_device *adev);
1035
1036/*
1037 * Registers read & write functions.
1038 */
1039#define AMDGPU_REGS_NO_KIQ (1<<1)
1040#define AMDGPU_REGS_RLC (1<<2)
1041
1042#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1043#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1044
1045#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1046#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1047
1048#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1049#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1050
1051#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1052#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1053#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1054#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1055#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1056#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1057#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1058#define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg))
1059#define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v))
1060#define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg))
1061#define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v))
1062#define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg))
1063#define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v))
1064#define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg))
1065#define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v))
1066#define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg))
1067#define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v))
1068#define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg))
1069#define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v))
1070#define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg))
1071#define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v))
1072#define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg))
1073#define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v))
1074#define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg))
1075#define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v))
1076#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg))
1077#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v))
1078#define RREG32_AUDIO_ENDPT(block, reg) \
1079 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg))
1080#define WREG32_AUDIO_ENDPT(block, reg, v) \
1081 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v))
1082#define WREG32_P(reg, val, mask) \
1083 do { \
1084 uint32_t tmp_ = RREG32(reg); \
1085 tmp_ &= (mask); \
1086 tmp_ |= ((val) & ~(mask)); \
1087 WREG32(reg, tmp_); \
1088 } while (0)
1089#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1090#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1091#define WREG32_PLL_P(reg, val, mask) \
1092 do { \
1093 uint32_t tmp_ = RREG32_PLL(reg); \
1094 tmp_ &= (mask); \
1095 tmp_ |= ((val) & ~(mask)); \
1096 WREG32_PLL(reg, tmp_); \
1097 } while (0)
1098
1099#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1100 do { \
1101 u32 tmp = RREG32_SMC(_Reg); \
1102 tmp &= (_Mask); \
1103 tmp |= ((_Val) & ~(_Mask)); \
1104 WREG32_SMC(_Reg, tmp); \
1105 } while (0)
1106
1107#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1108
1109#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1110#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1111
1112#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1113 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1114 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1115
1116#define REG_GET_FIELD(value, reg, field) \
1117 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1118
1119#define WREG32_FIELD(reg, field, val) \
1120 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1121
1122#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1123 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1124
1125#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1126/*
1127 * BIOS helpers.
1128 */
1129#define RBIOS8(i) (adev->bios[i])
1130#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1131#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1132
1133#include "amdgpu_reset.h"
1134
1135/*
1136 * ASICs macro.
1137 */
1138#define amdgpu_asic_set_vga_state(adev, state) \
1139 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1140#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1141#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1142#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1143#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1144#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1145#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1146#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1147#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1148#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1149#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1150#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1151#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1152#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1153#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1154#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1155#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1156#define amdgpu_asic_supports_baco(adev) \
1157 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0)
1158#define amdgpu_asic_pre_asic_init(adev) \
1159 { \
1160 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \
1161 (adev)->asic_funcs->pre_asic_init((adev)); \
1162 }
1163#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1164 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1165#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1166
1167#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1168
1169#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1170#define for_each_inst(i, inst_mask) \
1171 for (i = ffs(inst_mask); i-- != 0; \
1172 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1173
1174/* Common functions */
1175bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1176bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1177int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1178 struct amdgpu_job *job,
1179 struct amdgpu_reset_context *reset_context);
1180void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1181int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1182bool amdgpu_device_need_post(struct amdgpu_device *adev);
1183bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1184bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1185
1186void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1187 u64 num_vis_bytes);
1188int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1189void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1190 const u32 *registers,
1191 const u32 array_size);
1192
1193int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1194int amdgpu_device_link_reset(struct amdgpu_device *adev);
1195bool amdgpu_device_supports_atpx(struct amdgpu_device *adev);
1196bool amdgpu_device_supports_px(struct amdgpu_device *adev);
1197bool amdgpu_device_supports_boco(struct amdgpu_device *adev);
1198bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev);
1199int amdgpu_device_supports_baco(struct amdgpu_device *adev);
1200void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev);
1201bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1202 struct amdgpu_device *peer_adev);
1203int amdgpu_device_baco_enter(struct amdgpu_device *adev);
1204int amdgpu_device_baco_exit(struct amdgpu_device *adev);
1205
1206void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1207 struct amdgpu_ring *ring);
1208void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1209 struct amdgpu_ring *ring);
1210
1211void amdgpu_device_halt(struct amdgpu_device *adev);
1212struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);
1213struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1214 struct dma_fence *gang);
1215struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev,
1216 struct amdgpu_ring *ring,
1217 struct amdgpu_job *job);
1218bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1219ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
1220ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
1221void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev,
1222 const struct amdgpu_vm_pte_funcs *vm_pte_funcs);
1223void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev,
1224 const struct amdgpu_buffer_funcs *buffer_funcs);
1225
1226/* atpx handler */
1227#if defined(CONFIG_VGA_SWITCHEROO)
1228void amdgpu_register_atpx_handler(void);
1229void amdgpu_unregister_atpx_handler(void);
1230bool amdgpu_has_atpx_dgpu_power_cntl(void);
1231bool amdgpu_is_atpx_hybrid(void);
1232bool amdgpu_has_atpx(void);
1233#else
1234static inline void amdgpu_register_atpx_handler(void) {}
1235static inline void amdgpu_unregister_atpx_handler(void) {}
1236static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1237static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1238static inline bool amdgpu_has_atpx(void) { return false; }
1239#endif
1240
1241/*
1242 * KMS
1243 */
1244extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1245extern const int amdgpu_max_kms_ioctl;
1246
1247int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1248void amdgpu_driver_unload_kms(struct drm_device *dev);
1249int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1250void amdgpu_driver_postclose_kms(struct drm_device *dev,
1251 struct drm_file *file_priv);
1252void amdgpu_driver_release_kms(struct drm_device *dev);
1253
1254int amdgpu_device_prepare(struct drm_device *dev);
1255void amdgpu_device_complete(struct drm_device *dev);
1256int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1257int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1258u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1259int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1260void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1261int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1262 struct drm_file *filp);
1263int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data,
1264 struct drm_file *filp);
1265
1266/*
1267 * functions used by amdgpu_encoder.c
1268 */
1269struct amdgpu_afmt_acr {
1270 u32 clock;
1271
1272 int n_32khz;
1273 int cts_32khz;
1274
1275 int n_44_1khz;
1276 int cts_44_1khz;
1277
1278 int n_48khz;
1279 int cts_48khz;
1280
1281};
1282
1283struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1284
1285void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1286void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1287
1288pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1289 pci_channel_state_t state);
1290pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1291pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1292void amdgpu_pci_resume(struct pci_dev *pdev);
1293
1294bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1295bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1296
1297bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1298
1299int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1300 enum amd_clockgating_state state);
1301int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1302 enum amd_powergating_state state);
1303
1304static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1305{
1306 return amdgpu_gpu_recovery != 0 &&
1307 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1308 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1309 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1310 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1311}
1312
1313#include "amdgpu_object.h"
1314
1315static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1316{
1317 return adev->gmc.tmz_enabled;
1318}
1319
1320int amdgpu_in_reset(struct amdgpu_device *adev);
1321
1322extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1323extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1324extern const struct attribute_group amdgpu_flash_attr_group;
1325
1326void amdgpu_set_init_level(struct amdgpu_device *adev,
1327 enum amdgpu_init_lvl_id lvl);
1328
1329static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev)
1330{
1331 u32 status;
1332 int r;
1333
1334 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status);
1335 if (r || PCI_POSSIBLE_ERROR(status)) {
1336 dev_err(adev->dev, "device lost from bus!");
1337 return -ENODEV;
1338 }
1339
1340 return 0;
1341}
1342
1343void amdgpu_device_set_uid(struct amdgpu_uid *uid_info,
1344 enum amdgpu_uid_type type, uint8_t inst,
1345 uint64_t uid);
1346uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info,
1347 enum amdgpu_uid_type type, uint8_t inst);
1348#endif