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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include "amdgpu_amdkfd.h"
25#include "amd_pcie.h"
26#include "amd_shared.h"
27
28#include "amdgpu.h"
29#include "amdgpu_gfx.h"
30#include "amdgpu_dma_buf.h"
31#include <drm/ttm/ttm_tt.h>
32#include <linux/module.h>
33#include <linux/dma-buf.h>
34#include "amdgpu_xgmi.h"
35#include <uapi/linux/kfd_ioctl.h>
36#include "amdgpu_ras.h"
37#include "amdgpu_umc.h"
38#include "amdgpu_reset.h"
39#if IS_ENABLED(CONFIG_HSA_AMD)
40#include "kfd_priv.h"
41#endif
42#include "kfd_svm.h"
43
44/* Total memory size in system memory and all GPU VRAM. Used to
45 * estimate worst case amount of memory to reserve for page tables
46 */
47uint64_t amdgpu_amdkfd_total_mem_size;
48
49static bool kfd_initialized;
50
51int amdgpu_amdkfd_init(void)
52{
53 struct sysinfo si;
54 int ret;
55
56 si_meminfo(&si);
57 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
58 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
59
60 ret = kgd2kfd_init();
61 kfd_initialized = !ret;
62
63 return ret;
64}
65
66void amdgpu_amdkfd_fini(void)
67{
68 if (kfd_initialized) {
69 kgd2kfd_exit();
70 kfd_initialized = false;
71 }
72}
73
74void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
75{
76 bool vf = amdgpu_sriov_vf(adev);
77
78 if (!kfd_initialized)
79 return;
80
81 adev->kfd.dev = kgd2kfd_probe(adev, vf);
82}
83
84/**
85 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
86 * setup amdkfd
87 *
88 * @adev: amdgpu_device pointer
89 * @aperture_base: output returning doorbell aperture base physical address
90 * @aperture_size: output returning doorbell aperture size in bytes
91 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
92 *
93 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
94 * takes doorbells required for its own rings and reports the setup to amdkfd.
95 * amdgpu reserved doorbells are at the start of the doorbell aperture.
96 */
97static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
98 phys_addr_t *aperture_base,
99 size_t *aperture_size,
100 size_t *start_offset)
101{
102 /*
103 * The first num_kernel_doorbells are used by amdgpu.
104 * amdkfd takes whatever's left in the aperture.
105 */
106 if (adev->enable_mes) {
107 /*
108 * With MES enabled, we only need to initialize
109 * the base address. The size and offset are
110 * not initialized as AMDGPU manages the whole
111 * doorbell space.
112 */
113 *aperture_base = adev->doorbell.base;
114 *aperture_size = 0;
115 *start_offset = 0;
116 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells *
117 sizeof(u32)) {
118 *aperture_base = adev->doorbell.base;
119 *aperture_size = adev->doorbell.size;
120 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32);
121 } else {
122 *aperture_base = 0;
123 *aperture_size = 0;
124 *start_offset = 0;
125 }
126}
127
128
129static void amdgpu_amdkfd_reset_work(struct work_struct *work)
130{
131 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
132 kfd.reset_work);
133
134 struct amdgpu_reset_context reset_context;
135
136 memset(&reset_context, 0, sizeof(reset_context));
137
138 reset_context.method = AMD_RESET_METHOD_NONE;
139 reset_context.reset_req_dev = adev;
140 reset_context.src = adev->enable_mes ?
141 AMDGPU_RESET_SRC_MES :
142 AMDGPU_RESET_SRC_HWS;
143 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
144
145 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
146}
147
148static const struct drm_client_funcs kfd_client_funcs = {
149 .unregister = drm_client_release,
150};
151
152int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev)
153{
154 int ret;
155
156 if (!adev->kfd.init_complete || adev->kfd.client.dev)
157 return 0;
158
159 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd",
160 &kfd_client_funcs);
161 if (ret) {
162 dev_err(adev->dev, "Failed to init DRM client: %d\n",
163 ret);
164 return ret;
165 }
166
167 drm_client_register(&adev->kfd.client);
168
169 return 0;
170}
171
172void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
173{
174 int i;
175 int last_valid_bit;
176
177 amdgpu_amdkfd_gpuvm_init_mem_limits();
178
179 if (adev->kfd.dev) {
180 struct kgd2kfd_shared_resources gpu_resources = {
181 .compute_vmid_bitmap =
182 ((1 << AMDGPU_NUM_VMID) - 1) -
183 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
184 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
185 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
186 .gpuvm_size = min(adev->vm_manager.max_pfn
187 << AMDGPU_GPU_PAGE_SHIFT,
188 AMDGPU_GMC_HOLE_START),
189 .drm_render_minor = adev_to_drm(adev)->render->index,
190 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
191 .enable_mes = adev->enable_mes,
192 };
193
194 /* this is going to have a few of the MSBs set that we need to
195 * clear
196 */
197 bitmap_complement(gpu_resources.cp_queue_bitmap,
198 adev->gfx.mec_bitmap[0].queue_bitmap,
199 AMDGPU_MAX_QUEUES);
200
201 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
202 * nbits is not compile time constant
203 */
204 last_valid_bit = 1 /* only first MEC can have compute queues */
205 * adev->gfx.mec.num_pipe_per_mec
206 * adev->gfx.mec.num_queue_per_pipe;
207 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i)
208 clear_bit(i, gpu_resources.cp_queue_bitmap);
209
210 amdgpu_doorbell_get_kfd_info(adev,
211 &gpu_resources.doorbell_physical_address,
212 &gpu_resources.doorbell_aperture_size,
213 &gpu_resources.doorbell_start_offset);
214
215 /* Since SOC15, BIF starts to statically use the
216 * lower 12 bits of doorbell addresses for routing
217 * based on settings in registers like
218 * SDMA0_DOORBELL_RANGE etc..
219 * In order to route a doorbell to CP engine, the lower
220 * 12 bits of its address has to be outside the range
221 * set for SDMA, VCN, and IH blocks.
222 */
223 if (adev->asic_type >= CHIP_VEGA10) {
224 gpu_resources.non_cp_doorbells_start =
225 adev->doorbell_index.first_non_cp;
226 gpu_resources.non_cp_doorbells_end =
227 adev->doorbell_index.last_non_cp;
228 }
229
230 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
231 &gpu_resources);
232
233 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
234
235 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
236 }
237}
238
239void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
240{
241 if (adev->kfd.dev) {
242 kgd2kfd_device_exit(adev->kfd.dev);
243 adev->kfd.dev = NULL;
244 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size;
245 }
246}
247
248void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
249 const void *ih_ring_entry)
250{
251 if (adev->kfd.dev)
252 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
253}
254
255void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev)
256{
257 kgd2kfd_teardown_processes(adev);
258}
259
260void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc)
261{
262 if (adev->kfd.dev) {
263 if (adev->in_s0ix)
264 kgd2kfd_stop_sched_all_nodes(adev->kfd.dev);
265 else
266 kgd2kfd_suspend(adev->kfd.dev, suspend_proc);
267 }
268}
269
270int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc)
271{
272 int r = 0;
273
274 if (adev->kfd.dev) {
275 if (adev->in_s0ix)
276 r = kgd2kfd_start_sched_all_nodes(adev->kfd.dev);
277 else
278 r = kgd2kfd_resume(adev->kfd.dev, resume_proc);
279 }
280
281 return r;
282}
283
284void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev)
285{
286 if (adev->kfd.dev)
287 kgd2kfd_suspend_process(adev->kfd.dev);
288}
289
290int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev)
291{
292 int r = 0;
293
294 if (adev->kfd.dev)
295 r = kgd2kfd_resume_process(adev->kfd.dev);
296
297 return r;
298}
299
300int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
301 struct amdgpu_reset_context *reset_context)
302{
303 int r = 0;
304
305 if (adev->kfd.dev)
306 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context);
307
308 return r;
309}
310
311int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
312{
313 int r = 0;
314
315 if (adev->kfd.dev)
316 r = kgd2kfd_post_reset(adev->kfd.dev);
317
318 return r;
319}
320
321void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
322{
323 if (amdgpu_device_should_recover_gpu(adev))
324 (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work);
325}
326
327void amdgpu_amdkfd_clear_kfd_mapping(struct amdgpu_device *adev)
328{
329#if IS_ENABLED(CONFIG_HSA_AMD)
330 struct kfd_dev *kfd = adev->kfd.dev;
331 unsigned int i;
332
333 if (!kfd || !kfd->init_complete)
334 return;
335
336 for (i = 0; i < kfd->num_nodes; i++) {
337 struct kfd_node *node = kfd->nodes[i];
338
339 kfd_dev_unmap_mapping_range(KFD_MMAP_TYPE_DOORBELL |
340 KFD_MMAP_GPU_ID(node->id),
341 kfd_doorbell_process_slice(kfd));
342 kfd_dev_unmap_mapping_range(KFD_MMAP_TYPE_MMIO |
343 KFD_MMAP_GPU_ID(node->id),
344 PAGE_SIZE);
345 }
346#endif
347}
348
349int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size,
350 u32 domain, void **mem_obj, uint64_t *gpu_addr,
351 void **cpu_ptr, bool cp_mqd_gfx9)
352{
353 struct amdgpu_bo *bo = NULL;
354 struct amdgpu_bo_param bp;
355 int r;
356 void *cpu_ptr_tmp = NULL;
357
358 memset(&bp, 0, sizeof(bp));
359 bp.size = size;
360 bp.byte_align = PAGE_SIZE;
361 bp.domain = domain;
362 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
363 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
364 bp.type = ttm_bo_type_kernel;
365 bp.resv = NULL;
366 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
367
368 if (cp_mqd_gfx9)
369 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
370
371 r = amdgpu_bo_create(adev, &bp, &bo);
372 if (r) {
373 dev_err(adev->dev,
374 "failed to allocate BO for amdkfd (%d)\n", r);
375 return r;
376 }
377
378 /* map the buffer */
379 r = amdgpu_bo_reserve(bo, true);
380 if (r) {
381 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
382 goto allocate_mem_reserve_bo_failed;
383 }
384
385 r = amdgpu_bo_pin(bo, domain);
386 if (r) {
387 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
388 goto allocate_mem_pin_bo_failed;
389 }
390
391 r = amdgpu_ttm_alloc_gart(&bo->tbo);
392 if (r) {
393 dev_err(adev->dev, "%p bind failed\n", bo);
394 goto allocate_mem_kmap_bo_failed;
395 }
396
397 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
398 if (r) {
399 dev_err(adev->dev,
400 "(%d) failed to map bo to kernel for amdkfd\n", r);
401 goto allocate_mem_kmap_bo_failed;
402 }
403
404 *mem_obj = bo;
405 *gpu_addr = amdgpu_bo_gpu_offset(bo);
406 *cpu_ptr = cpu_ptr_tmp;
407
408 amdgpu_bo_unreserve(bo);
409
410 return 0;
411
412allocate_mem_kmap_bo_failed:
413 amdgpu_bo_unpin(bo);
414allocate_mem_pin_bo_failed:
415 amdgpu_bo_unreserve(bo);
416allocate_mem_reserve_bo_failed:
417 amdgpu_bo_unref(&bo);
418
419 return r;
420}
421
422void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj)
423{
424 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj;
425
426 if (!bo || !*bo)
427 return;
428
429 (void)amdgpu_bo_reserve(*bo, true);
430 amdgpu_bo_kunmap(*bo);
431 amdgpu_bo_unpin(*bo);
432 amdgpu_bo_unreserve(*bo);
433 amdgpu_bo_unref(bo);
434}
435
436int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
437 void **mem_obj)
438{
439 struct amdgpu_bo *bo = NULL;
440 struct amdgpu_bo_user *ubo;
441 struct amdgpu_bo_param bp;
442 int r;
443
444 memset(&bp, 0, sizeof(bp));
445 bp.size = size;
446 bp.byte_align = 1;
447 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
448 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
449 bp.type = ttm_bo_type_device;
450 bp.resv = NULL;
451 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
452
453 r = amdgpu_bo_create_user(adev, &bp, &ubo);
454 if (r) {
455 dev_err(adev->dev,
456 "failed to allocate gws BO for amdkfd (%d)\n", r);
457 return r;
458 }
459
460 bo = &ubo->bo;
461 *mem_obj = bo;
462 return 0;
463}
464
465void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
466{
467 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
468
469 amdgpu_bo_unref(&bo);
470}
471
472uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
473 enum kgd_engine_type type)
474{
475 switch (type) {
476 case KGD_ENGINE_PFP:
477 return adev->gfx.pfp_fw_version;
478
479 case KGD_ENGINE_ME:
480 return adev->gfx.me_fw_version;
481
482 case KGD_ENGINE_CE:
483 return adev->gfx.ce_fw_version;
484
485 case KGD_ENGINE_MEC1:
486 return adev->gfx.mec_fw_version;
487
488 case KGD_ENGINE_MEC2:
489 return adev->gfx.mec2_fw_version;
490
491 case KGD_ENGINE_RLC:
492 return adev->gfx.rlc_fw_version;
493
494 case KGD_ENGINE_SDMA1:
495 return adev->sdma.instance[0].fw_version;
496
497 case KGD_ENGINE_SDMA2:
498 return adev->sdma.instance[1].fw_version;
499
500 default:
501 return 0;
502 }
503
504 return 0;
505}
506
507void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
508 struct kfd_local_mem_info *mem_info,
509 struct amdgpu_xcp *xcp)
510{
511 memset(mem_info, 0, sizeof(*mem_info));
512
513 if (xcp) {
514 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size)
515 mem_info->local_mem_size_public =
516 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
517 else
518 mem_info->local_mem_size_private =
519 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
520 } else if (adev->apu_prefer_gtt) {
521 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT);
522 mem_info->local_mem_size_private = 0;
523 } else {
524 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
525 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
526 adev->gmc.visible_vram_size;
527 }
528 mem_info->vram_width = adev->gmc.vram_width;
529
530 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
531 &adev->gmc.aper_base,
532 mem_info->local_mem_size_public,
533 mem_info->local_mem_size_private);
534
535 if (adev->pm.dpm_enabled) {
536 if (amdgpu_emu_mode == 1)
537 mem_info->mem_clk_max = 0;
538 else
539 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
540 } else
541 mem_info->mem_clk_max = 100;
542}
543
544uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
545{
546 if (adev->gfx.funcs->get_gpu_clock_counter)
547 return adev->gfx.funcs->get_gpu_clock_counter(adev);
548 return 0;
549}
550
551uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
552{
553 /* the sclk is in quantas of 10kHz */
554 if (adev->pm.dpm_enabled)
555 return amdgpu_dpm_get_sclk(adev, false) / 100;
556 else
557 return 100;
558}
559
560int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
561 struct amdgpu_device **dmabuf_adev,
562 uint64_t *bo_size, void **metadata_buffer,
563 size_t buffer_size, uint32_t *metadata_size,
564 uint32_t *flags, int8_t *xcp_id)
565{
566 struct dma_buf *dma_buf;
567 struct drm_gem_object *obj;
568 struct amdgpu_bo *bo;
569 uint64_t metadata_flags;
570 int r = -EINVAL;
571
572 dma_buf = dma_buf_get(dma_buf_fd);
573 if (IS_ERR(dma_buf))
574 return PTR_ERR(dma_buf);
575
576 if (dma_buf->ops != &amdgpu_dmabuf_ops)
577 /* Can't handle non-graphics buffers */
578 goto out_put;
579
580 obj = dma_buf->priv;
581 if (obj->dev->driver != adev_to_drm(adev)->driver)
582 /* Can't handle buffers from different drivers */
583 goto out_put;
584
585 adev = drm_to_adev(obj->dev);
586 bo = gem_to_amdgpu_bo(obj);
587 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
588 AMDGPU_GEM_DOMAIN_GTT)))
589 /* Only VRAM and GTT BOs are supported */
590 goto out_put;
591
592 r = 0;
593 if (dmabuf_adev)
594 *dmabuf_adev = adev;
595 if (bo_size)
596 *bo_size = amdgpu_bo_size(bo);
597 if (metadata_buffer) {
598 /* first get metadata_size by buffer = NULL */
599 r = amdgpu_bo_get_metadata(bo, NULL, 0,
600 metadata_size, NULL);
601 if (r)
602 goto out_put;
603
604 /* user buf_size is bigger than bo metadata_size
605 * allocate a buf at kernel space and copy */
606 if (*metadata_size <= buffer_size) {
607 *metadata_buffer = kzalloc(*metadata_size, GFP_KERNEL);
608
609 if (!*metadata_buffer) {
610 r = -ENOMEM;
611 goto out_put;
612 }
613
614 r = amdgpu_bo_get_metadata(bo, *metadata_buffer, *metadata_size,
615 NULL, &metadata_flags);
616 } else
617 r = -EINVAL;
618 }
619 if (flags) {
620 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
621 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
622 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
623
624 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
625 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
626 }
627 if (xcp_id)
628 *xcp_id = bo->xcp_id;
629
630out_put:
631 dma_buf_put(dma_buf);
632 return r;
633}
634
635int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
636{
637 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
638 fls(adev->pm.pcie_mlw_mask)) - 1;
639 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
640 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
641 fls(adev->pm.pcie_gen_mask &
642 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
643 uint32_t num_lanes_mask = 1 << num_lanes_shift;
644 uint32_t gen_speed_mask = 1 << gen_speed_shift;
645 int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
646
647 switch (num_lanes_mask) {
648 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
649 num_lanes_factor = 1;
650 break;
651 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
652 num_lanes_factor = 2;
653 break;
654 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
655 num_lanes_factor = 4;
656 break;
657 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
658 num_lanes_factor = 8;
659 break;
660 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
661 num_lanes_factor = 12;
662 break;
663 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
664 num_lanes_factor = 16;
665 break;
666 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
667 num_lanes_factor = 32;
668 break;
669 }
670
671 switch (gen_speed_mask) {
672 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
673 gen_speed_mbits_factor = 2500;
674 break;
675 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
676 gen_speed_mbits_factor = 5000;
677 break;
678 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
679 gen_speed_mbits_factor = 8000;
680 break;
681 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
682 gen_speed_mbits_factor = 16000;
683 break;
684 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
685 gen_speed_mbits_factor = 32000;
686 break;
687 }
688
689 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
690}
691
692int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
693 enum kgd_engine_type engine,
694 uint32_t vmid, uint64_t gpu_addr,
695 uint32_t *ib_cmd, uint32_t ib_len)
696{
697 struct amdgpu_job *job;
698 struct amdgpu_ib *ib;
699 struct amdgpu_ring *ring;
700 struct dma_fence *f = NULL;
701 int ret;
702
703 switch (engine) {
704 case KGD_ENGINE_MEC1:
705 ring = &adev->gfx.compute_ring[0];
706 break;
707 case KGD_ENGINE_SDMA1:
708 ring = &adev->sdma.instance[0].ring;
709 break;
710 case KGD_ENGINE_SDMA2:
711 ring = &adev->sdma.instance[1].ring;
712 break;
713 default:
714 pr_err("Invalid engine in IB submission: %d\n", engine);
715 ret = -EINVAL;
716 goto err;
717 }
718
719 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, 0, GFP_KERNEL,
720 &job);
721 if (ret)
722 goto err;
723
724 ib = &job->ibs[0];
725 memset(ib, 0, sizeof(struct amdgpu_ib));
726
727 ib->gpu_addr = gpu_addr;
728 ib->ptr = ib_cmd;
729 ib->length_dw = ib_len;
730 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
731 job->vmid = vmid;
732 job->num_ibs = 1;
733
734 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
735
736 if (ret) {
737 drm_err(adev_to_drm(adev), "failed to schedule IB.\n");
738 goto err_ib_sched;
739 }
740
741 ret = dma_fence_wait(f, false);
742 /* Drop the returned fence reference after the wait completes */
743 dma_fence_put(f);
744
745err_ib_sched:
746 amdgpu_job_free(job);
747err:
748 return ret;
749}
750
751void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
752{
753 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE;
754 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
755 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) ||
756 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) {
757 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
758 amdgpu_gfx_off_ctrl(adev, idle);
759 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &&
760 (adev->flags & AMD_IS_APU)) {
761 /* Disable GFXOFF and PG. Temporary workaround
762 * to fix some compute applications issue on GFX9.
763 */
764 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
765 if (gfx_block != NULL)
766 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state);
767 }
768 (void)amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle);
769
770}
771
772bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
773{
774 if (adev->kfd.dev)
775 return vmid >= adev->vm_manager.first_kfd_vmid;
776
777 return false;
778}
779
780bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
781{
782 return adev->have_atomics_support;
783}
784
785void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev)
786{
787 amdgpu_device_flush_hdp(adev, NULL);
788}
789
790bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)
791{
792 return amdgpu_ras_get_fed_status(adev);
793}
794
795void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev,
796 enum amdgpu_ras_block block, uint16_t pasid,
797 pasid_notify pasid_fn, void *data, uint32_t reset)
798{
799 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset);
800}
801
802void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
803 enum amdgpu_ras_block block, uint32_t reset)
804{
805 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset);
806}
807
808int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
809 uint32_t *payload)
810{
811 int ret;
812
813 /* Device or IH ring is not ready so bail. */
814 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih);
815 if (ret)
816 return ret;
817
818 /* Send payload to fence KFD interrupts */
819 amdgpu_amdkfd_interrupt(adev, payload);
820
821 return 0;
822}
823
824int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev)
825{
826 return kgd2kfd_check_and_lock_kfd(adev->kfd.dev);
827}
828
829void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev)
830{
831 kgd2kfd_unlock_kfd(adev->kfd.dev);
832}
833
834
835u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)
836{
837 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id);
838 u64 tmp;
839
840 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
841 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) {
842 /* In NPS1 mode, we should restrict the vram reporting
843 * tied to the ttm_pages_limit which is 1/2 of the system
844 * memory. For other partition modes, the HBM is uniformly
845 * divided already per numa node reported. If user wants to
846 * go beyond the default ttm limit and maximize the ROCm
847 * allocations, they can go up to max ttm and sysmem limits.
848 */
849
850 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes();
851 } else {
852 tmp = adev->gmc.mem_partitions[mem_id].size;
853 }
854
855 if (adev->xcp_mgr->mem_alloc_mode == AMDGPU_PARTITION_MEM_CAPPING_EVEN)
856 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
857
858 return ALIGN_DOWN(tmp, PAGE_SIZE);
859 } else if (adev->apu_prefer_gtt) {
860 return (ttm_tt_pages_limit() << PAGE_SHIFT);
861 } else {
862 return adev->gmc.real_vram_size;
863 }
864}
865
866int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
867 u32 inst)
868{
869 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
870 struct amdgpu_ring *kiq_ring = &kiq->ring;
871 struct amdgpu_ring_funcs *ring_funcs;
872 struct amdgpu_ring *ring;
873 int r = 0;
874
875 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
876 return -EINVAL;
877
878 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev))
879 return 0;
880
881 ring_funcs = kzalloc_obj(*ring_funcs);
882 if (!ring_funcs)
883 return -ENOMEM;
884
885 ring = kzalloc_obj(*ring);
886 if (!ring) {
887 r = -ENOMEM;
888 goto free_ring_funcs;
889 }
890
891 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE;
892 ring->doorbell_index = doorbell_off;
893 ring->funcs = ring_funcs;
894
895 spin_lock(&kiq->ring_lock);
896
897 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
898 spin_unlock(&kiq->ring_lock);
899 r = -ENOMEM;
900 goto free_ring;
901 }
902
903 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0);
904
905 /* Submit unmap queue packet */
906 amdgpu_ring_commit(kiq_ring);
907 /*
908 * Ring test will do a basic scratch register change check. Just run
909 * this to ensure that unmap queues that is submitted before got
910 * processed successfully before returning.
911 */
912 r = amdgpu_ring_test_helper(kiq_ring);
913
914 spin_unlock(&kiq->ring_lock);
915
916free_ring:
917 kfree(ring);
918
919free_ring_funcs:
920 kfree(ring_funcs);
921
922 return r;
923}
924
925/* Stop scheduling on KFD */
926int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id)
927{
928 if (!adev->kfd.init_complete)
929 return 0;
930
931 return kgd2kfd_stop_sched(adev->kfd.dev, node_id);
932}
933
934/* Start scheduling on KFD */
935int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id)
936{
937 if (!adev->kfd.init_complete)
938 return 0;
939
940 return kgd2kfd_start_sched(adev->kfd.dev, node_id);
941}
942
943/* check if there are KFD queues active */
944bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id)
945{
946 if (!adev->kfd.init_complete)
947 return false;
948
949 return kgd2kfd_compute_active(adev->kfd.dev, node_id);
950}
951
952/* Config CGTT_SQ_CLK_CTRL */
953int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,
954 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable)
955{
956 int r;
957
958 if (!adev->kfd.init_complete)
959 return 0;
960
961 r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable,
962 reg_override_enable, perfmon_override_enable);
963
964 return r;
965}
966
967/* Reset an MES queue */
968int amdgpu_amdkfd_reset_mes_queue(struct amdgpu_device *adev,
969 uint32_t node_id,
970 int queue_type,
971 int pipe, int queue,
972 unsigned int db)
973{
974 if (!adev->kfd.init_complete)
975 return 0;
976
977 return kgd2kfd_reset_mes_queue(adev->kfd.dev, node_id, queue_type,
978 pipe, queue, db);
979}