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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <drm/ttm/ttm_tt.h>
29
30#include <drm/drm_exec.h>
31
32#include "amdgpu_object.h"
33#include "amdgpu_gem.h"
34#include "amdgpu_vm.h"
35#include "amdgpu_hmm.h"
36#include "amdgpu_amdkfd.h"
37#include "amdgpu_dma_buf.h"
38#include <uapi/linux/kfd_ioctl.h>
39#include "amdgpu_xgmi.h"
40#include "kfd_priv.h"
41#include "kfd_smi_events.h"
42
43/* Userptr restore delay, just long enough to allow consecutive VM
44 * changes to accumulate
45 */
46#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
47#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
48
49/*
50 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
51 * BO chunk
52 */
53#define VRAM_AVAILABLITY_ALIGN (1 << 21)
54
55/* Impose limit on how much memory KFD can use */
56static struct {
57 uint64_t max_system_mem_limit;
58 uint64_t max_ttm_mem_limit;
59 int64_t system_mem_used;
60 int64_t ttm_mem_used;
61 spinlock_t mem_limit_lock;
62} kfd_mem_limit;
63
64static const char * const domain_bit_to_string[] = {
65 "CPU",
66 "GTT",
67 "VRAM",
68 "GDS",
69 "GWS",
70 "OA"
71};
72
73#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
74
75static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
76
77static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
78 struct kgd_mem *mem)
79{
80 struct kfd_mem_attachment *entry;
81
82 list_for_each_entry(entry, &mem->attachments, list)
83 if (entry->bo_va->base.vm == avm)
84 return true;
85
86 return false;
87}
88
89/**
90 * reuse_dmamap() - Check whether adev can share the original
91 * userptr BO
92 *
93 * If both adev and bo_adev are in direct mapping or
94 * in the same iommu group, they can share the original BO.
95 *
96 * @adev: Device to which can or cannot share the original BO
97 * @bo_adev: Device to which allocated BO belongs to
98 *
99 * Return: returns true if adev can share original userptr BO,
100 * false otherwise.
101 */
102static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
103{
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
106}
107
108/* Set memory usage limits. Current, limits are
109 * System (TTM + userptr) memory - 15/16th System RAM
110 * TTM memory - 3/8th System RAM
111 */
112void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
113{
114 struct sysinfo si;
115 uint64_t mem;
116
117 if (kfd_mem_limit.max_system_mem_limit)
118 return;
119
120 si_meminfo(&si);
121 mem = si.totalram - si.totalhigh;
122 mem *= si.mem_unit;
123
124 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
125 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
126 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
127 kfd_mem_limit.max_system_mem_limit >>= 1;
128 else
129 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
130
131 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
132 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
133 (kfd_mem_limit.max_system_mem_limit >> 20),
134 (kfd_mem_limit.max_ttm_mem_limit >> 20));
135}
136
137void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
138{
139 kfd_mem_limit.system_mem_used += size;
140}
141
142/* Estimate page table size needed to represent a given memory size
143 *
144 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
145 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
146 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
147 * for 2MB pages for TLB efficiency. However, small allocations and
148 * fragmented system memory still need some 4KB pages. We choose a
149 * compromise that should work in most cases without reserving too
150 * much memory for page tables unnecessarily (factor 16K, >> 14).
151 */
152
153#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
154
155/**
156 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
157 * of buffer.
158 *
159 * @adev: Device to which allocated BO belongs to
160 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
161 * equivalent to amdgpu_bo_size(BO)
162 * @alloc_flag: Flag used in allocating a BO as noted above
163 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
164 * managed as one compute node in driver for app
165 *
166 * Return:
167 * returns -ENOMEM in case of error, ZERO otherwise
168 */
169int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
170 uint64_t size, u32 alloc_flag, int8_t xcp_id)
171{
172 uint64_t reserved_for_pt =
173 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
174 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
175 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0);
176 size_t system_mem_needed, ttm_mem_needed, vram_needed;
177 int ret = 0;
178 uint64_t vram_size = 0;
179
180 system_mem_needed = 0;
181 ttm_mem_needed = 0;
182 vram_needed = 0;
183 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
184 system_mem_needed = size;
185 ttm_mem_needed = size;
186 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
187 /*
188 * Conservatively round up the allocation requirement to 2 MB
189 * to avoid fragmentation caused by 4K allocations in the tail
190 * 2M BO chunk.
191 */
192 vram_needed = size;
193 /*
194 * For GFX 9.4.3, get the VRAM size from XCP structs
195 */
196 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
197 return -EINVAL;
198
199 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
200 if (adev->apu_prefer_gtt) {
201 system_mem_needed = size;
202 ttm_mem_needed = size;
203 }
204 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
205 system_mem_needed = size;
206 } else if (!(alloc_flag &
207 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
208 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
209 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
210 return -ENOMEM;
211 }
212
213 spin_lock(&kfd_mem_limit.mem_limit_lock);
214
215 if (kfd_mem_limit.system_mem_used + system_mem_needed >
216 kfd_mem_limit.max_system_mem_limit) {
217 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
218 if (!no_system_mem_limit) {
219 ret = -ENOMEM;
220 goto release;
221 }
222 }
223
224 if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
225 kfd_mem_limit.max_ttm_mem_limit) {
226 ret = -ENOMEM;
227 goto release;
228 }
229
230 /*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with
231 * carve out < gtt. In that case, VRAM allocation will go to gtt domain, skip
232 * VRAM check since ttm_mem_limit check already cover this allocation
233 */
234
235 if (adev && xcp_id >= 0 && (!adev->apu_prefer_gtt || adev->gmc.is_app_apu)) {
236 uint64_t vram_available =
237 vram_size - reserved_for_pt - reserved_for_ras -
238 atomic64_read(&adev->vram_pin_size);
239 if (adev->kfd.vram_used[xcp_id] + vram_needed > vram_available) {
240 ret = -ENOMEM;
241 goto release;
242 }
243 }
244
245 /* Update memory accounting by decreasing available system
246 * memory, TTM memory and GPU memory as computed above
247 */
248 WARN_ONCE(vram_needed && !adev,
249 "adev reference can't be null when vram is used");
250 if (adev && xcp_id >= 0) {
251 adev->kfd.vram_used[xcp_id] += vram_needed;
252 adev->kfd.vram_used_aligned[xcp_id] +=
253 adev->apu_prefer_gtt ?
254 vram_needed :
255 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
256 }
257 kfd_mem_limit.system_mem_used += system_mem_needed;
258 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
259
260release:
261 spin_unlock(&kfd_mem_limit.mem_limit_lock);
262 return ret;
263}
264
265void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
266 uint64_t size, u32 alloc_flag, int8_t xcp_id)
267{
268 spin_lock(&kfd_mem_limit.mem_limit_lock);
269
270 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
271 kfd_mem_limit.system_mem_used -= size;
272 kfd_mem_limit.ttm_mem_used -= size;
273 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
274 WARN_ONCE(!adev,
275 "adev reference can't be null when alloc mem flags vram is set");
276 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
277 goto release;
278
279 if (adev) {
280 adev->kfd.vram_used[xcp_id] -= size;
281 if (adev->apu_prefer_gtt) {
282 adev->kfd.vram_used_aligned[xcp_id] -= size;
283 kfd_mem_limit.system_mem_used -= size;
284 kfd_mem_limit.ttm_mem_used -= size;
285 } else {
286 adev->kfd.vram_used_aligned[xcp_id] -=
287 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
288 }
289 }
290 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
291 kfd_mem_limit.system_mem_used -= size;
292 } else if (!(alloc_flag &
293 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
294 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
295 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
296 goto release;
297 }
298 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
299 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
300 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
301 "KFD TTM memory accounting unbalanced");
302 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
303 "KFD system memory accounting unbalanced");
304
305release:
306 spin_unlock(&kfd_mem_limit.mem_limit_lock);
307}
308
309void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
310{
311 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
312 u32 alloc_flags = bo->kfd_bo->alloc_flags;
313 u64 size = amdgpu_bo_size(bo);
314
315 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
316 bo->xcp_id);
317
318 kfree(bo->kfd_bo);
319}
320
321/**
322 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
323 * about USERPTR or DOOREBELL or MMIO BO.
324 *
325 * @adev: Device for which dmamap BO is being created
326 * @mem: BO of peer device that is being DMA mapped. Provides parameters
327 * in building the dmamap BO
328 * @bo_out: Output parameter updated with handle of dmamap BO
329 */
330static int
331create_dmamap_sg_bo(struct amdgpu_device *adev,
332 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
333{
334 struct drm_gem_object *gem_obj;
335 int ret;
336 uint64_t flags = 0;
337
338 ret = amdgpu_bo_reserve(mem->bo, false);
339 if (ret)
340 return ret;
341
342 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
343 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
344 AMDGPU_GEM_CREATE_UNCACHED);
345
346 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
347 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
348 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
349
350 amdgpu_bo_unreserve(mem->bo);
351
352 if (ret) {
353 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
354 return -EINVAL;
355 }
356
357 *bo_out = gem_to_amdgpu_bo(gem_obj);
358 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
359 return ret;
360}
361
362/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
363 * reservation object.
364 *
365 * @bo: [IN] Remove eviction fence(s) from this BO
366 * @ef: [IN] This eviction fence is removed if it
367 * is present in the shared list.
368 *
369 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
370 */
371static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
372 struct amdgpu_amdkfd_fence *ef)
373{
374 struct dma_fence *replacement;
375
376 if (!ef)
377 return -EINVAL;
378
379 /* TODO: Instead of block before we should use the fence of the page
380 * table update and TLB flush here directly.
381 */
382 replacement = dma_fence_get_stub();
383 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
384 replacement, DMA_RESV_USAGE_BOOKKEEP);
385 dma_fence_put(replacement);
386 return 0;
387}
388
389/**
390 * amdgpu_amdkfd_remove_all_eviction_fences - Remove all eviction fences
391 * @bo: the BO where to remove the evictions fences from.
392 *
393 * This functions should only be used on release when all references to the BO
394 * are already dropped. We remove the eviction fence from the private copy of
395 * the dma_resv object here since that is what is used during release to
396 * determine of the BO is idle or not.
397 */
398void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo)
399{
400 struct dma_resv *resv = &bo->tbo.base._resv;
401 struct dma_fence *fence, *stub;
402 struct dma_resv_iter cursor;
403
404 dma_resv_assert_held(resv);
405
406 stub = dma_fence_get_stub();
407 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
408 if (!to_amdgpu_amdkfd_fence(fence))
409 continue;
410
411 dma_resv_replace_fences(resv, fence->context, stub,
412 DMA_RESV_USAGE_BOOKKEEP);
413 }
414 dma_fence_put(stub);
415}
416
417static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
418 bool wait)
419{
420 struct ttm_operation_ctx ctx = { false, false };
421 int ret;
422
423 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
424 "Called with userptr BO"))
425 return -EINVAL;
426
427 /* bo has been pinned, not need validate it */
428 if (bo->tbo.pin_count)
429 return 0;
430
431 amdgpu_bo_placement_from_domain(bo, domain);
432
433 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
434 if (ret)
435 goto validate_fail;
436 if (wait)
437 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
438
439validate_fail:
440 return ret;
441}
442
443int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
444 uint32_t domain,
445 struct dma_fence *fence)
446{
447 int ret = amdgpu_bo_reserve(bo, false);
448
449 if (ret)
450 return ret;
451
452 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
453 if (ret)
454 goto unreserve_out;
455
456 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
457 if (ret)
458 goto unreserve_out;
459
460 dma_resv_add_fence(bo->tbo.base.resv, fence,
461 DMA_RESV_USAGE_BOOKKEEP);
462
463unreserve_out:
464 amdgpu_bo_unreserve(bo);
465
466 return ret;
467}
468
469static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
470{
471 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
472}
473
474/* vm_validate_pt_pd_bos - Validate page table and directory BOs
475 *
476 * Page directories are not updated here because huge page handling
477 * during page table updates can invalidate page directory entries
478 * again. Page directories are only updated after updating page
479 * tables.
480 */
481static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm,
482 struct ww_acquire_ctx *ticket)
483{
484 struct amdgpu_bo *pd = vm->root.bo;
485 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
486 int ret;
487
488 ret = amdgpu_vm_validate(adev, vm, ticket,
489 amdgpu_amdkfd_validate_vm_bo, NULL);
490 if (ret) {
491 pr_err("failed to validate PT BOs\n");
492 return ret;
493 }
494
495 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
496
497 return 0;
498}
499
500static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
501{
502 struct amdgpu_bo *pd = vm->root.bo;
503 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
504 int ret;
505
506 ret = amdgpu_vm_update_pdes(adev, vm, false);
507 if (ret)
508 return ret;
509
510 return amdgpu_sync_fence(sync, vm->last_update, GFP_KERNEL);
511}
512
513static uint64_t get_pte_flags(struct amdgpu_device *adev, struct amdgpu_vm *vm,
514 struct kgd_mem *mem)
515{
516 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
517 AMDGPU_VM_MTYPE_DEFAULT;
518
519 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
520 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
521 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
522 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
523
524 return mapping_flags;
525}
526
527/**
528 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
529 * @addr: The starting address to point to
530 * @size: Size of memory area in bytes being pointed to
531 *
532 * Allocates an instance of sg_table and initializes it to point to memory
533 * area specified by input parameters. The address used to build is assumed
534 * to be DMA mapped, if needed.
535 *
536 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
537 * because they are physically contiguous.
538 *
539 * Return: Initialized instance of SG Table or NULL
540 */
541static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
542{
543 struct sg_table *sg = kmalloc_obj(*sg);
544
545 if (!sg)
546 return NULL;
547 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
548 kfree(sg);
549 return NULL;
550 }
551 sg_dma_address(sg->sgl) = addr;
552 sg->sgl->length = size;
553#ifdef CONFIG_NEED_SG_DMA_LENGTH
554 sg->sgl->dma_length = size;
555#endif
556 return sg;
557}
558
559static int
560kfd_mem_dmamap_userptr(struct kgd_mem *mem,
561 struct kfd_mem_attachment *attachment)
562{
563 enum dma_data_direction direction =
564 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
565 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
566 struct ttm_operation_ctx ctx = {.interruptible = true};
567 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
568 struct amdgpu_device *adev = attachment->adev;
569 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
570 struct ttm_tt *ttm = bo->tbo.ttm;
571 int ret;
572
573 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
574 return -EINVAL;
575
576 ttm->sg = kmalloc_obj(*ttm->sg);
577 if (unlikely(!ttm->sg))
578 return -ENOMEM;
579
580 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
581 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
582 ttm->num_pages, 0,
583 (u64)ttm->num_pages << PAGE_SHIFT,
584 GFP_KERNEL);
585 if (unlikely(ret))
586 goto free_sg;
587
588 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
589 if (unlikely(ret))
590 goto release_sg;
591
592 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
593 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
594 if (ret)
595 goto unmap_sg;
596
597 return 0;
598
599unmap_sg:
600 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
601release_sg:
602 pr_err("DMA map userptr failed: %d\n", ret);
603 sg_free_table(ttm->sg);
604free_sg:
605 kfree(ttm->sg);
606 ttm->sg = NULL;
607 return ret;
608}
609
610static int
611kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
612{
613 struct ttm_operation_ctx ctx = {.interruptible = true};
614 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
615
616 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
617 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
618}
619
620/**
621 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
622 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
623 * @attachment: Virtual address attachment of the BO on accessing device
624 *
625 * An access request from the device that owns DOORBELL does not require DMA mapping.
626 * This is because the request doesn't go through PCIe root complex i.e. it instead
627 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
628 *
629 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
630 * device ownership. This is because access requests for MMIO go through PCIe root
631 * complex.
632 *
633 * This is accomplished in two steps:
634 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
635 * in updating requesting device's page table
636 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
637 * accessible. This allows an update of requesting device's page table
638 * with entries associated with DOOREBELL or MMIO memory
639 *
640 * This method is invoked in the following contexts:
641 * - Mapping of DOORBELL or MMIO BO of same or peer device
642 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
643 *
644 * Return: ZERO if successful, NON-ZERO otherwise
645 */
646static int
647kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
648 struct kfd_mem_attachment *attachment)
649{
650 struct ttm_operation_ctx ctx = {.interruptible = true};
651 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
652 struct amdgpu_device *adev = attachment->adev;
653 struct ttm_tt *ttm = bo->tbo.ttm;
654 enum dma_data_direction dir;
655 dma_addr_t dma_addr;
656 bool mmio;
657 int ret;
658
659 /* Expect SG Table of dmapmap BO to be NULL */
660 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
661 if (unlikely(ttm->sg)) {
662 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
663 return -EINVAL;
664 }
665
666 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
667 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
668 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
669 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
670 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
671 dma_addr = dma_map_resource(adev->dev, dma_addr,
672 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
673 ret = dma_mapping_error(adev->dev, dma_addr);
674 if (unlikely(ret))
675 return ret;
676 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
677
678 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
679 if (unlikely(!ttm->sg)) {
680 ret = -ENOMEM;
681 goto unmap_sg;
682 }
683
684 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
685 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
686 if (unlikely(ret))
687 goto free_sg;
688
689 return ret;
690
691free_sg:
692 sg_free_table(ttm->sg);
693 kfree(ttm->sg);
694 ttm->sg = NULL;
695unmap_sg:
696 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
697 dir, DMA_ATTR_SKIP_CPU_SYNC);
698 return ret;
699}
700
701static int
702kfd_mem_dmamap_attachment(struct kgd_mem *mem,
703 struct kfd_mem_attachment *attachment)
704{
705 switch (attachment->type) {
706 case KFD_MEM_ATT_SHARED:
707 return 0;
708 case KFD_MEM_ATT_USERPTR:
709 return kfd_mem_dmamap_userptr(mem, attachment);
710 case KFD_MEM_ATT_DMABUF:
711 return kfd_mem_dmamap_dmabuf(attachment);
712 case KFD_MEM_ATT_SG:
713 return kfd_mem_dmamap_sg_bo(mem, attachment);
714 default:
715 WARN_ON_ONCE(1);
716 }
717 return -EINVAL;
718}
719
720static void
721kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
722 struct kfd_mem_attachment *attachment)
723{
724 enum dma_data_direction direction =
725 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
726 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
727 struct ttm_operation_ctx ctx = {.interruptible = false};
728 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
729 struct amdgpu_device *adev = attachment->adev;
730 struct ttm_tt *ttm = bo->tbo.ttm;
731
732 if (unlikely(!ttm->sg))
733 return;
734
735 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
736 (void)ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
737
738 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
739 sg_free_table(ttm->sg);
740 kfree(ttm->sg);
741 ttm->sg = NULL;
742}
743
744static void
745kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
746{
747 /* This is a no-op. We don't want to trigger eviction fences when
748 * unmapping DMABufs. Therefore the invalidation (moving to system
749 * domain) is done in kfd_mem_dmamap_dmabuf.
750 */
751}
752
753/**
754 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
755 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
756 * @attachment: Virtual address attachment of the BO on accessing device
757 *
758 * The method performs following steps:
759 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
760 * - Free SG Table that is used to encapsulate DMA mapped memory of
761 * peer device's DOORBELL or MMIO memory
762 *
763 * This method is invoked in the following contexts:
764 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
765 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
766 *
767 * Return: void
768 */
769static void
770kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
771 struct kfd_mem_attachment *attachment)
772{
773 struct ttm_operation_ctx ctx = {.interruptible = true};
774 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
775 struct amdgpu_device *adev = attachment->adev;
776 struct ttm_tt *ttm = bo->tbo.ttm;
777 enum dma_data_direction dir;
778
779 if (unlikely(!ttm->sg)) {
780 pr_debug("SG Table of BO is NULL");
781 return;
782 }
783
784 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
785 (void)ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
786
787 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
788 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
789 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
790 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
791 sg_free_table(ttm->sg);
792 kfree(ttm->sg);
793 ttm->sg = NULL;
794 bo->tbo.sg = NULL;
795}
796
797static void
798kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
799 struct kfd_mem_attachment *attachment)
800{
801 switch (attachment->type) {
802 case KFD_MEM_ATT_SHARED:
803 break;
804 case KFD_MEM_ATT_USERPTR:
805 kfd_mem_dmaunmap_userptr(mem, attachment);
806 break;
807 case KFD_MEM_ATT_DMABUF:
808 kfd_mem_dmaunmap_dmabuf(attachment);
809 break;
810 case KFD_MEM_ATT_SG:
811 kfd_mem_dmaunmap_sg_bo(mem, attachment);
812 break;
813 default:
814 WARN_ON_ONCE(1);
815 }
816}
817
818static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
819{
820 if (!mem->dmabuf) {
821 struct amdgpu_device *bo_adev;
822 struct dma_buf *dmabuf;
823
824 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
825 dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file,
826 mem->gem_handle,
827 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
828 DRM_RDWR : 0);
829 if (IS_ERR(dmabuf))
830 return PTR_ERR(dmabuf);
831 mem->dmabuf = dmabuf;
832 }
833
834 return 0;
835}
836
837static int
838kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
839 struct amdgpu_bo **bo)
840{
841 struct drm_gem_object *gobj;
842 int ret;
843
844 ret = kfd_mem_export_dmabuf(mem);
845 if (ret)
846 return ret;
847
848 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
849 if (IS_ERR(gobj))
850 return PTR_ERR(gobj);
851
852 *bo = gem_to_amdgpu_bo(gobj);
853 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
854
855 return 0;
856}
857
858/* kfd_mem_attach - Add a BO to a VM
859 *
860 * Everything that needs to bo done only once when a BO is first added
861 * to a VM. It can later be mapped and unmapped many times without
862 * repeating these steps.
863 *
864 * 0. Create BO for DMA mapping, if needed
865 * 1. Allocate and initialize BO VA entry data structure
866 * 2. Add BO to the VM
867 * 3. Determine ASIC-specific PTE flags
868 * 4. Alloc page tables and directories if needed
869 * 4a. Validate new page tables and directories
870 */
871static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
872 struct amdgpu_vm *vm, bool is_aql)
873{
874 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
875 unsigned long bo_size = mem->bo->tbo.base.size;
876 uint64_t va = mem->va;
877 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
878 struct amdgpu_bo *bo[2] = {NULL, NULL};
879 struct amdgpu_bo_va *bo_va;
880 bool same_hive = false;
881 struct drm_exec exec;
882 int i, ret;
883
884 if (!va) {
885 pr_err("Invalid VA when adding BO to VM\n");
886 return -EINVAL;
887 }
888
889 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
890 *
891 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
892 * In contrast the access path of VRAM BOs depens upon the type of
893 * link that connects the peer device. Access over PCIe is allowed
894 * if peer device has large BAR. In contrast, access over xGMI is
895 * allowed for both small and large BAR configurations of peer device
896 */
897 if ((adev != bo_adev && !adev->apu_prefer_gtt) &&
898 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
899 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
900 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
901 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
902 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
903 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
904 return -EINVAL;
905 }
906
907 for (i = 0; i <= is_aql; i++) {
908 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
909 if (unlikely(!attachment[i])) {
910 ret = -ENOMEM;
911 goto unwind;
912 }
913
914 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
915 va + bo_size, vm);
916
917 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
918 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
919 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
920 same_hive) {
921 /* Mappings on the local GPU, or VRAM mappings in the
922 * local hive, or userptr, or GTT mapping can reuse dma map
923 * address space share the original BO
924 */
925 attachment[i]->type = KFD_MEM_ATT_SHARED;
926 bo[i] = mem->bo;
927 drm_gem_object_get(&bo[i]->tbo.base);
928 } else if (i > 0) {
929 /* Multiple mappings on the same GPU share the BO */
930 attachment[i]->type = KFD_MEM_ATT_SHARED;
931 bo[i] = bo[0];
932 drm_gem_object_get(&bo[i]->tbo.base);
933 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
934 /* Create an SG BO to DMA-map userptrs on other GPUs */
935 attachment[i]->type = KFD_MEM_ATT_USERPTR;
936 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
937 if (ret)
938 goto unwind;
939 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
940 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
941 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
942 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
943 "Handing invalid SG BO in ATTACH request");
944 attachment[i]->type = KFD_MEM_ATT_SG;
945 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
946 if (ret)
947 goto unwind;
948 /* Enable acces to GTT and VRAM BOs of peer devices */
949 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
950 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
951 attachment[i]->type = KFD_MEM_ATT_DMABUF;
952 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
953 if (ret)
954 goto unwind;
955 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
956 } else {
957 WARN_ONCE(true, "Handling invalid ATTACH request");
958 ret = -EINVAL;
959 goto unwind;
960 }
961
962 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
963 drm_exec_until_all_locked(&exec) {
964 ret = amdgpu_vm_lock_pd(vm, &exec, 0);
965 drm_exec_retry_on_contention(&exec);
966 if (unlikely(ret))
967 goto unwind;
968 ret = drm_exec_lock_obj(&exec, &bo[i]->tbo.base);
969 drm_exec_retry_on_contention(&exec);
970 if (unlikely(ret))
971 goto unwind;
972 }
973
974 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
975 if (!bo_va)
976 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
977 else
978 ++bo_va->ref_count;
979 attachment[i]->bo_va = bo_va;
980 drm_exec_fini(&exec);
981 if (unlikely(!attachment[i]->bo_va)) {
982 ret = -ENOMEM;
983 pr_err("Failed to add BO object to VM. ret == %d\n",
984 ret);
985 goto unwind;
986 }
987 attachment[i]->va = va;
988 attachment[i]->pte_flags = get_pte_flags(adev, vm, mem);
989 attachment[i]->adev = adev;
990 list_add(&attachment[i]->list, &mem->attachments);
991
992 va += bo_size;
993 }
994
995 return 0;
996
997unwind:
998 for (; i >= 0; i--) {
999 if (!attachment[i])
1000 continue;
1001 if (attachment[i]->bo_va) {
1002 (void)amdgpu_bo_reserve(bo[i], true);
1003 if (--attachment[i]->bo_va->ref_count == 0)
1004 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
1005 amdgpu_bo_unreserve(bo[i]);
1006 list_del(&attachment[i]->list);
1007 }
1008 if (bo[i])
1009 drm_gem_object_put(&bo[i]->tbo.base);
1010 kfree(attachment[i]);
1011 }
1012 return ret;
1013}
1014
1015static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1016{
1017 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1018
1019 pr_debug("\t remove VA 0x%llx in entry %p\n",
1020 attachment->va, attachment);
1021 if (--attachment->bo_va->ref_count == 0)
1022 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1023 drm_gem_object_put(&bo->tbo.base);
1024 list_del(&attachment->list);
1025 kfree(attachment);
1026}
1027
1028static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1029 struct amdkfd_process_info *process_info,
1030 bool userptr)
1031{
1032 mutex_lock(&process_info->lock);
1033 if (userptr)
1034 list_add_tail(&mem->validate_list,
1035 &process_info->userptr_valid_list);
1036 else
1037 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1038 mutex_unlock(&process_info->lock);
1039}
1040
1041static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1042 struct amdkfd_process_info *process_info)
1043{
1044 mutex_lock(&process_info->lock);
1045 list_del(&mem->validate_list);
1046 mutex_unlock(&process_info->lock);
1047}
1048
1049/* Initializes user pages. It registers the MMU notifier and validates
1050 * the userptr BO in the GTT domain.
1051 *
1052 * The BO must already be on the userptr_valid_list. Otherwise an
1053 * eviction and restore may happen that leaves the new BO unmapped
1054 * with the user mode queues running.
1055 *
1056 * Takes the process_info->lock to protect against concurrent restore
1057 * workers.
1058 *
1059 * Returns 0 for success, negative errno for errors.
1060 */
1061static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1062 bool criu_resume)
1063{
1064 struct amdkfd_process_info *process_info = mem->process_info;
1065 struct amdgpu_bo *bo = mem->bo;
1066 struct ttm_operation_ctx ctx = { true, false };
1067 struct amdgpu_hmm_range *range;
1068 int ret = 0;
1069
1070 mutex_lock(&process_info->lock);
1071
1072 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1073 if (ret) {
1074 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1075 goto out;
1076 }
1077
1078 ret = amdgpu_hmm_register(bo, user_addr);
1079 if (ret) {
1080 pr_err("%s: Failed to register MMU notifier: %d\n",
1081 __func__, ret);
1082 goto out;
1083 }
1084
1085 if (criu_resume) {
1086 /*
1087 * During a CRIU restore operation, the userptr buffer objects
1088 * will be validated in the restore_userptr_work worker at a
1089 * later stage when it is scheduled by another ioctl called by
1090 * CRIU master process for the target pid for restore.
1091 */
1092 mutex_lock(&process_info->notifier_lock);
1093 mem->invalid++;
1094 mutex_unlock(&process_info->notifier_lock);
1095 mutex_unlock(&process_info->lock);
1096 return 0;
1097 }
1098
1099 range = amdgpu_hmm_range_alloc(NULL);
1100 if (unlikely(!range)) {
1101 ret = -ENOMEM;
1102 goto unregister_out;
1103 }
1104
1105 ret = amdgpu_ttm_tt_get_user_pages(bo, range);
1106 if (ret) {
1107 amdgpu_hmm_range_free(range);
1108 if (ret == -EAGAIN)
1109 pr_debug("Failed to get user pages, try again\n");
1110 else
1111 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1112 goto unregister_out;
1113 }
1114
1115 ret = amdgpu_bo_reserve(bo, true);
1116 if (ret) {
1117 pr_err("%s: Failed to reserve BO\n", __func__);
1118 goto release_out;
1119 }
1120
1121 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range);
1122
1123 amdgpu_bo_placement_from_domain(bo, mem->domain);
1124 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1125 if (ret)
1126 pr_err("%s: failed to validate BO\n", __func__);
1127 amdgpu_bo_unreserve(bo);
1128
1129release_out:
1130 amdgpu_hmm_range_free(range);
1131unregister_out:
1132 if (ret)
1133 amdgpu_hmm_unregister(bo);
1134out:
1135 mutex_unlock(&process_info->lock);
1136 return ret;
1137}
1138
1139/* Reserving a BO and its page table BOs must happen atomically to
1140 * avoid deadlocks. Some operations update multiple VMs at once. Track
1141 * all the reservation info in a context structure. Optionally a sync
1142 * object can track VM updates.
1143 */
1144struct bo_vm_reservation_context {
1145 /* DRM execution context for the reservation */
1146 struct drm_exec exec;
1147 /* Number of VMs reserved */
1148 unsigned int n_vms;
1149 /* Pointer to sync object */
1150 struct amdgpu_sync *sync;
1151};
1152
1153enum bo_vm_match {
1154 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1155 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1156 BO_VM_ALL, /* Match all VMs a BO was added to */
1157};
1158
1159/**
1160 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1161 * @mem: KFD BO structure.
1162 * @vm: the VM to reserve.
1163 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1164 */
1165static int reserve_bo_and_vm(struct kgd_mem *mem,
1166 struct amdgpu_vm *vm,
1167 struct bo_vm_reservation_context *ctx)
1168{
1169 struct amdgpu_bo *bo = mem->bo;
1170 int ret;
1171
1172 WARN_ON(!vm);
1173
1174 ctx->n_vms = 1;
1175 ctx->sync = &mem->sync;
1176 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1177 drm_exec_until_all_locked(&ctx->exec) {
1178 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1179 drm_exec_retry_on_contention(&ctx->exec);
1180 if (unlikely(ret))
1181 goto error;
1182
1183 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1184 drm_exec_retry_on_contention(&ctx->exec);
1185 if (unlikely(ret))
1186 goto error;
1187 }
1188 return 0;
1189
1190error:
1191 pr_err("Failed to reserve buffers in ttm.\n");
1192 drm_exec_fini(&ctx->exec);
1193 return ret;
1194}
1195
1196/**
1197 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1198 * @mem: KFD BO structure.
1199 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1200 * is used. Otherwise, a single VM associated with the BO.
1201 * @map_type: the mapping status that will be used to filter the VMs.
1202 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1203 *
1204 * Returns 0 for success, negative for failure.
1205 */
1206static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1207 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1208 struct bo_vm_reservation_context *ctx)
1209{
1210 struct kfd_mem_attachment *entry;
1211 struct amdgpu_bo *bo = mem->bo;
1212 int ret;
1213
1214 ctx->sync = &mem->sync;
1215 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
1216 DRM_EXEC_IGNORE_DUPLICATES, 0);
1217 drm_exec_until_all_locked(&ctx->exec) {
1218 ctx->n_vms = 0;
1219 list_for_each_entry(entry, &mem->attachments, list) {
1220 if ((vm && vm != entry->bo_va->base.vm) ||
1221 (entry->is_mapped != map_type
1222 && map_type != BO_VM_ALL))
1223 continue;
1224
1225 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1226 &ctx->exec, 2);
1227 drm_exec_retry_on_contention(&ctx->exec);
1228 if (unlikely(ret))
1229 goto error;
1230 ++ctx->n_vms;
1231 }
1232
1233 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1234 drm_exec_retry_on_contention(&ctx->exec);
1235 if (unlikely(ret))
1236 goto error;
1237 }
1238 return 0;
1239
1240error:
1241 pr_err("Failed to reserve buffers in ttm.\n");
1242 drm_exec_fini(&ctx->exec);
1243 return ret;
1244}
1245
1246/**
1247 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1248 * @ctx: Reservation context to unreserve
1249 * @wait: Optionally wait for a sync object representing pending VM updates
1250 * @intr: Whether the wait is interruptible
1251 *
1252 * Also frees any resources allocated in
1253 * reserve_bo_and_(cond_)vm(s). Returns the status from
1254 * amdgpu_sync_wait.
1255 */
1256static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1257 bool wait, bool intr)
1258{
1259 int ret = 0;
1260
1261 if (wait)
1262 ret = amdgpu_sync_wait(ctx->sync, intr);
1263
1264 drm_exec_fini(&ctx->exec);
1265 ctx->sync = NULL;
1266 return ret;
1267}
1268
1269static int unmap_bo_from_gpuvm(struct kgd_mem *mem,
1270 struct kfd_mem_attachment *entry,
1271 struct amdgpu_sync *sync)
1272{
1273 struct amdgpu_bo_va *bo_va = entry->bo_va;
1274 struct amdgpu_device *adev = entry->adev;
1275 struct amdgpu_vm *vm = bo_va->base.vm;
1276
1277 if (bo_va->queue_refcount) {
1278 pr_debug("bo_va->queue_refcount %d\n", bo_va->queue_refcount);
1279 return -EBUSY;
1280 }
1281
1282 (void)amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1283
1284 /* VM entity stopped if process killed, don't clear freed pt bo */
1285 if (!amdgpu_vm_ready(vm))
1286 return 0;
1287
1288 (void)amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1289
1290 (void)amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL);
1291
1292 return 0;
1293}
1294
1295static int update_gpuvm_pte(struct kgd_mem *mem,
1296 struct kfd_mem_attachment *entry,
1297 struct amdgpu_sync *sync)
1298{
1299 struct amdgpu_bo_va *bo_va = entry->bo_va;
1300 struct amdgpu_device *adev = entry->adev;
1301 int ret;
1302
1303 ret = kfd_mem_dmamap_attachment(mem, entry);
1304 if (ret)
1305 return ret;
1306
1307 /* Update the page tables */
1308 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1309 if (ret) {
1310 pr_err("amdgpu_vm_bo_update failed\n");
1311 return ret;
1312 }
1313
1314 return amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL);
1315}
1316
1317static int map_bo_to_gpuvm(struct kgd_mem *mem,
1318 struct kfd_mem_attachment *entry,
1319 struct amdgpu_sync *sync,
1320 bool no_update_pte)
1321{
1322 int ret;
1323
1324 /* Set virtual address for the allocation */
1325 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1326 amdgpu_bo_size(entry->bo_va->base.bo),
1327 entry->pte_flags);
1328 if (ret) {
1329 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1330 entry->va, ret);
1331 return ret;
1332 }
1333
1334 if (no_update_pte)
1335 return 0;
1336
1337 ret = update_gpuvm_pte(mem, entry, sync);
1338 if (ret) {
1339 pr_err("update_gpuvm_pte() failed\n");
1340 goto update_gpuvm_pte_failed;
1341 }
1342
1343 return 0;
1344
1345update_gpuvm_pte_failed:
1346 unmap_bo_from_gpuvm(mem, entry, sync);
1347 kfd_mem_dmaunmap_attachment(mem, entry);
1348 return ret;
1349}
1350
1351static int process_validate_vms(struct amdkfd_process_info *process_info,
1352 struct ww_acquire_ctx *ticket)
1353{
1354 struct amdgpu_vm *peer_vm;
1355 int ret;
1356
1357 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1358 vm_list_node) {
1359 ret = vm_validate_pt_pd_bos(peer_vm, ticket);
1360 if (ret)
1361 return ret;
1362 }
1363
1364 return 0;
1365}
1366
1367static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1368 struct amdgpu_sync *sync)
1369{
1370 struct amdgpu_vm *peer_vm;
1371 int ret;
1372
1373 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1374 vm_list_node) {
1375 struct amdgpu_bo *pd = peer_vm->root.bo;
1376
1377 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1378 AMDGPU_SYNC_NE_OWNER,
1379 AMDGPU_FENCE_OWNER_KFD);
1380 if (ret)
1381 return ret;
1382 }
1383
1384 return 0;
1385}
1386
1387static int process_update_pds(struct amdkfd_process_info *process_info,
1388 struct amdgpu_sync *sync)
1389{
1390 struct amdgpu_vm *peer_vm;
1391 int ret;
1392
1393 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1394 vm_list_node) {
1395 ret = vm_update_pds(peer_vm, sync);
1396 if (ret)
1397 return ret;
1398 }
1399
1400 return 0;
1401}
1402
1403static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1404 struct dma_fence **ef)
1405{
1406 struct amdkfd_process_info *info = NULL;
1407 struct kfd_process *process = NULL;
1408 int ret;
1409
1410 process = container_of(process_info, struct kfd_process, kgd_process_info);
1411 if (!*process_info) {
1412 info = kzalloc_obj(*info);
1413 if (!info)
1414 return -ENOMEM;
1415
1416 mutex_init(&info->lock);
1417 mutex_init(&info->notifier_lock);
1418 INIT_LIST_HEAD(&info->vm_list_head);
1419 INIT_LIST_HEAD(&info->kfd_bo_list);
1420 INIT_LIST_HEAD(&info->userptr_valid_list);
1421 INIT_LIST_HEAD(&info->userptr_inval_list);
1422
1423 info->eviction_fence =
1424 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1425 current->mm,
1426 process->context_id);
1427 if (!info->eviction_fence) {
1428 pr_err("Failed to create eviction fence\n");
1429 ret = -ENOMEM;
1430 goto create_evict_fence_fail;
1431 }
1432
1433 info->pid = get_task_pid(current, PIDTYPE_TGID);
1434 INIT_DELAYED_WORK(&info->restore_userptr_work,
1435 amdgpu_amdkfd_restore_userptr_worker);
1436
1437 info->context_id = process->context_id;
1438
1439 *process_info = info;
1440 }
1441
1442 if (cmpxchg(&vm->process_info, NULL, *process_info) != NULL) {
1443 ret = -EINVAL;
1444 goto already_acquired;
1445 }
1446
1447 /* Validate page directory and attach eviction fence */
1448 ret = amdgpu_bo_reserve(vm->root.bo, true);
1449 if (ret)
1450 goto reserve_pd_fail;
1451 ret = vm_validate_pt_pd_bos(vm, NULL);
1452 if (ret) {
1453 pr_err("validate_pt_pd_bos() failed\n");
1454 goto validate_pd_fail;
1455 }
1456 ret = amdgpu_bo_sync_wait(vm->root.bo,
1457 AMDGPU_FENCE_OWNER_KFD, false);
1458 if (ret)
1459 goto wait_pd_fail;
1460 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1461 if (ret)
1462 goto reserve_shared_fail;
1463 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1464 &vm->process_info->eviction_fence->base,
1465 DMA_RESV_USAGE_BOOKKEEP);
1466 amdgpu_bo_unreserve(vm->root.bo);
1467
1468 /* Update process info */
1469 mutex_lock(&vm->process_info->lock);
1470 list_add_tail(&vm->vm_list_node,
1471 &(vm->process_info->vm_list_head));
1472 vm->process_info->n_vms++;
1473 if (ef)
1474 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1475 mutex_unlock(&vm->process_info->lock);
1476
1477 return 0;
1478
1479reserve_shared_fail:
1480wait_pd_fail:
1481validate_pd_fail:
1482 amdgpu_bo_unreserve(vm->root.bo);
1483reserve_pd_fail:
1484 vm->process_info = NULL;
1485already_acquired:
1486 if (info) {
1487 dma_fence_put(&info->eviction_fence->base);
1488 *process_info = NULL;
1489 put_pid(info->pid);
1490create_evict_fence_fail:
1491 mutex_destroy(&info->lock);
1492 mutex_destroy(&info->notifier_lock);
1493 kfree(info);
1494 }
1495 return ret;
1496}
1497
1498/**
1499 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1500 * @bo: Handle of buffer object being pinned
1501 * @domain: Domain into which BO should be pinned
1502 *
1503 * - USERPTR BOs are UNPINNABLE and will return error
1504 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1505 * PIN count incremented. It is valid to PIN a BO multiple times
1506 *
1507 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1508 */
1509static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1510{
1511 int ret = 0;
1512
1513 ret = amdgpu_bo_reserve(bo, false);
1514 if (unlikely(ret))
1515 return ret;
1516
1517 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) {
1518 /*
1519 * If bo is not contiguous on VRAM, move to system memory first to ensure
1520 * we can get contiguous VRAM space after evicting other BOs.
1521 */
1522 if (!(bo->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) {
1523 struct ttm_operation_ctx ctx = { true, false };
1524
1525 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
1526 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1527 if (unlikely(ret)) {
1528 pr_debug("validate bo 0x%p to GTT failed %d\n", &bo->tbo, ret);
1529 goto out;
1530 }
1531 }
1532 }
1533
1534 ret = amdgpu_bo_pin(bo, domain);
1535 if (ret)
1536 pr_err("Error in Pinning BO to domain: %d\n", domain);
1537
1538 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1539out:
1540 amdgpu_bo_unreserve(bo);
1541 return ret;
1542}
1543
1544/**
1545 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1546 * @bo: Handle of buffer object being unpinned
1547 *
1548 * - Is a illegal request for USERPTR BOs and is ignored
1549 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1550 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1551 */
1552static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1553{
1554 int ret = 0;
1555
1556 ret = amdgpu_bo_reserve(bo, false);
1557 if (unlikely(ret))
1558 return;
1559
1560 amdgpu_bo_unpin(bo);
1561 amdgpu_bo_unreserve(bo);
1562}
1563
1564int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1565 struct amdgpu_vm *avm,
1566 void **process_info,
1567 struct dma_fence **ef)
1568{
1569 int ret;
1570
1571 /* Already a compute VM? */
1572 if (avm->process_info)
1573 return -EINVAL;
1574
1575 /* Convert VM into a compute VM */
1576 ret = amdgpu_vm_make_compute(adev, avm);
1577 if (ret)
1578 return ret;
1579
1580 /* Initialize KFD part of the VM and process info */
1581 ret = init_kfd_vm(avm, process_info, ef);
1582 if (ret)
1583 return ret;
1584
1585 amdgpu_vm_set_task_info(avm);
1586
1587 return 0;
1588}
1589
1590void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1591 struct amdgpu_vm *vm)
1592{
1593 struct amdkfd_process_info *process_info = vm->process_info;
1594
1595 if (!process_info)
1596 return;
1597
1598 /* Update process info */
1599 mutex_lock(&process_info->lock);
1600 process_info->n_vms--;
1601 list_del(&vm->vm_list_node);
1602 mutex_unlock(&process_info->lock);
1603
1604 vm->process_info = NULL;
1605
1606 /* Release per-process resources when last compute VM is destroyed */
1607 if (!process_info->n_vms) {
1608 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1609 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1610 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1611
1612 dma_fence_put(&process_info->eviction_fence->base);
1613 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1614 put_pid(process_info->pid);
1615 mutex_destroy(&process_info->lock);
1616 mutex_destroy(&process_info->notifier_lock);
1617 kfree(process_info);
1618 }
1619}
1620
1621uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1622{
1623 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1624 struct amdgpu_bo *pd = avm->root.bo;
1625 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1626
1627 if (adev->asic_type < CHIP_VEGA10)
1628 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1629 return avm->pd_phys_addr;
1630}
1631
1632void amdgpu_amdkfd_block_mmu_notifications(void *p)
1633{
1634 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1635
1636 mutex_lock(&pinfo->lock);
1637 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1638 mutex_unlock(&pinfo->lock);
1639}
1640
1641int amdgpu_amdkfd_criu_resume(void *p)
1642{
1643 int ret = 0;
1644 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1645
1646 mutex_lock(&pinfo->lock);
1647 pr_debug("scheduling work\n");
1648 mutex_lock(&pinfo->notifier_lock);
1649 pinfo->evicted_bos++;
1650 mutex_unlock(&pinfo->notifier_lock);
1651 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1652 ret = -EINVAL;
1653 goto out_unlock;
1654 }
1655 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1656 queue_delayed_work(system_freezable_wq,
1657 &pinfo->restore_userptr_work, 0);
1658
1659out_unlock:
1660 mutex_unlock(&pinfo->lock);
1661 return ret;
1662}
1663
1664size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1665 uint8_t xcp_id)
1666{
1667 uint64_t reserved_for_pt =
1668 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1669 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1670 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0);
1671 ssize_t available;
1672 uint64_t vram_available, system_mem_available, ttm_mem_available;
1673
1674 spin_lock(&kfd_mem_limit.mem_limit_lock);
1675 if (adev->apu_prefer_gtt && !adev->gmc.is_app_apu)
1676 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1677 - adev->kfd.vram_used_aligned[xcp_id];
1678 else
1679 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1680 - adev->kfd.vram_used_aligned[xcp_id]
1681 - atomic64_read(&adev->vram_pin_size)
1682 - reserved_for_pt
1683 - reserved_for_ras;
1684
1685 if (adev->apu_prefer_gtt) {
1686 system_mem_available = no_system_mem_limit ?
1687 kfd_mem_limit.max_system_mem_limit :
1688 kfd_mem_limit.max_system_mem_limit -
1689 kfd_mem_limit.system_mem_used;
1690
1691 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1692 kfd_mem_limit.ttm_mem_used;
1693
1694 available = min3(system_mem_available, ttm_mem_available,
1695 vram_available);
1696 available = ALIGN_DOWN(available, PAGE_SIZE);
1697 } else {
1698 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1699 }
1700
1701 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1702
1703 if (available < 0)
1704 available = 0;
1705
1706 return available;
1707}
1708
1709int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1710 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1711 void *drm_priv, struct kgd_mem **mem,
1712 uint64_t *offset, uint32_t flags, bool criu_resume)
1713{
1714 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1715 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1716 enum ttm_bo_type bo_type = ttm_bo_type_device;
1717 struct sg_table *sg = NULL;
1718 uint64_t user_addr = 0;
1719 struct amdgpu_bo *bo;
1720 struct drm_gem_object *gobj = NULL;
1721 u32 domain, alloc_domain;
1722 uint64_t aligned_size;
1723 int8_t xcp_id = -1;
1724 u64 alloc_flags;
1725 int ret;
1726
1727 /*
1728 * Check on which domain to allocate BO
1729 */
1730 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1731 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1732
1733 if (adev->apu_prefer_gtt) {
1734 domain = AMDGPU_GEM_DOMAIN_GTT;
1735 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1736 alloc_flags = 0;
1737 } else {
1738 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE |
1739 AMDGPU_GEM_CREATE_VRAM_CLEARED;
1740 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1741 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1742
1743 /* For contiguous VRAM allocation */
1744 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_CONTIGUOUS)
1745 alloc_flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1746 }
1747 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1748 0 : fpriv->xcp_id;
1749 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1750 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1751 alloc_flags = 0;
1752 } else {
1753 domain = AMDGPU_GEM_DOMAIN_GTT;
1754 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1755 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1756
1757 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1758 if (!offset || !*offset)
1759 return -EINVAL;
1760 user_addr = untagged_addr(*offset);
1761 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1762 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1763 bo_type = ttm_bo_type_sg;
1764 if (size > UINT_MAX)
1765 return -EINVAL;
1766 sg = create_sg_table(*offset, size);
1767 if (!sg)
1768 return -ENOMEM;
1769 } else {
1770 return -EINVAL;
1771 }
1772 }
1773
1774 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1775 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1776 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1777 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1778 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1779 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1780
1781 *mem = kzalloc_obj(struct kgd_mem);
1782 if (!*mem) {
1783 ret = -ENOMEM;
1784 goto err;
1785 }
1786 INIT_LIST_HEAD(&(*mem)->attachments);
1787 mutex_init(&(*mem)->lock);
1788 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1789
1790 /* Workaround for AQL queue wraparound bug. Map the same
1791 * memory twice. That means we only actually allocate half
1792 * the memory.
1793 */
1794 if ((*mem)->aql_queue)
1795 size >>= 1;
1796 aligned_size = PAGE_ALIGN(size);
1797
1798 /* reject AQL queue with size < 2 */
1799 if (!aligned_size) {
1800 ret = -EINVAL;
1801 goto err_alignment_size;
1802 }
1803
1804 (*mem)->alloc_flags = flags;
1805
1806 amdgpu_sync_create(&(*mem)->sync);
1807
1808 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1809 xcp_id);
1810 if (ret) {
1811 pr_debug("Insufficient memory\n");
1812 goto err_reserve_limit;
1813 }
1814
1815 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1816 va, (*mem)->aql_queue ? size << 1 : size,
1817 domain_string(alloc_domain), xcp_id);
1818
1819 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1820 bo_type, NULL, &gobj, xcp_id + 1);
1821 if (ret) {
1822 pr_debug("Failed to create BO on domain %s. ret %d\n",
1823 domain_string(alloc_domain), ret);
1824 goto err_bo_create;
1825 }
1826 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1827 if (ret) {
1828 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1829 goto err_node_allow;
1830 }
1831 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1832 if (ret)
1833 goto err_gem_handle_create;
1834 bo = gem_to_amdgpu_bo(gobj);
1835 if (bo_type == ttm_bo_type_sg) {
1836 bo->tbo.sg = sg;
1837 bo->tbo.ttm->sg = sg;
1838 }
1839 bo->kfd_bo = *mem;
1840 (*mem)->bo = bo;
1841 if (user_addr)
1842 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1843
1844 (*mem)->va = va;
1845 (*mem)->domain = domain;
1846 (*mem)->mapped_to_gpu_memory = 0;
1847 (*mem)->process_info = avm->process_info;
1848
1849 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1850
1851 if (user_addr) {
1852 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1853 ret = init_user_pages(*mem, user_addr, criu_resume);
1854 if (ret)
1855 goto allocate_init_user_pages_failed;
1856 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1857 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1858 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1859 if (ret) {
1860 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1861 goto err_pin_bo;
1862 }
1863 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1864 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1865 } else {
1866 mutex_lock(&avm->process_info->lock);
1867 if (avm->process_info->eviction_fence &&
1868 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1869 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1870 &avm->process_info->eviction_fence->base);
1871 mutex_unlock(&avm->process_info->lock);
1872 if (ret)
1873 goto err_validate_bo;
1874 }
1875
1876 if (offset)
1877 *offset = amdgpu_bo_mmap_offset(bo);
1878
1879 return 0;
1880
1881allocate_init_user_pages_failed:
1882err_pin_bo:
1883err_validate_bo:
1884 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1885 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1886err_gem_handle_create:
1887 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1888err_node_allow:
1889 /* Don't unreserve system mem limit twice */
1890 goto err_reserve_limit;
1891err_bo_create:
1892 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1893err_reserve_limit:
1894 amdgpu_sync_free(&(*mem)->sync);
1895err_alignment_size:
1896 mutex_destroy(&(*mem)->lock);
1897 if (gobj)
1898 drm_gem_object_put(gobj);
1899 else
1900 kfree(*mem);
1901err:
1902 if (sg) {
1903 sg_free_table(sg);
1904 kfree(sg);
1905 }
1906 return ret;
1907}
1908
1909int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1910 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1911 uint64_t *size)
1912{
1913 struct amdkfd_process_info *process_info = mem->process_info;
1914 unsigned long bo_size = mem->bo->tbo.base.size;
1915 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1916 struct kfd_mem_attachment *entry, *tmp;
1917 struct bo_vm_reservation_context ctx;
1918 unsigned int mapped_to_gpu_memory;
1919 int ret;
1920 bool is_imported = false;
1921
1922 mutex_lock(&mem->lock);
1923
1924 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1925 is_imported = mem->is_imported;
1926 mutex_unlock(&mem->lock);
1927 /* lock is not needed after this, since mem is unused and will
1928 * be freed anyway
1929 */
1930
1931 if (mapped_to_gpu_memory > 0) {
1932 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1933 mem->va, bo_size);
1934 return -EBUSY;
1935 }
1936
1937 /* At this point the BO is guaranteed to be freed, so unpin the
1938 * MMIO/DOORBELL BOs that were pinned during allocation.
1939 */
1940 if (mem->alloc_flags &
1941 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1942 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1943 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1944 }
1945
1946 /* Make sure restore workers don't access the BO any more */
1947 mutex_lock(&process_info->lock);
1948 if (!list_empty(&mem->validate_list))
1949 list_del_init(&mem->validate_list);
1950 mutex_unlock(&process_info->lock);
1951
1952 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1953 if (unlikely(ret))
1954 return ret;
1955
1956 /* Cleanup user pages and MMU notifiers */
1957 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1958 amdgpu_hmm_unregister(mem->bo);
1959 amdgpu_hmm_range_free(mem->range);
1960 mem->range = NULL;
1961 }
1962
1963 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1964 process_info->eviction_fence);
1965 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1966 mem->va + bo_size * (1 + mem->aql_queue));
1967
1968 /* Remove from VM internal data structures */
1969 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1970 kfd_mem_dmaunmap_attachment(mem, entry);
1971 kfd_mem_detach(entry);
1972 }
1973
1974 ret = unreserve_bo_and_vms(&ctx, false, false);
1975
1976 /* Free the sync object */
1977 amdgpu_sync_free(&mem->sync);
1978
1979 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1980 * remap BO. We need to free it.
1981 */
1982 if (mem->bo->tbo.sg) {
1983 sg_free_table(mem->bo->tbo.sg);
1984 kfree(mem->bo->tbo.sg);
1985 }
1986
1987 /* Update the size of the BO being freed if it was allocated from
1988 * VRAM and is not imported. For APP APU VRAM allocations are done
1989 * in GTT domain
1990 */
1991 if (size) {
1992 if (!is_imported &&
1993 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
1994 *size = bo_size;
1995 else
1996 *size = 0;
1997 }
1998
1999 /* Free the BO*/
2000 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
2001 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
2002 if (mem->dmabuf) {
2003 dma_buf_put(mem->dmabuf);
2004 mem->dmabuf = NULL;
2005 }
2006 mutex_destroy(&mem->lock);
2007
2008 /* If this releases the last reference, it will end up calling
2009 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
2010 * this needs to be the last call here.
2011 */
2012 drm_gem_object_put(&mem->bo->tbo.base);
2013
2014 /*
2015 * For kgd_mem allocated in import_obj_create() via
2016 * amdgpu_amdkfd_gpuvm_import_dmabuf_fd(),
2017 * explicitly free it here.
2018 */
2019 if (!use_release_notifier)
2020 kfree(mem);
2021
2022 return ret;
2023}
2024
2025int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
2026 struct amdgpu_device *adev, struct kgd_mem *mem,
2027 void *drm_priv)
2028{
2029 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2030 int ret;
2031 struct amdgpu_bo *bo;
2032 uint32_t domain;
2033 struct kfd_mem_attachment *entry;
2034 struct bo_vm_reservation_context ctx;
2035 unsigned long bo_size;
2036 bool is_invalid_userptr = false;
2037
2038 bo = mem->bo;
2039 if (!bo) {
2040 pr_err("Invalid BO when mapping memory to GPU\n");
2041 return -EINVAL;
2042 }
2043
2044 /* Make sure restore is not running concurrently. Since we
2045 * don't map invalid userptr BOs, we rely on the next restore
2046 * worker to do the mapping
2047 */
2048 mutex_lock(&mem->process_info->lock);
2049
2050 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2051 * sure that the MMU notifier is no longer running
2052 * concurrently and the queues are actually stopped
2053 */
2054 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2055 mutex_lock(&mem->process_info->notifier_lock);
2056 is_invalid_userptr = !!mem->invalid;
2057 mutex_unlock(&mem->process_info->notifier_lock);
2058 }
2059
2060 mutex_lock(&mem->lock);
2061
2062 domain = mem->domain;
2063 bo_size = bo->tbo.base.size;
2064
2065 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2066 mem->va,
2067 mem->va + bo_size * (1 + mem->aql_queue),
2068 avm, domain_string(domain));
2069
2070 if (!kfd_mem_is_attached(avm, mem)) {
2071 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2072 if (ret)
2073 goto out;
2074 }
2075
2076 ret = reserve_bo_and_vm(mem, avm, &ctx);
2077 if (unlikely(ret))
2078 goto out;
2079
2080 /* Userptr can be marked as "not invalid", but not actually be
2081 * validated yet (still in the system domain). In that case
2082 * the queues are still stopped and we can leave mapping for
2083 * the next restore worker
2084 */
2085 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2086 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2087 is_invalid_userptr = true;
2088
2089 ret = vm_validate_pt_pd_bos(avm, NULL);
2090 if (unlikely(ret))
2091 goto out_unreserve;
2092
2093 list_for_each_entry(entry, &mem->attachments, list) {
2094 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2095 continue;
2096
2097 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2098 entry->va, entry->va + bo_size, entry);
2099
2100 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2101 is_invalid_userptr);
2102 if (ret) {
2103 pr_err("Failed to map bo to gpuvm\n");
2104 goto out_unreserve;
2105 }
2106
2107 ret = vm_update_pds(avm, ctx.sync);
2108 if (ret) {
2109 pr_err("Failed to update page directories\n");
2110 goto out_unreserve;
2111 }
2112
2113 entry->is_mapped = true;
2114 mem->mapped_to_gpu_memory++;
2115 pr_debug("\t INC mapping count %d\n",
2116 mem->mapped_to_gpu_memory);
2117 }
2118
2119 ret = unreserve_bo_and_vms(&ctx, false, false);
2120
2121 goto out;
2122
2123out_unreserve:
2124 unreserve_bo_and_vms(&ctx, false, false);
2125out:
2126 mutex_unlock(&mem->process_info->lock);
2127 mutex_unlock(&mem->lock);
2128 return ret;
2129}
2130
2131int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2132{
2133 struct kfd_mem_attachment *entry;
2134 struct amdgpu_vm *vm;
2135 int ret;
2136
2137 vm = drm_priv_to_vm(drm_priv);
2138
2139 mutex_lock(&mem->lock);
2140
2141 ret = amdgpu_bo_reserve(mem->bo, true);
2142 if (ret)
2143 goto out;
2144
2145 list_for_each_entry(entry, &mem->attachments, list) {
2146 if (entry->bo_va->base.vm != vm)
2147 continue;
2148 if (entry->bo_va->base.bo->tbo.ttm &&
2149 !entry->bo_va->base.bo->tbo.ttm->sg)
2150 continue;
2151
2152 kfd_mem_dmaunmap_attachment(mem, entry);
2153 }
2154
2155 amdgpu_bo_unreserve(mem->bo);
2156out:
2157 mutex_unlock(&mem->lock);
2158
2159 return ret;
2160}
2161
2162int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2163 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2164{
2165 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2166 unsigned long bo_size = mem->bo->tbo.base.size;
2167 struct kfd_mem_attachment *entry;
2168 struct bo_vm_reservation_context ctx;
2169 int ret;
2170
2171 mutex_lock(&mem->lock);
2172
2173 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2174 if (unlikely(ret))
2175 goto out;
2176 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2177 if (ctx.n_vms == 0) {
2178 ret = -EINVAL;
2179 goto unreserve_out;
2180 }
2181
2182 ret = vm_validate_pt_pd_bos(avm, NULL);
2183 if (unlikely(ret))
2184 goto unreserve_out;
2185
2186 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2187 mem->va,
2188 mem->va + bo_size * (1 + mem->aql_queue),
2189 avm);
2190
2191 list_for_each_entry(entry, &mem->attachments, list) {
2192 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2193 continue;
2194
2195 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2196 entry->va, entry->va + bo_size, entry);
2197
2198 ret = unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2199 if (ret)
2200 goto unreserve_out;
2201
2202 entry->is_mapped = false;
2203
2204 mem->mapped_to_gpu_memory--;
2205 pr_debug("\t DEC mapping count %d\n",
2206 mem->mapped_to_gpu_memory);
2207 }
2208
2209unreserve_out:
2210 unreserve_bo_and_vms(&ctx, false, false);
2211out:
2212 mutex_unlock(&mem->lock);
2213 return ret;
2214}
2215
2216int amdgpu_amdkfd_gpuvm_sync_memory(
2217 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2218{
2219 struct amdgpu_sync sync;
2220 int ret;
2221
2222 amdgpu_sync_create(&sync);
2223
2224 mutex_lock(&mem->lock);
2225 amdgpu_sync_clone(&mem->sync, &sync);
2226 mutex_unlock(&mem->lock);
2227
2228 ret = amdgpu_sync_wait(&sync, intr);
2229 amdgpu_sync_free(&sync);
2230 return ret;
2231}
2232
2233/**
2234 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2235 * @bo: Buffer object to be mapped
2236 * @bo_gart: Return bo reference
2237 *
2238 * Before return, bo reference count is incremented. To release the reference and unpin/
2239 * unmap the BO, call amdgpu_amdkfd_free_kernel_mem.
2240 */
2241int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart)
2242{
2243 int ret;
2244
2245 ret = amdgpu_bo_reserve(bo, true);
2246 if (ret) {
2247 pr_err("Failed to reserve bo. ret %d\n", ret);
2248 goto err_reserve_bo_failed;
2249 }
2250
2251 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2252 if (ret) {
2253 pr_err("Failed to pin bo. ret %d\n", ret);
2254 goto err_pin_bo_failed;
2255 }
2256
2257 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2258 if (ret) {
2259 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2260 goto err_map_bo_gart_failed;
2261 }
2262
2263 amdgpu_amdkfd_remove_eviction_fence(
2264 bo, bo->vm_bo->vm->process_info->eviction_fence);
2265
2266 amdgpu_bo_unreserve(bo);
2267
2268 *bo_gart = amdgpu_bo_ref(bo);
2269
2270 return 0;
2271
2272err_map_bo_gart_failed:
2273 amdgpu_bo_unpin(bo);
2274err_pin_bo_failed:
2275 amdgpu_bo_unreserve(bo);
2276err_reserve_bo_failed:
2277
2278 return ret;
2279}
2280
2281/** amdgpu_amdkfd_gpuvm_map_bo_to_kernel() - Map GTT or VRAM BO for kernel CPU access
2282 *
2283 * @mem: Buffer object to be mapped for CPU access
2284 * @kptr[out]: pointer in kernel CPU address space
2285 * @size[out]: size of the buffer
2286 * @domain[IN]: domain for pinning (AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM,
2287 * or their combination to let the driver choose). CPU visibility is
2288 * automatically enforced by amdgpu_bo_pin()
2289 *
2290 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2291 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2292 * validate_list, so the GPU mapping can be restored after a page table was
2293 * evicted.
2294 *
2295 * Return: 0 on success, error code on failure
2296 */
2297int amdgpu_amdkfd_gpuvm_map_bo_to_kernel(struct kgd_mem *mem, void **kptr,
2298 u64 *size, u32 domain)
2299{
2300 int ret;
2301 struct amdgpu_bo *bo = mem->bo;
2302
2303 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2304 pr_err("userptr can't be mapped to kernel\n");
2305 return -EINVAL;
2306 }
2307
2308 if (!(domain & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM))) {
2309 pr_debug("Invalid domain 0x%x for kernel mapping\n", domain);
2310 return -EINVAL;
2311 }
2312
2313 mutex_lock(&mem->process_info->lock);
2314
2315 ret = amdgpu_bo_reserve(bo, true);
2316 if (ret) {
2317 pr_err("Failed to reserve bo. ret %d\n", ret);
2318 goto bo_reserve_failed;
2319 }
2320
2321 ret = amdgpu_bo_pin(bo, domain);
2322 if (ret) {
2323 pr_err("Failed to pin bo. ret %d\n", ret);
2324 goto pin_failed;
2325 }
2326
2327 ret = amdgpu_bo_kmap(bo, kptr);
2328 if (ret) {
2329 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2330 goto kmap_failed;
2331 }
2332
2333 amdgpu_amdkfd_remove_eviction_fence(
2334 bo, mem->process_info->eviction_fence);
2335
2336 if (size)
2337 *size = amdgpu_bo_size(bo);
2338
2339 amdgpu_bo_unreserve(bo);
2340
2341 mutex_unlock(&mem->process_info->lock);
2342 return 0;
2343
2344kmap_failed:
2345 amdgpu_bo_unpin(bo);
2346pin_failed:
2347 amdgpu_bo_unreserve(bo);
2348bo_reserve_failed:
2349 mutex_unlock(&mem->process_info->lock);
2350
2351 return ret;
2352}
2353
2354/** amdgpu_amdkfd_gpuvm_unmap_bo_from_kernel() - Unmap GTT or VRAM BO for kernel CPU access
2355 *
2356 * @mem: Buffer object to be unmapped for CPU access
2357 *
2358 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2359 * eviction fence, so this function should only be used for cleanup before the
2360 * BO is destroyed.
2361 */
2362void amdgpu_amdkfd_gpuvm_unmap_bo_from_kernel(struct kgd_mem *mem)
2363{
2364 struct amdgpu_bo *bo = mem->bo;
2365
2366 (void)amdgpu_bo_reserve(bo, true);
2367 amdgpu_bo_kunmap(bo);
2368 amdgpu_bo_unpin(bo);
2369 amdgpu_bo_unreserve(bo);
2370}
2371
2372int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2373 struct kfd_vm_fault_info *mem)
2374{
2375 if (atomic_read_acquire(&adev->gmc.vm_fault_info_updated) == 1) {
2376 *mem = *adev->gmc.vm_fault_info;
2377 atomic_set_release(&adev->gmc.vm_fault_info_updated, 0);
2378 }
2379 return 0;
2380}
2381
2382static int import_obj_create(struct amdgpu_device *adev,
2383 struct dma_buf *dma_buf,
2384 struct drm_gem_object *obj,
2385 uint64_t va, void *drm_priv,
2386 struct kgd_mem **mem, uint64_t *size,
2387 uint64_t *mmap_offset)
2388{
2389 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2390 struct amdgpu_bo *bo;
2391 int ret;
2392
2393 bo = gem_to_amdgpu_bo(obj);
2394 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2395 AMDGPU_GEM_DOMAIN_GTT)))
2396 /* Only VRAM and GTT BOs are supported */
2397 return -EINVAL;
2398
2399 *mem = kzalloc_obj(struct kgd_mem);
2400 if (!*mem)
2401 return -ENOMEM;
2402
2403 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2404 if (ret)
2405 goto err_free_mem;
2406
2407 if (size)
2408 *size = amdgpu_bo_size(bo);
2409
2410 if (mmap_offset)
2411 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2412
2413 INIT_LIST_HEAD(&(*mem)->attachments);
2414 mutex_init(&(*mem)->lock);
2415
2416 (*mem)->alloc_flags =
2417 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2418 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2419 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2420 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2421
2422 get_dma_buf(dma_buf);
2423 (*mem)->dmabuf = dma_buf;
2424 (*mem)->bo = bo;
2425 (*mem)->va = va;
2426 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) &&
2427 !adev->apu_prefer_gtt ?
2428 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2429
2430 (*mem)->mapped_to_gpu_memory = 0;
2431 (*mem)->process_info = avm->process_info;
2432 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2433 amdgpu_sync_create(&(*mem)->sync);
2434 (*mem)->is_imported = true;
2435
2436 mutex_lock(&avm->process_info->lock);
2437 if (avm->process_info->eviction_fence &&
2438 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2439 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2440 &avm->process_info->eviction_fence->base);
2441 mutex_unlock(&avm->process_info->lock);
2442 if (ret)
2443 goto err_remove_mem;
2444
2445 return 0;
2446
2447err_remove_mem:
2448 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2449 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2450err_free_mem:
2451 kfree(*mem);
2452 return ret;
2453}
2454
2455int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2456 uint64_t va, void *drm_priv,
2457 struct kgd_mem **mem, uint64_t *size,
2458 uint64_t *mmap_offset)
2459{
2460 struct drm_gem_object *obj;
2461 uint32_t handle;
2462 int ret;
2463
2464 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2465 &handle);
2466 if (ret)
2467 return ret;
2468 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2469 if (!obj) {
2470 ret = -EINVAL;
2471 goto err_release_handle;
2472 }
2473
2474 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2475 mmap_offset);
2476 if (ret)
2477 goto err_put_obj;
2478
2479 (*mem)->gem_handle = handle;
2480
2481 return 0;
2482
2483err_put_obj:
2484 drm_gem_object_put(obj);
2485err_release_handle:
2486 drm_gem_handle_delete(adev->kfd.client.file, handle);
2487 return ret;
2488}
2489
2490int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2491 struct dma_buf **dma_buf)
2492{
2493 int ret;
2494
2495 mutex_lock(&mem->lock);
2496 ret = kfd_mem_export_dmabuf(mem);
2497 if (ret)
2498 goto out;
2499
2500 get_dma_buf(mem->dmabuf);
2501 *dma_buf = mem->dmabuf;
2502out:
2503 mutex_unlock(&mem->lock);
2504 return ret;
2505}
2506
2507/* Evict a userptr BO by stopping the queues if necessary
2508 *
2509 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2510 * cannot do any memory allocations, and cannot take any locks that
2511 * are held elsewhere while allocating memory.
2512 *
2513 * It doesn't do anything to the BO itself. The real work happens in
2514 * restore, where we get updated page addresses. This function only
2515 * ensures that GPU access to the BO is stopped.
2516 */
2517int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2518 unsigned long cur_seq, struct kgd_mem *mem)
2519{
2520 struct amdkfd_process_info *process_info = mem->process_info;
2521 int r = 0;
2522
2523 /* Do not process MMU notifications during CRIU restore until
2524 * KFD_CRIU_OP_RESUME IOCTL is received
2525 */
2526 if (READ_ONCE(process_info->block_mmu_notifications))
2527 return 0;
2528
2529 mutex_lock(&process_info->notifier_lock);
2530 mmu_interval_set_seq(mni, cur_seq);
2531
2532 mem->invalid++;
2533 if (++process_info->evicted_bos == 1) {
2534 /* First eviction, stop the queues */
2535 r = kgd2kfd_quiesce_mm(mni->mm,
2536 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2537
2538 if (r && r != -ESRCH)
2539 pr_err("Failed to quiesce KFD\n");
2540
2541 if (r != -ESRCH)
2542 queue_delayed_work(system_freezable_wq,
2543 &process_info->restore_userptr_work,
2544 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2545 }
2546 mutex_unlock(&process_info->notifier_lock);
2547
2548 return r;
2549}
2550
2551/* Update invalid userptr BOs
2552 *
2553 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2554 * userptr_inval_list and updates user pages for all BOs that have
2555 * been invalidated since their last update.
2556 */
2557static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2558 struct mm_struct *mm)
2559{
2560 struct kgd_mem *mem, *tmp_mem;
2561 struct amdgpu_bo *bo;
2562 struct ttm_operation_ctx ctx = { false, false };
2563 uint32_t invalid;
2564 int ret = 0;
2565
2566 mutex_lock(&process_info->notifier_lock);
2567
2568 /* Move all invalidated BOs to the userptr_inval_list */
2569 list_for_each_entry_safe(mem, tmp_mem,
2570 &process_info->userptr_valid_list,
2571 validate_list)
2572 if (mem->invalid)
2573 list_move_tail(&mem->validate_list,
2574 &process_info->userptr_inval_list);
2575
2576 /* Go through userptr_inval_list and update any invalid user_pages */
2577 list_for_each_entry(mem, &process_info->userptr_inval_list,
2578 validate_list) {
2579 invalid = mem->invalid;
2580 if (!invalid)
2581 /* BO hasn't been invalidated since the last
2582 * revalidation attempt. Keep its page list.
2583 */
2584 continue;
2585
2586 bo = mem->bo;
2587
2588 amdgpu_hmm_range_free(mem->range);
2589 mem->range = NULL;
2590
2591 /* BO reservations and getting user pages (hmm_range_fault)
2592 * must happen outside the notifier lock
2593 */
2594 mutex_unlock(&process_info->notifier_lock);
2595
2596 /* Move the BO to system (CPU) domain if necessary to unmap
2597 * and free the SG table
2598 */
2599 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2600 if (amdgpu_bo_reserve(bo, true))
2601 return -EAGAIN;
2602 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2603 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2604 amdgpu_bo_unreserve(bo);
2605 if (ret) {
2606 pr_err("%s: Failed to invalidate userptr BO\n",
2607 __func__);
2608 return -EAGAIN;
2609 }
2610 }
2611
2612 mem->range = amdgpu_hmm_range_alloc(NULL);
2613 if (unlikely(!mem->range))
2614 return -ENOMEM;
2615 /* Get updated user pages */
2616 ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range);
2617 if (ret) {
2618 amdgpu_hmm_range_free(mem->range);
2619 mem->range = NULL;
2620 pr_debug("Failed %d to get user pages\n", ret);
2621
2622 /* Return -EFAULT bad address error as success. It will
2623 * fail later with a VM fault if the GPU tries to access
2624 * it. Better than hanging indefinitely with stalled
2625 * user mode queues.
2626 *
2627 * Return other error -EBUSY or -ENOMEM to retry restore
2628 */
2629 if (ret != -EFAULT)
2630 return ret;
2631
2632 /* If applications unmap memory before destroying the userptr
2633 * from the KFD, trigger a segmentation fault in VM debug mode.
2634 */
2635 if (amdgpu_ttm_adev(bo->tbo.bdev)->debug_vm_userptr) {
2636 struct kfd_process *p;
2637
2638 pr_err("Pid %d unmapped memory before destroying userptr at GPU addr 0x%llx\n",
2639 pid_nr(process_info->pid), mem->va);
2640
2641 // Send GPU VM fault to user space
2642 p = kfd_lookup_process_by_pid(process_info->pid);
2643 if (p) {
2644 kfd_signal_vm_fault_event_with_userptr(p, mem->va);
2645 kfd_unref_process(p);
2646 }
2647 }
2648
2649 ret = 0;
2650 }
2651
2652 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->range);
2653
2654 mutex_lock(&process_info->notifier_lock);
2655
2656 /* Mark the BO as valid unless it was invalidated
2657 * again concurrently.
2658 */
2659 if (mem->invalid != invalid) {
2660 ret = -EAGAIN;
2661 goto unlock_out;
2662 }
2663 /* set mem valid if mem has hmm range associated */
2664 if (mem->range)
2665 mem->invalid = 0;
2666 }
2667
2668unlock_out:
2669 mutex_unlock(&process_info->notifier_lock);
2670
2671 return ret;
2672}
2673
2674/* Validate invalid userptr BOs
2675 *
2676 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2677 * with new page addresses and waits for the page table updates to complete.
2678 */
2679static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2680{
2681 struct ttm_operation_ctx ctx = { false, false };
2682 struct amdgpu_sync sync;
2683 struct drm_exec exec;
2684
2685 struct amdgpu_vm *peer_vm;
2686 struct kgd_mem *mem, *tmp_mem;
2687 struct amdgpu_bo *bo;
2688 int ret;
2689
2690 amdgpu_sync_create(&sync);
2691
2692 drm_exec_init(&exec, 0, 0);
2693 /* Reserve all BOs and page tables for validation */
2694 drm_exec_until_all_locked(&exec) {
2695 /* Reserve all the page directories */
2696 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2697 vm_list_node) {
2698 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2699 drm_exec_retry_on_contention(&exec);
2700 if (unlikely(ret))
2701 goto unreserve_out;
2702 }
2703
2704 /* Reserve the userptr_inval_list entries to resv_list */
2705 list_for_each_entry(mem, &process_info->userptr_inval_list,
2706 validate_list) {
2707 struct drm_gem_object *gobj;
2708
2709 gobj = &mem->bo->tbo.base;
2710 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2711 drm_exec_retry_on_contention(&exec);
2712 if (unlikely(ret))
2713 goto unreserve_out;
2714 }
2715 }
2716
2717 ret = process_validate_vms(process_info, NULL);
2718 if (ret)
2719 goto unreserve_out;
2720
2721 /* Validate BOs and update GPUVM page tables */
2722 list_for_each_entry_safe(mem, tmp_mem,
2723 &process_info->userptr_inval_list,
2724 validate_list) {
2725 struct kfd_mem_attachment *attachment;
2726
2727 bo = mem->bo;
2728
2729 /* Validate the BO if we got user pages */
2730 if (bo->tbo.ttm->pages[0]) {
2731 amdgpu_bo_placement_from_domain(bo, mem->domain);
2732 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2733 if (ret) {
2734 pr_err("%s: failed to validate BO\n", __func__);
2735 goto unreserve_out;
2736 }
2737 }
2738
2739 /* Update mapping. If the BO was not validated
2740 * (because we couldn't get user pages), this will
2741 * clear the page table entries, which will result in
2742 * VM faults if the GPU tries to access the invalid
2743 * memory.
2744 */
2745 list_for_each_entry(attachment, &mem->attachments, list) {
2746 if (!attachment->is_mapped)
2747 continue;
2748
2749 kfd_mem_dmaunmap_attachment(mem, attachment);
2750 ret = update_gpuvm_pte(mem, attachment, &sync);
2751 if (ret) {
2752 pr_err("%s: update PTE failed\n", __func__);
2753 /* make sure this gets validated again */
2754 mutex_lock(&process_info->notifier_lock);
2755 mem->invalid++;
2756 mutex_unlock(&process_info->notifier_lock);
2757 goto unreserve_out;
2758 }
2759 }
2760 }
2761
2762 /* Update page directories */
2763 ret = process_update_pds(process_info, &sync);
2764
2765unreserve_out:
2766 drm_exec_fini(&exec);
2767 amdgpu_sync_wait(&sync, false);
2768 amdgpu_sync_free(&sync);
2769
2770 return ret;
2771}
2772
2773/* Confirm that all user pages are valid while holding the notifier lock
2774 *
2775 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2776 */
2777static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2778{
2779 struct kgd_mem *mem, *tmp_mem;
2780 int ret = 0;
2781
2782 list_for_each_entry_safe(mem, tmp_mem,
2783 &process_info->userptr_inval_list,
2784 validate_list) {
2785 bool valid;
2786
2787 /* keep mem without hmm range at userptr_inval_list */
2788 if (!mem->range)
2789 continue;
2790
2791 /* Only check mem with hmm range associated */
2792 valid = amdgpu_hmm_range_valid(mem->range);
2793 amdgpu_hmm_range_free(mem->range);
2794
2795 mem->range = NULL;
2796 if (!valid) {
2797 WARN(!mem->invalid, "Invalid BO not marked invalid");
2798 ret = -EAGAIN;
2799 continue;
2800 }
2801
2802 if (mem->invalid) {
2803 WARN(1, "Valid BO is marked invalid");
2804 ret = -EAGAIN;
2805 continue;
2806 }
2807
2808 list_move_tail(&mem->validate_list,
2809 &process_info->userptr_valid_list);
2810 }
2811
2812 return ret;
2813}
2814
2815/* Worker callback to restore evicted userptr BOs
2816 *
2817 * Tries to update and validate all userptr BOs. If successful and no
2818 * concurrent evictions happened, the queues are restarted. Otherwise,
2819 * reschedule for another attempt later.
2820 */
2821static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2822{
2823 struct delayed_work *dwork = to_delayed_work(work);
2824 struct amdkfd_process_info *process_info =
2825 container_of(dwork, struct amdkfd_process_info,
2826 restore_userptr_work);
2827 struct task_struct *usertask;
2828 struct mm_struct *mm;
2829 uint32_t evicted_bos;
2830
2831 mutex_lock(&process_info->notifier_lock);
2832 evicted_bos = process_info->evicted_bos;
2833 mutex_unlock(&process_info->notifier_lock);
2834 if (!evicted_bos)
2835 return;
2836
2837 /* Reference task and mm in case of concurrent process termination */
2838 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2839 if (!usertask)
2840 return;
2841 mm = get_task_mm(usertask);
2842 if (!mm) {
2843 put_task_struct(usertask);
2844 return;
2845 }
2846
2847 mutex_lock(&process_info->lock);
2848
2849 if (update_invalid_user_pages(process_info, mm))
2850 goto unlock_out;
2851 /* userptr_inval_list can be empty if all evicted userptr BOs
2852 * have been freed. In that case there is nothing to validate
2853 * and we can just restart the queues.
2854 */
2855 if (!list_empty(&process_info->userptr_inval_list)) {
2856 if (validate_invalid_user_pages(process_info))
2857 goto unlock_out;
2858 }
2859 /* Final check for concurrent evicton and atomic update. If
2860 * another eviction happens after successful update, it will
2861 * be a first eviction that calls quiesce_mm. The eviction
2862 * reference counting inside KFD will handle this case.
2863 */
2864 mutex_lock(&process_info->notifier_lock);
2865 if (process_info->evicted_bos != evicted_bos)
2866 goto unlock_notifier_out;
2867
2868 if (confirm_valid_user_pages_locked(process_info)) {
2869 WARN(1, "User pages unexpectedly invalid");
2870 goto unlock_notifier_out;
2871 }
2872
2873 process_info->evicted_bos = evicted_bos = 0;
2874
2875 if (kgd2kfd_resume_mm(mm)) {
2876 pr_err("%s: Failed to resume KFD\n", __func__);
2877 /* No recovery from this failure. Probably the CP is
2878 * hanging. No point trying again.
2879 */
2880 }
2881
2882unlock_notifier_out:
2883 mutex_unlock(&process_info->notifier_lock);
2884unlock_out:
2885 mutex_unlock(&process_info->lock);
2886
2887 /* If validation failed, reschedule another attempt */
2888 if (evicted_bos) {
2889 queue_delayed_work(system_freezable_wq,
2890 &process_info->restore_userptr_work,
2891 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2892
2893 kfd_smi_event_queue_restore_rescheduled(mm);
2894 }
2895 mmput(mm);
2896 put_task_struct(usertask);
2897}
2898
2899static void replace_eviction_fence(struct dma_fence __rcu **ef,
2900 struct dma_fence *new_ef)
2901{
2902 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2903 /* protected by process_info->lock */);
2904
2905 /* If we're replacing an unsignaled eviction fence, that fence will
2906 * never be signaled, and if anyone is still waiting on that fence,
2907 * they will hang forever. This should never happen. We should only
2908 * replace the fence in restore_work that only gets scheduled after
2909 * eviction work signaled the fence.
2910 */
2911 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2912 "Replacing unsignaled eviction fence");
2913 dma_fence_put(old_ef);
2914}
2915
2916/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2917 * KFD process identified by process_info
2918 *
2919 * @process_info: amdkfd_process_info of the KFD process
2920 *
2921 * After memory eviction, restore thread calls this function. The function
2922 * should be called when the Process is still valid. BO restore involves -
2923 *
2924 * 1. Release old eviction fence and create new one
2925 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2926 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2927 * BOs that need to be reserved.
2928 * 4. Reserve all the BOs
2929 * 5. Validate of PD and PT BOs.
2930 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2931 * 7. Add fence to all PD and PT BOs.
2932 * 8. Unreserve all BOs
2933 */
2934int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2935{
2936 struct amdkfd_process_info *process_info = info;
2937 struct amdgpu_vm *peer_vm;
2938 struct kgd_mem *mem;
2939 struct list_head duplicate_save;
2940 struct amdgpu_sync sync_obj;
2941 unsigned long failed_size = 0;
2942 unsigned long total_size = 0;
2943 struct drm_exec exec;
2944 int ret;
2945
2946 INIT_LIST_HEAD(&duplicate_save);
2947
2948 mutex_lock(&process_info->lock);
2949
2950 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
2951 drm_exec_until_all_locked(&exec) {
2952 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2953 vm_list_node) {
2954 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2955 drm_exec_retry_on_contention(&exec);
2956 if (unlikely(ret)) {
2957 pr_err("Locking VM PD failed, ret: %d\n", ret);
2958 goto ttm_reserve_fail;
2959 }
2960 }
2961
2962 /* Reserve all BOs and page tables/directory. Add all BOs from
2963 * kfd_bo_list to ctx.list
2964 */
2965 list_for_each_entry(mem, &process_info->kfd_bo_list,
2966 validate_list) {
2967 struct drm_gem_object *gobj;
2968
2969 gobj = &mem->bo->tbo.base;
2970 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2971 drm_exec_retry_on_contention(&exec);
2972 if (unlikely(ret)) {
2973 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret);
2974 goto ttm_reserve_fail;
2975 }
2976 }
2977 }
2978
2979 amdgpu_sync_create(&sync_obj);
2980
2981 /* Validate BOs managed by KFD */
2982 list_for_each_entry(mem, &process_info->kfd_bo_list,
2983 validate_list) {
2984
2985 struct amdgpu_bo *bo = mem->bo;
2986 uint32_t domain = mem->domain;
2987 struct dma_resv_iter cursor;
2988 struct dma_fence *fence;
2989
2990 total_size += amdgpu_bo_size(bo);
2991
2992 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2993 if (ret) {
2994 pr_debug("Memory eviction: Validate BOs failed\n");
2995 failed_size += amdgpu_bo_size(bo);
2996 ret = amdgpu_amdkfd_bo_validate(bo,
2997 AMDGPU_GEM_DOMAIN_GTT, false);
2998 if (ret) {
2999 pr_debug("Memory eviction: Try again\n");
3000 goto validate_map_fail;
3001 }
3002 }
3003 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
3004 DMA_RESV_USAGE_KERNEL, fence) {
3005 ret = amdgpu_sync_fence(&sync_obj, fence, GFP_KERNEL);
3006 if (ret) {
3007 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
3008 goto validate_map_fail;
3009 }
3010 }
3011 }
3012
3013 if (failed_size)
3014 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
3015
3016 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
3017 * validations above would invalidate DMABuf imports again.
3018 */
3019 ret = process_validate_vms(process_info, drm_exec_ticket(&exec));
3020 if (ret) {
3021 pr_debug("Validating VMs failed, ret: %d\n", ret);
3022 goto validate_map_fail;
3023 }
3024
3025 /* Update mappings managed by KFD. */
3026 list_for_each_entry(mem, &process_info->kfd_bo_list,
3027 validate_list) {
3028 struct kfd_mem_attachment *attachment;
3029
3030 list_for_each_entry(attachment, &mem->attachments, list) {
3031 if (!attachment->is_mapped)
3032 continue;
3033
3034 kfd_mem_dmaunmap_attachment(mem, attachment);
3035 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
3036 if (ret) {
3037 pr_debug("Memory eviction: update PTE failed. Try again\n");
3038 goto validate_map_fail;
3039 }
3040 }
3041 }
3042
3043 /* Update mappings not managed by KFD */
3044 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3045 vm_list_node) {
3046 struct amdgpu_device *adev = amdgpu_ttm_adev(
3047 peer_vm->root.bo->tbo.bdev);
3048
3049 struct amdgpu_fpriv *fpriv =
3050 container_of(peer_vm, struct amdgpu_fpriv, vm);
3051
3052 ret = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
3053 if (ret) {
3054 dev_dbg(adev->dev,
3055 "Memory eviction: handle PRT moved failed, pid %8d. Try again.\n",
3056 pid_nr(process_info->pid));
3057 goto validate_map_fail;
3058 }
3059
3060 ret = amdgpu_vm_handle_moved(adev, peer_vm, drm_exec_ticket(&exec));
3061 if (ret) {
3062 dev_dbg(adev->dev,
3063 "Memory eviction: handle moved failed, pid %8d. Try again.\n",
3064 pid_nr(process_info->pid));
3065 goto validate_map_fail;
3066 }
3067 }
3068
3069 /* Update page directories */
3070 ret = process_update_pds(process_info, &sync_obj);
3071 if (ret) {
3072 pr_debug("Memory eviction: update PDs failed. Try again\n");
3073 goto validate_map_fail;
3074 }
3075
3076 /* Sync with fences on all the page tables. They implicitly depend on any
3077 * move fences from amdgpu_vm_handle_moved above.
3078 */
3079 ret = process_sync_pds_resv(process_info, &sync_obj);
3080 if (ret) {
3081 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
3082 goto validate_map_fail;
3083 }
3084
3085 /* Wait for validate and PT updates to finish */
3086 amdgpu_sync_wait(&sync_obj, false);
3087
3088 /* The old eviction fence may be unsignaled if restore happens
3089 * after a GPU reset or suspend/resume. Keep the old fence in that
3090 * case. Otherwise release the old eviction fence and create new
3091 * one, because fence only goes from unsignaled to signaled once
3092 * and cannot be reused. Use context and mm from the old fence.
3093 *
3094 * If an old eviction fence signals after this check, that's OK.
3095 * Anyone signaling an eviction fence must stop the queues first
3096 * and schedule another restore worker.
3097 */
3098 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
3099 struct amdgpu_amdkfd_fence *new_fence =
3100 amdgpu_amdkfd_fence_create(
3101 process_info->eviction_fence->base.context,
3102 process_info->eviction_fence->mm,
3103 process_info->context_id);
3104
3105 if (!new_fence) {
3106 pr_err("Failed to create eviction fence\n");
3107 ret = -ENOMEM;
3108 goto validate_map_fail;
3109 }
3110 dma_fence_put(&process_info->eviction_fence->base);
3111 process_info->eviction_fence = new_fence;
3112 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3113 } else {
3114 WARN_ONCE(rcu_access_pointer(*ef) != &process_info->eviction_fence->base,
3115 "KFD eviction fence doesn't match KGD process_info");
3116 }
3117
3118 /* Attach new eviction fence to all BOs except pinned ones */
3119 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3120 if (mem->bo->tbo.pin_count)
3121 continue;
3122
3123 dma_resv_add_fence(mem->bo->tbo.base.resv,
3124 &process_info->eviction_fence->base,
3125 DMA_RESV_USAGE_BOOKKEEP);
3126 }
3127 /* Attach eviction fence to PD / PT BOs and DMABuf imports */
3128 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3129 vm_list_node) {
3130 struct amdgpu_bo *bo = peer_vm->root.bo;
3131
3132 dma_resv_add_fence(bo->tbo.base.resv,
3133 &process_info->eviction_fence->base,
3134 DMA_RESV_USAGE_BOOKKEEP);
3135 }
3136
3137validate_map_fail:
3138 amdgpu_sync_free(&sync_obj);
3139ttm_reserve_fail:
3140 drm_exec_fini(&exec);
3141 mutex_unlock(&process_info->lock);
3142 return ret;
3143}
3144
3145int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3146{
3147 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3148 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3149 int ret;
3150
3151 if (!info || !gws)
3152 return -EINVAL;
3153
3154 *mem = kzalloc_obj(struct kgd_mem);
3155 if (!*mem)
3156 return -ENOMEM;
3157
3158 mutex_init(&(*mem)->lock);
3159 INIT_LIST_HEAD(&(*mem)->attachments);
3160 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3161 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3162 (*mem)->process_info = process_info;
3163 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3164 amdgpu_sync_create(&(*mem)->sync);
3165
3166
3167 /* Validate gws bo the first time it is added to process */
3168 mutex_lock(&(*mem)->process_info->lock);
3169 ret = amdgpu_bo_reserve(gws_bo, false);
3170 if (unlikely(ret)) {
3171 pr_err("Reserve gws bo failed %d\n", ret);
3172 goto bo_reservation_failure;
3173 }
3174
3175 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3176 if (ret) {
3177 pr_err("GWS BO validate failed %d\n", ret);
3178 goto bo_validation_failure;
3179 }
3180 /* GWS resource is shared b/t amdgpu and amdkfd
3181 * Add process eviction fence to bo so they can
3182 * evict each other.
3183 */
3184 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3185 if (ret)
3186 goto reserve_shared_fail;
3187 dma_resv_add_fence(gws_bo->tbo.base.resv,
3188 &process_info->eviction_fence->base,
3189 DMA_RESV_USAGE_BOOKKEEP);
3190 amdgpu_bo_unreserve(gws_bo);
3191 mutex_unlock(&(*mem)->process_info->lock);
3192
3193 return ret;
3194
3195reserve_shared_fail:
3196bo_validation_failure:
3197 amdgpu_bo_unreserve(gws_bo);
3198bo_reservation_failure:
3199 mutex_unlock(&(*mem)->process_info->lock);
3200 amdgpu_sync_free(&(*mem)->sync);
3201 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3202 amdgpu_bo_unref(&gws_bo);
3203 mutex_destroy(&(*mem)->lock);
3204 kfree(*mem);
3205 *mem = NULL;
3206 return ret;
3207}
3208
3209int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3210{
3211 int ret;
3212 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3213 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3214 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3215
3216 /* Remove BO from process's validate list so restore worker won't touch
3217 * it anymore
3218 */
3219 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3220
3221 ret = amdgpu_bo_reserve(gws_bo, false);
3222 if (unlikely(ret)) {
3223 pr_err("Reserve gws bo failed %d\n", ret);
3224 //TODO add BO back to validate_list?
3225 return ret;
3226 }
3227 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3228 process_info->eviction_fence);
3229 amdgpu_bo_unreserve(gws_bo);
3230 amdgpu_sync_free(&kgd_mem->sync);
3231 amdgpu_bo_unref(&gws_bo);
3232 mutex_destroy(&kgd_mem->lock);
3233 kfree(mem);
3234 return 0;
3235}
3236
3237/* Returns GPU-specific tiling mode information */
3238int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3239 struct tile_config *config)
3240{
3241 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3242 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3243 config->num_tile_configs =
3244 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3245 config->macro_tile_config_ptr =
3246 adev->gfx.config.macrotile_mode_array;
3247 config->num_macro_tile_configs =
3248 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3249
3250 /* Those values are not set from GFX9 onwards */
3251 config->num_banks = adev->gfx.config.num_banks;
3252 config->num_ranks = adev->gfx.config.num_ranks;
3253
3254 return 0;
3255}
3256
3257bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem)
3258{
3259 struct amdgpu_vm *vm = drm_priv_to_vm(drm_priv);
3260 struct kfd_mem_attachment *entry;
3261
3262 list_for_each_entry(entry, &mem->attachments, list) {
3263 if (entry->is_mapped && entry->bo_va->base.vm == vm)
3264 return true;
3265 }
3266 return false;
3267}
3268
3269#if defined(CONFIG_DEBUG_FS)
3270
3271int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3272{
3273
3274 spin_lock(&kfd_mem_limit.mem_limit_lock);
3275 seq_printf(m, "System mem used %lldM out of %lluM\n",
3276 (kfd_mem_limit.system_mem_used >> 20),
3277 (kfd_mem_limit.max_system_mem_limit >> 20));
3278 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3279 (kfd_mem_limit.ttm_mem_used >> 20),
3280 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3281 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3282
3283 return 0;
3284}
3285
3286#endif