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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <drm/display/drm_dp_helper.h>
28#include <drm/drm_crtc_helper.h>
29#include <drm/drm_edid.h>
30#include <drm/drm_modeset_helper_vtables.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "atom.h"
35#include "atombios_encoders.h"
36#include "atombios_dp.h"
37#include "amdgpu_connectors.h"
38#include "amdgpu_i2c.h"
39#include "amdgpu_display.h"
40
41#include <linux/pm_runtime.h>
42
43void amdgpu_connector_hotplug(struct drm_connector *connector)
44{
45 struct drm_device *dev = connector->dev;
46 struct amdgpu_device *adev = drm_to_adev(dev);
47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
48
49 /* bail if the connector does not have hpd pin, e.g.,
50 * VGA, TV, etc.
51 */
52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
53 return;
54
55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
56
57 /* if the connector is already off, don't turn it back on */
58 if (connector->dpms != DRM_MODE_DPMS_ON)
59 return;
60
61 /* just deal with DP (not eDP) here. */
62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
63 struct amdgpu_connector_atom_dig *dig_connector =
64 amdgpu_connector->con_priv;
65
66 /* if existing sink type was not DP no need to retrain */
67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
68 return;
69
70 /* first get sink type as it may be reset after (un)plug */
71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
72 /* don't do anything if sink is not display port, i.e.,
73 * passive dp->(dvi|hdmi) adaptor
74 */
75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
78 /* Don't start link training before we have the DPCD */
79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
80 return;
81
82 /* Turn the connector off and back on immediately, which
83 * will trigger link training
84 */
85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
87 }
88 }
89}
90
91static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
92{
93 struct drm_crtc *crtc = encoder->crtc;
94
95 if (crtc && crtc->enabled) {
96 drm_crtc_helper_set_mode(crtc, &crtc->mode,
97 crtc->x, crtc->y, crtc->primary->fb);
98 }
99}
100
101int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
102{
103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
104 struct amdgpu_connector_atom_dig *dig_connector;
105 int bpc = 8;
106 unsigned int mode_clock, max_tmds_clock;
107
108 switch (connector->connector_type) {
109 case DRM_MODE_CONNECTOR_DVII:
110 case DRM_MODE_CONNECTOR_HDMIB:
111 if (amdgpu_connector->use_digital) {
112 if (connector->display_info.is_hdmi) {
113 if (connector->display_info.bpc)
114 bpc = connector->display_info.bpc;
115 }
116 }
117 break;
118 case DRM_MODE_CONNECTOR_DVID:
119 case DRM_MODE_CONNECTOR_HDMIA:
120 if (connector->display_info.is_hdmi) {
121 if (connector->display_info.bpc)
122 bpc = connector->display_info.bpc;
123 }
124 break;
125 case DRM_MODE_CONNECTOR_DisplayPort:
126 dig_connector = amdgpu_connector->con_priv;
127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
129 connector->display_info.is_hdmi) {
130 if (connector->display_info.bpc)
131 bpc = connector->display_info.bpc;
132 }
133 break;
134 case DRM_MODE_CONNECTOR_eDP:
135 case DRM_MODE_CONNECTOR_LVDS:
136 if (connector->display_info.bpc)
137 bpc = connector->display_info.bpc;
138 else {
139 const struct drm_connector_helper_funcs *connector_funcs =
140 connector->helper_private;
141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
144
145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
146 bpc = 6;
147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
148 bpc = 8;
149 }
150 break;
151 }
152
153 if (connector->display_info.is_hdmi) {
154 /*
155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
157 * 12 bpc is always supported on hdmi deep color sinks, as this is
158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
159 */
160 if (bpc > 12) {
161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
162 connector->name, bpc);
163 bpc = 12;
164 }
165
166 /* Any defined maximum tmds clock limit we must not exceed? */
167 if (connector->display_info.max_tmds_clock > 0) {
168 /* mode_clock is clock in kHz for mode to be modeset on this connector */
169 mode_clock = amdgpu_connector->pixelclock_for_modeset;
170
171 /* Maximum allowable input clock in kHz */
172 max_tmds_clock = connector->display_info.max_tmds_clock;
173
174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
175 connector->name, mode_clock, max_tmds_clock);
176
177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
180 (mode_clock * 5/4 <= max_tmds_clock))
181 bpc = 10;
182 else
183 bpc = 8;
184
185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
186 connector->name, bpc);
187 }
188
189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
190 bpc = 8;
191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
192 connector->name, bpc);
193 }
194 } else if (bpc > 8) {
195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
197 connector->name);
198 bpc = 8;
199 }
200 }
201
202 if ((amdgpu_deep_color == 0) && (bpc > 8)) {
203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
204 connector->name);
205 bpc = 8;
206 }
207
208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
209 connector->name, connector->display_info.bpc, bpc);
210
211 return bpc;
212}
213
214static void
215amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
216 enum drm_connector_status status)
217{
218 struct drm_encoder *best_encoder;
219 struct drm_encoder *encoder;
220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
221 bool connected;
222
223 best_encoder = connector_funcs->best_encoder(connector);
224
225 drm_connector_for_each_possible_encoder(connector, encoder) {
226 if ((encoder == best_encoder) && (status == connector_status_connected))
227 connected = true;
228 else
229 connected = false;
230
231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
232 }
233}
234
235static struct drm_encoder *
236amdgpu_connector_find_encoder(struct drm_connector *connector,
237 int encoder_type)
238{
239 struct drm_encoder *encoder;
240
241 drm_connector_for_each_possible_encoder(connector, encoder) {
242 if (encoder->encoder_type == encoder_type)
243 return encoder;
244 }
245
246 return NULL;
247}
248
249static const struct drm_edid *
250amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
251{
252 return drm_edid_dup(adev->mode_info.bios_hardcoded_edid);
253}
254
255static void amdgpu_connector_get_edid(struct drm_connector *connector)
256{
257 struct drm_device *dev = connector->dev;
258 struct amdgpu_device *adev = drm_to_adev(dev);
259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
260
261 if (amdgpu_connector->edid)
262 return;
263
264 /* on hw with routers, select right port */
265 if (amdgpu_connector->router.ddc_valid)
266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
267
268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
269 ENCODER_OBJECT_ID_NONE) &&
270 amdgpu_connector->ddc_bus->has_aux) {
271 amdgpu_connector->edid = drm_edid_read_ddc(connector,
272 &amdgpu_connector->ddc_bus->aux.ddc);
273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
276
277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
279 amdgpu_connector->ddc_bus->has_aux)
280 amdgpu_connector->edid = drm_edid_read_ddc(connector,
281 &amdgpu_connector->ddc_bus->aux.ddc);
282 else if (amdgpu_connector->ddc_bus)
283 amdgpu_connector->edid = drm_edid_read_ddc(connector,
284 &amdgpu_connector->ddc_bus->adapter);
285 } else if (amdgpu_connector->ddc_bus) {
286 amdgpu_connector->edid = drm_edid_read_ddc(connector,
287 &amdgpu_connector->ddc_bus->adapter);
288 }
289
290 if (!amdgpu_connector->edid) {
291 /* some laptops provide a hardcoded edid in rom for LCDs */
292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
295 drm_edid_connector_update(connector, amdgpu_connector->edid);
296 }
297 }
298}
299
300static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
301{
302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
303 int ret;
304
305 if (amdgpu_connector->edid) {
306 drm_edid_connector_update(connector, amdgpu_connector->edid);
307 ret = drm_edid_connector_add_modes(connector);
308 return ret;
309 }
310 drm_edid_connector_update(connector, NULL);
311 return 0;
312}
313
314static struct drm_encoder *
315amdgpu_connector_best_single_encoder(struct drm_connector *connector)
316{
317 struct drm_encoder *encoder;
318
319 /* pick the first one */
320 drm_connector_for_each_possible_encoder(connector, encoder)
321 return encoder;
322
323 return NULL;
324}
325
326static void amdgpu_get_native_mode(struct drm_connector *connector)
327{
328 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
329 struct amdgpu_encoder *amdgpu_encoder;
330
331 if (encoder == NULL)
332 return;
333
334 amdgpu_encoder = to_amdgpu_encoder(encoder);
335
336 if (!list_empty(&connector->probed_modes)) {
337 struct drm_display_mode *preferred_mode =
338 list_first_entry(&connector->probed_modes,
339 struct drm_display_mode, head);
340
341 amdgpu_encoder->native_mode = *preferred_mode;
342 } else {
343 amdgpu_encoder->native_mode.clock = 0;
344 }
345}
346
347static struct drm_display_mode *
348amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
349{
350 struct drm_device *dev = encoder->dev;
351 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
352 struct drm_display_mode *mode = NULL;
353 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
354
355 if (native_mode->hdisplay != 0 &&
356 native_mode->vdisplay != 0 &&
357 native_mode->clock != 0) {
358 mode = drm_mode_duplicate(dev, native_mode);
359 if (!mode)
360 return NULL;
361
362 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
363 drm_mode_set_name(mode);
364
365 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
366 } else if (native_mode->hdisplay != 0 &&
367 native_mode->vdisplay != 0) {
368 /* mac laptops without an edid */
369 /* Note that this is not necessarily the exact panel mode,
370 * but an approximation based on the cvt formula. For these
371 * systems we should ideally read the mode info out of the
372 * registers or add a mode table, but this works and is much
373 * simpler.
374 */
375 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
376 if (!mode)
377 return NULL;
378
379 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
380 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
381 }
382 return mode;
383}
384
385static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
386 struct drm_connector *connector)
387{
388 struct drm_device *dev = encoder->dev;
389 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
390 struct drm_display_mode *mode = NULL;
391 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
392 int i;
393 int n;
394 struct mode_size {
395 char name[DRM_DISPLAY_MODE_LEN];
396 int w;
397 int h;
398 } common_modes[] = {
399 { "640x480", 640, 480},
400 { "800x600", 800, 600},
401 { "1024x768", 1024, 768},
402 { "1280x720", 1280, 720},
403 { "1280x800", 1280, 800},
404 {"1280x1024", 1280, 1024},
405 { "1440x900", 1440, 900},
406 {"1680x1050", 1680, 1050},
407 {"1600x1200", 1600, 1200},
408 {"1920x1080", 1920, 1080},
409 {"1920x1200", 1920, 1200}
410 };
411
412 n = ARRAY_SIZE(common_modes);
413
414 for (i = 0; i < n; i++) {
415 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
416 if (common_modes[i].w > 1024 ||
417 common_modes[i].h > 768)
418 continue;
419 }
420 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
421 if (common_modes[i].w > native_mode->hdisplay ||
422 common_modes[i].h > native_mode->vdisplay ||
423 (common_modes[i].w == native_mode->hdisplay &&
424 common_modes[i].h == native_mode->vdisplay))
425 continue;
426 }
427
428 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
429 if (!mode)
430 return;
431 strscpy(mode->name, common_modes[i].name, DRM_DISPLAY_MODE_LEN);
432
433 drm_mode_probed_add(connector, mode);
434 }
435}
436
437static int amdgpu_connector_set_property(struct drm_connector *connector,
438 struct drm_property *property,
439 uint64_t val)
440{
441 struct drm_device *dev = connector->dev;
442 struct amdgpu_device *adev = drm_to_adev(dev);
443 struct drm_encoder *encoder;
444 struct amdgpu_encoder *amdgpu_encoder;
445
446 if (property == adev->mode_info.coherent_mode_property) {
447 struct amdgpu_encoder_atom_dig *dig;
448 bool new_coherent_mode;
449
450 /* need to find digital encoder on connector */
451 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
452 if (!encoder)
453 return 0;
454
455 amdgpu_encoder = to_amdgpu_encoder(encoder);
456
457 if (!amdgpu_encoder->enc_priv)
458 return 0;
459
460 dig = amdgpu_encoder->enc_priv;
461 new_coherent_mode = val ? true : false;
462 if (dig->coherent_mode != new_coherent_mode) {
463 dig->coherent_mode = new_coherent_mode;
464 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
465 }
466 }
467
468 if (property == adev->mode_info.audio_property) {
469 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
470 /* need to find digital encoder on connector */
471 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
472 if (!encoder)
473 return 0;
474
475 amdgpu_encoder = to_amdgpu_encoder(encoder);
476
477 if (amdgpu_connector->audio != val) {
478 amdgpu_connector->audio = val;
479 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
480 }
481 }
482
483 if (property == adev->mode_info.dither_property) {
484 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
485 /* need to find digital encoder on connector */
486 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
487 if (!encoder)
488 return 0;
489
490 amdgpu_encoder = to_amdgpu_encoder(encoder);
491
492 if (amdgpu_connector->dither != val) {
493 amdgpu_connector->dither = val;
494 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
495 }
496 }
497
498 if (property == adev->mode_info.underscan_property) {
499 /* need to find digital encoder on connector */
500 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
501 if (!encoder)
502 return 0;
503
504 amdgpu_encoder = to_amdgpu_encoder(encoder);
505
506 if (amdgpu_encoder->underscan_type != val) {
507 amdgpu_encoder->underscan_type = val;
508 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
509 }
510 }
511
512 if (property == adev->mode_info.underscan_hborder_property) {
513 /* need to find digital encoder on connector */
514 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
515 if (!encoder)
516 return 0;
517
518 amdgpu_encoder = to_amdgpu_encoder(encoder);
519
520 if (amdgpu_encoder->underscan_hborder != val) {
521 amdgpu_encoder->underscan_hborder = val;
522 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
523 }
524 }
525
526 if (property == adev->mode_info.underscan_vborder_property) {
527 /* need to find digital encoder on connector */
528 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
529 if (!encoder)
530 return 0;
531
532 amdgpu_encoder = to_amdgpu_encoder(encoder);
533
534 if (amdgpu_encoder->underscan_vborder != val) {
535 amdgpu_encoder->underscan_vborder = val;
536 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
537 }
538 }
539
540 if (property == adev->mode_info.load_detect_property) {
541 struct amdgpu_connector *amdgpu_connector =
542 to_amdgpu_connector(connector);
543
544 if (val == 0)
545 amdgpu_connector->dac_load_detect = false;
546 else
547 amdgpu_connector->dac_load_detect = true;
548 }
549
550 if (property == dev->mode_config.scaling_mode_property) {
551 enum amdgpu_rmx_type rmx_type;
552
553 if (connector->encoder) {
554 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
555 } else {
556 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
557
558 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
559 }
560
561 switch (val) {
562 default:
563 case DRM_MODE_SCALE_NONE:
564 rmx_type = RMX_OFF;
565 break;
566 case DRM_MODE_SCALE_CENTER:
567 rmx_type = RMX_CENTER;
568 break;
569 case DRM_MODE_SCALE_ASPECT:
570 rmx_type = RMX_ASPECT;
571 break;
572 case DRM_MODE_SCALE_FULLSCREEN:
573 rmx_type = RMX_FULL;
574 break;
575 }
576
577 if (amdgpu_encoder->rmx_type == rmx_type)
578 return 0;
579
580 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
581 (amdgpu_encoder->native_mode.clock == 0))
582 return 0;
583
584 amdgpu_encoder->rmx_type = rmx_type;
585
586 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
587 }
588
589 return 0;
590}
591
592static void
593amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
594 struct drm_connector *connector)
595{
596 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
597 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
598 struct drm_display_mode *t, *mode;
599
600 /* If the EDID preferred mode doesn't match the native mode, use it */
601 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
602 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
603 if (mode->hdisplay != native_mode->hdisplay ||
604 mode->vdisplay != native_mode->vdisplay)
605 drm_mode_copy(native_mode, mode);
606 }
607 }
608
609 /* Try to get native mode details from EDID if necessary */
610 if (!native_mode->clock) {
611 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
612 if (mode->hdisplay == native_mode->hdisplay &&
613 mode->vdisplay == native_mode->vdisplay) {
614 drm_mode_copy(native_mode, mode);
615 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
616 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
617 break;
618 }
619 }
620 }
621
622 if (!native_mode->clock) {
623 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
624 amdgpu_encoder->rmx_type = RMX_OFF;
625 }
626}
627
628static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
629{
630 struct drm_encoder *encoder;
631 int ret = 0;
632 struct drm_display_mode *mode;
633
634 amdgpu_connector_get_edid(connector);
635 ret = amdgpu_connector_ddc_get_modes(connector);
636 if (ret > 0) {
637 encoder = amdgpu_connector_best_single_encoder(connector);
638 if (encoder) {
639 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
640 /* add scaled modes */
641 amdgpu_connector_add_common_modes(encoder, connector);
642 }
643 return ret;
644 }
645
646 encoder = amdgpu_connector_best_single_encoder(connector);
647 if (!encoder)
648 return 0;
649
650 /* we have no EDID modes */
651 mode = amdgpu_connector_lcd_native_mode(encoder);
652 if (mode) {
653 ret = 1;
654 drm_mode_probed_add(connector, mode);
655 /* add the width/height from vbios tables if available */
656 connector->display_info.width_mm = mode->width_mm;
657 connector->display_info.height_mm = mode->height_mm;
658 /* add scaled modes */
659 amdgpu_connector_add_common_modes(encoder, connector);
660 }
661
662 return ret;
663}
664
665static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
666 const struct drm_display_mode *mode)
667{
668 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
669
670 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
671 return MODE_PANEL;
672
673 if (encoder) {
674 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
675 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
676
677 /* AVIVO hardware supports downscaling modes larger than the panel
678 * to the panel size, but I'm not sure this is desirable.
679 */
680 if ((mode->hdisplay > native_mode->hdisplay) ||
681 (mode->vdisplay > native_mode->vdisplay))
682 return MODE_PANEL;
683
684 /* if scaling is disabled, block non-native modes */
685 if (amdgpu_encoder->rmx_type == RMX_OFF) {
686 if ((mode->hdisplay != native_mode->hdisplay) ||
687 (mode->vdisplay != native_mode->vdisplay))
688 return MODE_PANEL;
689 }
690 }
691
692 return MODE_OK;
693}
694
695static enum drm_connector_status
696amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
697{
698 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
699 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
700 enum drm_connector_status ret = connector_status_disconnected;
701 int r;
702
703 if (!drm_kms_helper_is_poll_worker()) {
704 r = pm_runtime_get_sync(connector->dev->dev);
705 if (r < 0) {
706 pm_runtime_put_autosuspend(connector->dev->dev);
707 return connector_status_disconnected;
708 }
709 }
710
711 if (encoder) {
712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
713 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
714
715 /* check if panel is valid */
716 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
717 ret = connector_status_connected;
718
719 }
720
721 /* check for edid as well */
722 amdgpu_connector_get_edid(connector);
723 if (amdgpu_connector->edid)
724 ret = connector_status_connected;
725 /* check acpi lid status ??? */
726
727 amdgpu_connector_update_scratch_regs(connector, ret);
728
729 if (!drm_kms_helper_is_poll_worker())
730 pm_runtime_put_autosuspend(connector->dev->dev);
731
732 return ret;
733}
734
735static void amdgpu_connector_unregister(struct drm_connector *connector)
736{
737 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
738
739 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
740 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
741 amdgpu_connector->ddc_bus->has_aux = false;
742 }
743}
744
745static void amdgpu_connector_destroy(struct drm_connector *connector)
746{
747 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
748
749 drm_edid_free(amdgpu_connector->edid);
750 kfree(amdgpu_connector->con_priv);
751 drm_connector_unregister(connector);
752 drm_connector_cleanup(connector);
753 kfree(connector);
754}
755
756static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
757 struct drm_property *property,
758 uint64_t value)
759{
760 struct drm_device *dev = connector->dev;
761 struct amdgpu_encoder *amdgpu_encoder;
762 enum amdgpu_rmx_type rmx_type;
763
764 DRM_DEBUG_KMS("\n");
765 if (property != dev->mode_config.scaling_mode_property)
766 return 0;
767
768 if (connector->encoder)
769 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
770 else {
771 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
772
773 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
774 }
775
776 switch (value) {
777 case DRM_MODE_SCALE_NONE:
778 rmx_type = RMX_OFF;
779 break;
780 case DRM_MODE_SCALE_CENTER:
781 rmx_type = RMX_CENTER;
782 break;
783 case DRM_MODE_SCALE_ASPECT:
784 rmx_type = RMX_ASPECT;
785 break;
786 default:
787 case DRM_MODE_SCALE_FULLSCREEN:
788 rmx_type = RMX_FULL;
789 break;
790 }
791
792 if (amdgpu_encoder->rmx_type == rmx_type)
793 return 0;
794
795 amdgpu_encoder->rmx_type = rmx_type;
796
797 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
798 return 0;
799}
800
801
802static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
803 .get_modes = amdgpu_connector_lvds_get_modes,
804 .mode_valid = amdgpu_connector_lvds_mode_valid,
805 .best_encoder = amdgpu_connector_best_single_encoder,
806};
807
808static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
809 .dpms = drm_helper_connector_dpms,
810 .detect = amdgpu_connector_lvds_detect,
811 .fill_modes = drm_helper_probe_single_connector_modes,
812 .early_unregister = amdgpu_connector_unregister,
813 .destroy = amdgpu_connector_destroy,
814 .set_property = amdgpu_connector_set_lcd_property,
815};
816
817static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
818{
819 int ret;
820
821 amdgpu_connector_get_edid(connector);
822 ret = amdgpu_connector_ddc_get_modes(connector);
823 amdgpu_get_native_mode(connector);
824
825 return ret;
826}
827
828static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
829 const struct drm_display_mode *mode)
830{
831 struct drm_device *dev = connector->dev;
832 struct amdgpu_device *adev = drm_to_adev(dev);
833
834 /* XXX check mode bandwidth */
835
836 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
837 return MODE_CLOCK_HIGH;
838
839 return MODE_OK;
840}
841
842static enum drm_connector_status
843amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
844{
845 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
846 struct drm_encoder *encoder;
847 const struct drm_encoder_helper_funcs *encoder_funcs;
848 bool dret = false;
849 enum drm_connector_status ret = connector_status_disconnected;
850 int r;
851
852 if (!drm_kms_helper_is_poll_worker()) {
853 r = pm_runtime_get_sync(connector->dev->dev);
854 if (r < 0) {
855 pm_runtime_put_autosuspend(connector->dev->dev);
856 return connector_status_disconnected;
857 }
858 }
859
860 encoder = amdgpu_connector_best_single_encoder(connector);
861 if (!encoder)
862 ret = connector_status_disconnected;
863
864 if (amdgpu_connector->ddc_bus)
865 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
866 if (dret) {
867 amdgpu_connector->detected_by_load = false;
868 drm_edid_free(amdgpu_connector->edid);
869 amdgpu_connector->edid = NULL;
870 amdgpu_connector_get_edid(connector);
871
872 if (!amdgpu_connector->edid) {
873 drm_err(connector->dev,
874 "%s: probed a monitor but no|invalid EDID\n",
875 connector->name);
876 ret = connector_status_connected;
877 } else {
878 amdgpu_connector->use_digital =
879 drm_edid_is_digital(amdgpu_connector->edid);
880
881 /* some oems have boards with separate digital and analog connectors
882 * with a shared ddc line (often vga + hdmi)
883 */
884 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
885 drm_edid_free(amdgpu_connector->edid);
886 amdgpu_connector->edid = NULL;
887 ret = connector_status_disconnected;
888 } else {
889 ret = connector_status_connected;
890 }
891 }
892 } else {
893
894 /* if we aren't forcing don't do destructive polling */
895 if (!force) {
896 /* only return the previous status if we last
897 * detected a monitor via load.
898 */
899 if (amdgpu_connector->detected_by_load)
900 ret = connector->status;
901 goto out;
902 }
903
904 if (amdgpu_connector->dac_load_detect && encoder) {
905 encoder_funcs = encoder->helper_private;
906 ret = encoder_funcs->detect(encoder, connector);
907 if (ret != connector_status_disconnected)
908 amdgpu_connector->detected_by_load = true;
909 }
910 }
911
912 amdgpu_connector_update_scratch_regs(connector, ret);
913
914out:
915 if (!drm_kms_helper_is_poll_worker())
916 pm_runtime_put_autosuspend(connector->dev->dev);
917
918 return ret;
919}
920
921static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
922 .get_modes = amdgpu_connector_vga_get_modes,
923 .mode_valid = amdgpu_connector_vga_mode_valid,
924 .best_encoder = amdgpu_connector_best_single_encoder,
925};
926
927static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
928 .dpms = drm_helper_connector_dpms,
929 .detect = amdgpu_connector_vga_detect,
930 .fill_modes = drm_helper_probe_single_connector_modes,
931 .early_unregister = amdgpu_connector_unregister,
932 .destroy = amdgpu_connector_destroy,
933 .set_property = amdgpu_connector_set_property,
934};
935
936static bool
937amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
938{
939 struct drm_device *dev = connector->dev;
940 struct amdgpu_device *adev = drm_to_adev(dev);
941 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
942 enum drm_connector_status status;
943
944 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
945 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
946 status = connector_status_connected;
947 else
948 status = connector_status_disconnected;
949 if (connector->status == status)
950 return true;
951 }
952
953 return false;
954}
955
956static void amdgpu_connector_shared_ddc(enum drm_connector_status *status,
957 struct drm_connector *connector,
958 struct amdgpu_connector *amdgpu_connector)
959{
960 struct drm_connector *list_connector;
961 struct drm_connector_list_iter iter;
962 struct amdgpu_connector *list_amdgpu_connector;
963 struct drm_device *dev = connector->dev;
964 struct amdgpu_device *adev = drm_to_adev(dev);
965
966 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) {
967 drm_connector_list_iter_begin(dev, &iter);
968 drm_for_each_connector_iter(list_connector,
969 &iter) {
970 if (connector == list_connector)
971 continue;
972 list_amdgpu_connector = to_amdgpu_connector(list_connector);
973 if (list_amdgpu_connector->shared_ddc &&
974 list_amdgpu_connector->ddc_bus->rec.i2c_id ==
975 amdgpu_connector->ddc_bus->rec.i2c_id) {
976 /* cases where both connectors are digital */
977 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
978 /* hpd is our only option in this case */
979 if (!amdgpu_display_hpd_sense(adev,
980 amdgpu_connector->hpd.hpd)) {
981 drm_edid_free(amdgpu_connector->edid);
982 amdgpu_connector->edid = NULL;
983 *status = connector_status_disconnected;
984 }
985 }
986 }
987 }
988 drm_connector_list_iter_end(&iter);
989 }
990}
991
992/*
993 * DVI is complicated
994 * Do a DDC probe, if DDC probe passes, get the full EDID so
995 * we can do analog/digital monitor detection at this point.
996 * If the monitor is an analog monitor or we got no DDC,
997 * we need to find the DAC encoder object for this connector.
998 * If we got no DDC, we do load detection on the DAC encoder object.
999 * If we got analog DDC or load detection passes on the DAC encoder
1000 * we have to check if this analog encoder is shared with anyone else (TV)
1001 * if its shared we have to set the other connector to disconnected.
1002 */
1003static enum drm_connector_status
1004amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
1005{
1006 struct drm_device *dev = connector->dev;
1007 struct amdgpu_device *adev = drm_to_adev(dev);
1008 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1009 const struct drm_encoder_helper_funcs *encoder_funcs;
1010 int r;
1011 enum drm_connector_status ret = connector_status_disconnected;
1012 bool dret = false, broken_edid = false;
1013
1014 if (!drm_kms_helper_is_poll_worker()) {
1015 r = pm_runtime_get_sync(connector->dev->dev);
1016 if (r < 0) {
1017 pm_runtime_put_autosuspend(connector->dev->dev);
1018 return connector_status_disconnected;
1019 }
1020 }
1021
1022 if (amdgpu_connector->detected_hpd_without_ddc) {
1023 force = true;
1024 amdgpu_connector->detected_hpd_without_ddc = false;
1025 }
1026
1027 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1028 ret = connector->status;
1029 goto exit;
1030 }
1031
1032 if (amdgpu_connector->ddc_bus) {
1033 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1034
1035 /* Sometimes the pins required for the DDC probe on DVI
1036 * connectors don't make contact at the same time that the ones
1037 * for HPD do. If the DDC probe fails even though we had an HPD
1038 * signal, try again later
1039 */
1040 if (!dret && !force &&
1041 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1042 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1043 amdgpu_connector->detected_hpd_without_ddc = true;
1044 schedule_delayed_work(&adev->hotplug_work,
1045 msecs_to_jiffies(1000));
1046 goto exit;
1047 }
1048 }
1049 if (dret) {
1050 amdgpu_connector->detected_by_load = false;
1051 drm_edid_free(amdgpu_connector->edid);
1052 amdgpu_connector->edid = NULL;
1053 amdgpu_connector_get_edid(connector);
1054
1055 if (!amdgpu_connector->edid) {
1056 drm_err(adev_to_drm(adev), "%s: probed a monitor but no|invalid EDID\n",
1057 connector->name);
1058 ret = connector_status_connected;
1059 broken_edid = true; /* defer use_digital to later */
1060 } else {
1061 amdgpu_connector->use_digital =
1062 drm_edid_is_digital(amdgpu_connector->edid);
1063
1064 /* some oems have boards with separate digital and analog connectors
1065 * with a shared ddc line (often vga + hdmi)
1066 */
1067 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1068 drm_edid_free(amdgpu_connector->edid);
1069 amdgpu_connector->edid = NULL;
1070 ret = connector_status_disconnected;
1071 } else {
1072 ret = connector_status_connected;
1073 }
1074
1075 /* This gets complicated. We have boards with VGA + HDMI with a
1076 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1077 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1078 * you don't really know what's connected to which port as both are digital.
1079 */
1080 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector);
1081 }
1082 }
1083
1084 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1085 goto out;
1086
1087 /* DVI-D and HDMI-A are digital only */
1088 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1089 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1090 goto out;
1091
1092 /* if we aren't forcing don't do destructive polling */
1093 if (!force) {
1094 /* only return the previous status if we last
1095 * detected a monitor via load.
1096 */
1097 if (amdgpu_connector->detected_by_load)
1098 ret = connector->status;
1099 goto out;
1100 }
1101
1102 /* find analog encoder */
1103 if (amdgpu_connector->dac_load_detect) {
1104 struct drm_encoder *encoder;
1105
1106 drm_connector_for_each_possible_encoder(connector, encoder) {
1107 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1108 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1109 continue;
1110
1111 encoder_funcs = encoder->helper_private;
1112 if (encoder_funcs->detect) {
1113 if (!broken_edid) {
1114 if (ret != connector_status_connected) {
1115 /* deal with analog monitors without DDC */
1116 ret = encoder_funcs->detect(encoder, connector);
1117 if (ret == connector_status_connected) {
1118 amdgpu_connector->use_digital = false;
1119 }
1120 if (ret != connector_status_disconnected)
1121 amdgpu_connector->detected_by_load = true;
1122 }
1123 } else {
1124 enum drm_connector_status lret;
1125 /* assume digital unless load detected otherwise */
1126 amdgpu_connector->use_digital = true;
1127 lret = encoder_funcs->detect(encoder, connector);
1128 DRM_DEBUG_KMS("load_detect %x returned: %x\n",
1129 encoder->encoder_type, lret);
1130 if (lret == connector_status_connected)
1131 amdgpu_connector->use_digital = false;
1132 }
1133 break;
1134 }
1135 }
1136 }
1137
1138out:
1139 /* updated in get modes as well since we need to know if it's analog or digital */
1140 amdgpu_connector_update_scratch_regs(connector, ret);
1141
1142exit:
1143 if (!drm_kms_helper_is_poll_worker())
1144 pm_runtime_put_autosuspend(connector->dev->dev);
1145
1146 return ret;
1147}
1148
1149/* okay need to be smart in here about which encoder to pick */
1150static struct drm_encoder *
1151amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1152{
1153 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1154 struct drm_encoder *encoder;
1155
1156 drm_connector_for_each_possible_encoder(connector, encoder) {
1157 if (amdgpu_connector->use_digital == true) {
1158 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1159 return encoder;
1160 } else {
1161 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1162 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1163 return encoder;
1164 }
1165 }
1166
1167 /* see if we have a default encoder TODO */
1168
1169 /* then check use digitial */
1170 /* pick the first one */
1171 drm_connector_for_each_possible_encoder(connector, encoder)
1172 return encoder;
1173
1174 return NULL;
1175}
1176
1177static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1178{
1179 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1180
1181 if (connector->force == DRM_FORCE_ON)
1182 amdgpu_connector->use_digital = false;
1183 if (connector->force == DRM_FORCE_ON_DIGITAL)
1184 amdgpu_connector->use_digital = true;
1185}
1186
1187/**
1188 * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock
1189 * @adev: pointer to amdgpu_device
1190 *
1191 * Return: maximum supported HDMI (TMDS) pixel clock in KHz.
1192 */
1193static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev)
1194{
1195 if (adev->asic_type >= CHIP_POLARIS10)
1196 return 600000;
1197 else if (adev->asic_type >= CHIP_TONGA)
1198 return 300000;
1199 else
1200 return 297000;
1201}
1202
1203/**
1204 * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors
1205 * @connector: DRM connector to validate the mode on
1206 * @mode: display mode to validate
1207 *
1208 * Validate the given display mode on DVI and HDMI connectors, including
1209 * analog signals on DVI-I.
1210 *
1211 * Return: drm_mode_status indicating whether the mode is valid.
1212 */
1213static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1214 const struct drm_display_mode *mode)
1215{
1216 struct drm_device *dev = connector->dev;
1217 struct amdgpu_device *adev = drm_to_adev(dev);
1218 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1219 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev);
1220 const int max_dvi_single_link_pixel_clock = 165000;
1221 int max_digital_pixel_clock_khz;
1222
1223 /* XXX check mode bandwidth */
1224
1225 if (amdgpu_connector->use_digital) {
1226 switch (amdgpu_connector->connector_object_id) {
1227 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:
1228 max_digital_pixel_clock_khz = max_hdmi_pixel_clock;
1229 break;
1230 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:
1231 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:
1232 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock;
1233 break;
1234 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:
1235 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:
1236 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B:
1237 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2;
1238 break;
1239 default:
1240 return MODE_BAD;
1241 }
1242
1243 /* When the display EDID claims that it's an HDMI display,
1244 * we use the HDMI encoder mode of the display HW,
1245 * so we should verify against the max HDMI clock here.
1246 */
1247 if (connector->display_info.is_hdmi)
1248 max_digital_pixel_clock_khz = max_hdmi_pixel_clock;
1249
1250 if (mode->clock > max_digital_pixel_clock_khz)
1251 return MODE_CLOCK_HIGH;
1252 }
1253
1254 /* check against the max pixel clock */
1255 if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1256 return MODE_CLOCK_HIGH;
1257
1258 return MODE_OK;
1259}
1260
1261static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1262 .get_modes = amdgpu_connector_vga_get_modes,
1263 .mode_valid = amdgpu_connector_dvi_mode_valid,
1264 .best_encoder = amdgpu_connector_dvi_encoder,
1265};
1266
1267static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1268 .dpms = drm_helper_connector_dpms,
1269 .detect = amdgpu_connector_dvi_detect,
1270 .fill_modes = drm_helper_probe_single_connector_modes,
1271 .set_property = amdgpu_connector_set_property,
1272 .early_unregister = amdgpu_connector_unregister,
1273 .destroy = amdgpu_connector_destroy,
1274 .force = amdgpu_connector_dvi_force,
1275};
1276
1277static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1278{
1279 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1280 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1281 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1282 int ret;
1283
1284 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1285 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1286 struct drm_display_mode *mode;
1287
1288 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1289 if (!amdgpu_dig_connector->edp_on)
1290 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1291 ATOM_TRANSMITTER_ACTION_POWER_ON);
1292 amdgpu_connector_get_edid(connector);
1293 ret = amdgpu_connector_ddc_get_modes(connector);
1294 if (!amdgpu_dig_connector->edp_on)
1295 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1296 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1297 } else {
1298 /* need to setup ddc on the bridge */
1299 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1300 ENCODER_OBJECT_ID_NONE) {
1301 if (encoder)
1302 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1303 }
1304 amdgpu_connector_get_edid(connector);
1305 ret = amdgpu_connector_ddc_get_modes(connector);
1306 }
1307
1308 if (ret > 0) {
1309 if (encoder) {
1310 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1311 /* add scaled modes */
1312 amdgpu_connector_add_common_modes(encoder, connector);
1313 }
1314 return ret;
1315 }
1316
1317 if (!encoder)
1318 return 0;
1319
1320 /* we have no EDID modes */
1321 mode = amdgpu_connector_lcd_native_mode(encoder);
1322 if (mode) {
1323 ret = 1;
1324 drm_mode_probed_add(connector, mode);
1325 /* add the width/height from vbios tables if available */
1326 connector->display_info.width_mm = mode->width_mm;
1327 connector->display_info.height_mm = mode->height_mm;
1328 /* add scaled modes */
1329 amdgpu_connector_add_common_modes(encoder, connector);
1330 }
1331 } else {
1332 /* need to setup ddc on the bridge */
1333 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1334 ENCODER_OBJECT_ID_NONE) {
1335 if (encoder)
1336 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1337 }
1338 amdgpu_connector_get_edid(connector);
1339 ret = amdgpu_connector_ddc_get_modes(connector);
1340
1341 amdgpu_get_native_mode(connector);
1342 }
1343
1344 return ret;
1345}
1346
1347u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1348{
1349 struct drm_encoder *encoder;
1350 struct amdgpu_encoder *amdgpu_encoder;
1351
1352 drm_connector_for_each_possible_encoder(connector, encoder) {
1353 amdgpu_encoder = to_amdgpu_encoder(encoder);
1354
1355 switch (amdgpu_encoder->encoder_id) {
1356 case ENCODER_OBJECT_ID_TRAVIS:
1357 case ENCODER_OBJECT_ID_NUTMEG:
1358 return amdgpu_encoder->encoder_id;
1359 default:
1360 break;
1361 }
1362 }
1363
1364 return ENCODER_OBJECT_ID_NONE;
1365}
1366
1367static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1368{
1369 struct drm_encoder *encoder;
1370 struct amdgpu_encoder *amdgpu_encoder;
1371 bool found = false;
1372
1373 drm_connector_for_each_possible_encoder(connector, encoder) {
1374 amdgpu_encoder = to_amdgpu_encoder(encoder);
1375 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1376 found = true;
1377 }
1378
1379 return found;
1380}
1381
1382bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1383{
1384 struct drm_device *dev = connector->dev;
1385 struct amdgpu_device *adev = drm_to_adev(dev);
1386
1387 if ((adev->clock.default_dispclk >= 53900) &&
1388 amdgpu_connector_encoder_is_hbr2(connector)) {
1389 return true;
1390 }
1391
1392 return false;
1393}
1394
1395static enum drm_connector_status
1396amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1397{
1398 struct drm_device *dev = connector->dev;
1399 struct amdgpu_device *adev = drm_to_adev(dev);
1400 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1401 enum drm_connector_status ret = connector_status_disconnected;
1402 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1403 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1404 int r;
1405
1406 if (!drm_kms_helper_is_poll_worker()) {
1407 r = pm_runtime_get_sync(connector->dev->dev);
1408 if (r < 0) {
1409 pm_runtime_put_autosuspend(connector->dev->dev);
1410 return connector_status_disconnected;
1411 }
1412 }
1413
1414 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1415 ret = connector->status;
1416 goto out;
1417 }
1418
1419 drm_edid_free(amdgpu_connector->edid);
1420 amdgpu_connector->edid = NULL;
1421
1422 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1423 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1424 if (encoder) {
1425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1426 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1427
1428 /* check if panel is valid */
1429 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1430 ret = connector_status_connected;
1431 }
1432 /* eDP is always DP */
1433 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1434 if (!amdgpu_dig_connector->edp_on)
1435 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1436 ATOM_TRANSMITTER_ACTION_POWER_ON);
1437 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1438 ret = connector_status_connected;
1439 if (!amdgpu_dig_connector->edp_on)
1440 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1441 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1442 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1443 ENCODER_OBJECT_ID_NONE) {
1444 /* DP bridges are always DP */
1445 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1446 /* get the DPCD from the bridge */
1447 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1448
1449 if (encoder) {
1450 /* setup ddc on the bridge */
1451 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1452 /* bridge chips are always aux */
1453 /* try DDC */
1454 if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1455 ret = connector_status_connected;
1456 else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1457 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1458
1459 ret = encoder_funcs->detect(encoder, connector);
1460 }
1461 }
1462 } else {
1463 amdgpu_dig_connector->dp_sink_type =
1464 amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1465 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1466 ret = connector_status_connected;
1467 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1468 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1469 } else {
1470 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1471 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1472 ret = connector_status_connected;
1473 } else {
1474 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1475 if (amdgpu_display_ddc_probe(amdgpu_connector,
1476 false))
1477 ret = connector_status_connected;
1478 }
1479 }
1480 }
1481
1482 amdgpu_connector_update_scratch_regs(connector, ret);
1483out:
1484 if (!drm_kms_helper_is_poll_worker())
1485 pm_runtime_put_autosuspend(connector->dev->dev);
1486
1487 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1488 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1489 drm_dp_set_subconnector_property(&amdgpu_connector->base,
1490 ret,
1491 amdgpu_dig_connector->dpcd,
1492 amdgpu_dig_connector->downstream_ports);
1493 return ret;
1494}
1495
1496static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1497 const struct drm_display_mode *mode)
1498{
1499 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1500 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1501
1502 /* XXX check mode bandwidth */
1503
1504 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1505 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1506 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1507
1508 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1509 return MODE_PANEL;
1510
1511 if (encoder) {
1512 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1513 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1514
1515 /* AVIVO hardware supports downscaling modes larger than the panel
1516 * to the panel size, but I'm not sure this is desirable.
1517 */
1518 if ((mode->hdisplay > native_mode->hdisplay) ||
1519 (mode->vdisplay > native_mode->vdisplay))
1520 return MODE_PANEL;
1521
1522 /* if scaling is disabled, block non-native modes */
1523 if (amdgpu_encoder->rmx_type == RMX_OFF) {
1524 if ((mode->hdisplay != native_mode->hdisplay) ||
1525 (mode->vdisplay != native_mode->vdisplay))
1526 return MODE_PANEL;
1527 }
1528 }
1529 return MODE_OK;
1530 } else {
1531 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1532 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1533 return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1534 } else {
1535 if (connector->display_info.is_hdmi) {
1536 /* HDMI 1.3+ supports max clock of 340 Mhz */
1537 if (mode->clock > 340000)
1538 return MODE_CLOCK_HIGH;
1539 } else {
1540 if (mode->clock > 165000)
1541 return MODE_CLOCK_HIGH;
1542 }
1543 }
1544 }
1545
1546 return MODE_OK;
1547}
1548
1549static int
1550amdgpu_connector_late_register(struct drm_connector *connector)
1551{
1552 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1553 int r = 0;
1554
1555 if (amdgpu_connector->ddc_bus->has_aux) {
1556 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1557 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1558 }
1559
1560 return r;
1561}
1562
1563static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1564 .get_modes = amdgpu_connector_dp_get_modes,
1565 .mode_valid = amdgpu_connector_dp_mode_valid,
1566 .best_encoder = amdgpu_connector_dvi_encoder,
1567};
1568
1569static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1570 .dpms = drm_helper_connector_dpms,
1571 .detect = amdgpu_connector_dp_detect,
1572 .fill_modes = drm_helper_probe_single_connector_modes,
1573 .set_property = amdgpu_connector_set_property,
1574 .early_unregister = amdgpu_connector_unregister,
1575 .destroy = amdgpu_connector_destroy,
1576 .force = amdgpu_connector_dvi_force,
1577 .late_register = amdgpu_connector_late_register,
1578};
1579
1580static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1581 .dpms = drm_helper_connector_dpms,
1582 .detect = amdgpu_connector_dp_detect,
1583 .fill_modes = drm_helper_probe_single_connector_modes,
1584 .set_property = amdgpu_connector_set_lcd_property,
1585 .early_unregister = amdgpu_connector_unregister,
1586 .destroy = amdgpu_connector_destroy,
1587 .force = amdgpu_connector_dvi_force,
1588 .late_register = amdgpu_connector_late_register,
1589};
1590
1591void
1592amdgpu_connector_add(struct amdgpu_device *adev,
1593 uint32_t connector_id,
1594 uint32_t supported_device,
1595 int connector_type,
1596 struct amdgpu_i2c_bus_rec *i2c_bus,
1597 uint16_t connector_object_id,
1598 struct amdgpu_hpd *hpd,
1599 struct amdgpu_router *router)
1600{
1601 struct drm_device *dev = adev_to_drm(adev);
1602 struct drm_connector *connector;
1603 struct drm_connector_list_iter iter;
1604 struct amdgpu_connector *amdgpu_connector;
1605 struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1606 struct drm_encoder *encoder;
1607 struct amdgpu_encoder *amdgpu_encoder;
1608 struct i2c_adapter *ddc = NULL;
1609 uint32_t subpixel_order = SubPixelNone;
1610 bool shared_ddc = false;
1611 bool is_dp_bridge = false;
1612 bool has_aux = false;
1613
1614 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1615 return;
1616
1617 /* see if we already added it */
1618 drm_connector_list_iter_begin(dev, &iter);
1619 drm_for_each_connector_iter(connector, &iter) {
1620 amdgpu_connector = to_amdgpu_connector(connector);
1621 if (amdgpu_connector->connector_id == connector_id) {
1622 amdgpu_connector->devices |= supported_device;
1623 drm_connector_list_iter_end(&iter);
1624 return;
1625 }
1626 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1627 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1628 amdgpu_connector->shared_ddc = true;
1629 shared_ddc = true;
1630 }
1631 if (amdgpu_connector->router_bus && router->ddc_valid &&
1632 (amdgpu_connector->router.router_id == router->router_id)) {
1633 amdgpu_connector->shared_ddc = false;
1634 shared_ddc = false;
1635 }
1636 }
1637 }
1638 drm_connector_list_iter_end(&iter);
1639
1640 /* check if it's a dp bridge */
1641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1642 amdgpu_encoder = to_amdgpu_encoder(encoder);
1643 if (amdgpu_encoder->devices & supported_device) {
1644 switch (amdgpu_encoder->encoder_id) {
1645 case ENCODER_OBJECT_ID_TRAVIS:
1646 case ENCODER_OBJECT_ID_NUTMEG:
1647 is_dp_bridge = true;
1648 break;
1649 default:
1650 break;
1651 }
1652 }
1653 }
1654
1655 amdgpu_connector = kzalloc_obj(struct amdgpu_connector);
1656 if (!amdgpu_connector)
1657 return;
1658
1659 connector = &amdgpu_connector->base;
1660
1661 amdgpu_connector->connector_id = connector_id;
1662 amdgpu_connector->devices = supported_device;
1663 amdgpu_connector->shared_ddc = shared_ddc;
1664 amdgpu_connector->connector_object_id = connector_object_id;
1665 amdgpu_connector->hpd = *hpd;
1666
1667 amdgpu_connector->router = *router;
1668 if (router->ddc_valid || router->cd_valid) {
1669 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1670 if (!amdgpu_connector->router_bus)
1671 drm_err(adev_to_drm(adev),
1672 "Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1673 }
1674
1675 if (is_dp_bridge) {
1676 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig);
1677 if (!amdgpu_dig_connector)
1678 goto failed;
1679 amdgpu_connector->con_priv = amdgpu_dig_connector;
1680 if (i2c_bus->valid) {
1681 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1682 if (amdgpu_connector->ddc_bus) {
1683 has_aux = true;
1684 ddc = &amdgpu_connector->ddc_bus->adapter;
1685 } else {
1686 drm_err(adev_to_drm(adev),
1687 "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1688 }
1689 }
1690 switch (connector_type) {
1691 case DRM_MODE_CONNECTOR_VGA:
1692 case DRM_MODE_CONNECTOR_DVIA:
1693 default:
1694 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1695 &amdgpu_connector_dp_funcs,
1696 connector_type,
1697 ddc);
1698 drm_connector_helper_add(&amdgpu_connector->base,
1699 &amdgpu_connector_dp_helper_funcs);
1700 connector->interlace_allowed = true;
1701 connector->doublescan_allowed = true;
1702 amdgpu_connector->dac_load_detect = true;
1703 drm_object_attach_property(&amdgpu_connector->base.base,
1704 adev->mode_info.load_detect_property,
1705 1);
1706 drm_object_attach_property(&amdgpu_connector->base.base,
1707 dev->mode_config.scaling_mode_property,
1708 DRM_MODE_SCALE_NONE);
1709 break;
1710 case DRM_MODE_CONNECTOR_DVII:
1711 case DRM_MODE_CONNECTOR_DVID:
1712 case DRM_MODE_CONNECTOR_HDMIA:
1713 case DRM_MODE_CONNECTOR_HDMIB:
1714 case DRM_MODE_CONNECTOR_DisplayPort:
1715 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1716 &amdgpu_connector_dp_funcs,
1717 connector_type,
1718 ddc);
1719 drm_connector_helper_add(&amdgpu_connector->base,
1720 &amdgpu_connector_dp_helper_funcs);
1721 drm_object_attach_property(&amdgpu_connector->base.base,
1722 adev->mode_info.underscan_property,
1723 UNDERSCAN_OFF);
1724 drm_object_attach_property(&amdgpu_connector->base.base,
1725 adev->mode_info.underscan_hborder_property,
1726 0);
1727 drm_object_attach_property(&amdgpu_connector->base.base,
1728 adev->mode_info.underscan_vborder_property,
1729 0);
1730
1731 drm_object_attach_property(&amdgpu_connector->base.base,
1732 dev->mode_config.scaling_mode_property,
1733 DRM_MODE_SCALE_NONE);
1734
1735 drm_object_attach_property(&amdgpu_connector->base.base,
1736 adev->mode_info.dither_property,
1737 AMDGPU_FMT_DITHER_DISABLE);
1738
1739 if (amdgpu_audio != 0) {
1740 drm_object_attach_property(&amdgpu_connector->base.base,
1741 adev->mode_info.audio_property,
1742 AMDGPU_AUDIO_AUTO);
1743 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1744 }
1745
1746 subpixel_order = SubPixelHorizontalRGB;
1747 connector->interlace_allowed = true;
1748 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1749 connector->doublescan_allowed = true;
1750 else
1751 connector->doublescan_allowed = false;
1752 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1753 amdgpu_connector->dac_load_detect = true;
1754 drm_object_attach_property(&amdgpu_connector->base.base,
1755 adev->mode_info.load_detect_property,
1756 1);
1757 }
1758 break;
1759 case DRM_MODE_CONNECTOR_LVDS:
1760 case DRM_MODE_CONNECTOR_eDP:
1761 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1762 &amdgpu_connector_edp_funcs,
1763 connector_type,
1764 ddc);
1765 drm_connector_helper_add(&amdgpu_connector->base,
1766 &amdgpu_connector_dp_helper_funcs);
1767 drm_object_attach_property(&amdgpu_connector->base.base,
1768 dev->mode_config.scaling_mode_property,
1769 DRM_MODE_SCALE_FULLSCREEN);
1770 subpixel_order = SubPixelHorizontalRGB;
1771 connector->interlace_allowed = false;
1772 connector->doublescan_allowed = false;
1773 break;
1774 }
1775 } else {
1776 switch (connector_type) {
1777 case DRM_MODE_CONNECTOR_VGA:
1778 if (i2c_bus->valid) {
1779 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1780 if (!amdgpu_connector->ddc_bus)
1781 drm_err(adev_to_drm(adev),
1782 "VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1783 else
1784 ddc = &amdgpu_connector->ddc_bus->adapter;
1785 }
1786 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1787 &amdgpu_connector_vga_funcs,
1788 connector_type,
1789 ddc);
1790 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1791 amdgpu_connector->dac_load_detect = true;
1792 drm_object_attach_property(&amdgpu_connector->base.base,
1793 adev->mode_info.load_detect_property,
1794 1);
1795 drm_object_attach_property(&amdgpu_connector->base.base,
1796 dev->mode_config.scaling_mode_property,
1797 DRM_MODE_SCALE_NONE);
1798 /* no HPD on analog connectors */
1799 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1800 connector->interlace_allowed = true;
1801 connector->doublescan_allowed = true;
1802 break;
1803 case DRM_MODE_CONNECTOR_DVIA:
1804 if (i2c_bus->valid) {
1805 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1806 if (!amdgpu_connector->ddc_bus)
1807 drm_err(adev_to_drm(adev),
1808 "DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1809 else
1810 ddc = &amdgpu_connector->ddc_bus->adapter;
1811 }
1812 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1813 &amdgpu_connector_vga_funcs,
1814 connector_type,
1815 ddc);
1816 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1817 amdgpu_connector->dac_load_detect = true;
1818 drm_object_attach_property(&amdgpu_connector->base.base,
1819 adev->mode_info.load_detect_property,
1820 1);
1821 drm_object_attach_property(&amdgpu_connector->base.base,
1822 dev->mode_config.scaling_mode_property,
1823 DRM_MODE_SCALE_NONE);
1824 /* no HPD on analog connectors */
1825 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1826 connector->interlace_allowed = true;
1827 connector->doublescan_allowed = true;
1828 break;
1829 case DRM_MODE_CONNECTOR_DVII:
1830 case DRM_MODE_CONNECTOR_DVID:
1831 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig);
1832 if (!amdgpu_dig_connector)
1833 goto failed;
1834 amdgpu_connector->con_priv = amdgpu_dig_connector;
1835 if (i2c_bus->valid) {
1836 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1837 if (!amdgpu_connector->ddc_bus)
1838 drm_err(adev_to_drm(adev),
1839 "DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1840 else
1841 ddc = &amdgpu_connector->ddc_bus->adapter;
1842 }
1843 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1844 &amdgpu_connector_dvi_funcs,
1845 connector_type,
1846 ddc);
1847 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1848 subpixel_order = SubPixelHorizontalRGB;
1849 drm_object_attach_property(&amdgpu_connector->base.base,
1850 adev->mode_info.coherent_mode_property,
1851 1);
1852 drm_object_attach_property(&amdgpu_connector->base.base,
1853 adev->mode_info.underscan_property,
1854 UNDERSCAN_OFF);
1855 drm_object_attach_property(&amdgpu_connector->base.base,
1856 adev->mode_info.underscan_hborder_property,
1857 0);
1858 drm_object_attach_property(&amdgpu_connector->base.base,
1859 adev->mode_info.underscan_vborder_property,
1860 0);
1861 drm_object_attach_property(&amdgpu_connector->base.base,
1862 dev->mode_config.scaling_mode_property,
1863 DRM_MODE_SCALE_NONE);
1864
1865 if (amdgpu_audio != 0) {
1866 drm_object_attach_property(&amdgpu_connector->base.base,
1867 adev->mode_info.audio_property,
1868 AMDGPU_AUDIO_AUTO);
1869 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1870 }
1871 drm_object_attach_property(&amdgpu_connector->base.base,
1872 adev->mode_info.dither_property,
1873 AMDGPU_FMT_DITHER_DISABLE);
1874 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1875 amdgpu_connector->dac_load_detect = true;
1876 drm_object_attach_property(&amdgpu_connector->base.base,
1877 adev->mode_info.load_detect_property,
1878 1);
1879 }
1880 connector->interlace_allowed = true;
1881 if (connector_type == DRM_MODE_CONNECTOR_DVII)
1882 connector->doublescan_allowed = true;
1883 else
1884 connector->doublescan_allowed = false;
1885 break;
1886 case DRM_MODE_CONNECTOR_HDMIA:
1887 case DRM_MODE_CONNECTOR_HDMIB:
1888 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig);
1889 if (!amdgpu_dig_connector)
1890 goto failed;
1891 amdgpu_connector->con_priv = amdgpu_dig_connector;
1892 if (i2c_bus->valid) {
1893 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1894 if (!amdgpu_connector->ddc_bus)
1895 drm_err(adev_to_drm(adev),
1896 "HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1897 else
1898 ddc = &amdgpu_connector->ddc_bus->adapter;
1899 }
1900 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1901 &amdgpu_connector_dvi_funcs,
1902 connector_type,
1903 ddc);
1904 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1905 drm_object_attach_property(&amdgpu_connector->base.base,
1906 adev->mode_info.coherent_mode_property,
1907 1);
1908 drm_object_attach_property(&amdgpu_connector->base.base,
1909 adev->mode_info.underscan_property,
1910 UNDERSCAN_OFF);
1911 drm_object_attach_property(&amdgpu_connector->base.base,
1912 adev->mode_info.underscan_hborder_property,
1913 0);
1914 drm_object_attach_property(&amdgpu_connector->base.base,
1915 adev->mode_info.underscan_vborder_property,
1916 0);
1917 drm_object_attach_property(&amdgpu_connector->base.base,
1918 dev->mode_config.scaling_mode_property,
1919 DRM_MODE_SCALE_NONE);
1920 if (amdgpu_audio != 0) {
1921 drm_object_attach_property(&amdgpu_connector->base.base,
1922 adev->mode_info.audio_property,
1923 AMDGPU_AUDIO_AUTO);
1924 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1925 }
1926 drm_object_attach_property(&amdgpu_connector->base.base,
1927 adev->mode_info.dither_property,
1928 AMDGPU_FMT_DITHER_DISABLE);
1929 subpixel_order = SubPixelHorizontalRGB;
1930 connector->interlace_allowed = true;
1931 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1932 connector->doublescan_allowed = true;
1933 else
1934 connector->doublescan_allowed = false;
1935 break;
1936 case DRM_MODE_CONNECTOR_DisplayPort:
1937 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig);
1938 if (!amdgpu_dig_connector)
1939 goto failed;
1940 amdgpu_connector->con_priv = amdgpu_dig_connector;
1941 if (i2c_bus->valid) {
1942 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1943 if (amdgpu_connector->ddc_bus) {
1944 has_aux = true;
1945 ddc = &amdgpu_connector->ddc_bus->adapter;
1946 } else {
1947 drm_err(adev_to_drm(adev),
1948 "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1949 }
1950 }
1951 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1952 &amdgpu_connector_dp_funcs,
1953 connector_type,
1954 ddc);
1955 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1956 subpixel_order = SubPixelHorizontalRGB;
1957 drm_object_attach_property(&amdgpu_connector->base.base,
1958 adev->mode_info.coherent_mode_property,
1959 1);
1960 drm_object_attach_property(&amdgpu_connector->base.base,
1961 adev->mode_info.underscan_property,
1962 UNDERSCAN_OFF);
1963 drm_object_attach_property(&amdgpu_connector->base.base,
1964 adev->mode_info.underscan_hborder_property,
1965 0);
1966 drm_object_attach_property(&amdgpu_connector->base.base,
1967 adev->mode_info.underscan_vborder_property,
1968 0);
1969 drm_object_attach_property(&amdgpu_connector->base.base,
1970 dev->mode_config.scaling_mode_property,
1971 DRM_MODE_SCALE_NONE);
1972 if (amdgpu_audio != 0) {
1973 drm_object_attach_property(&amdgpu_connector->base.base,
1974 adev->mode_info.audio_property,
1975 AMDGPU_AUDIO_AUTO);
1976 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1977 }
1978 drm_object_attach_property(&amdgpu_connector->base.base,
1979 adev->mode_info.dither_property,
1980 AMDGPU_FMT_DITHER_DISABLE);
1981 connector->interlace_allowed = true;
1982 /* in theory with a DP to VGA converter... */
1983 connector->doublescan_allowed = false;
1984 break;
1985 case DRM_MODE_CONNECTOR_eDP:
1986 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig);
1987 if (!amdgpu_dig_connector)
1988 goto failed;
1989 amdgpu_connector->con_priv = amdgpu_dig_connector;
1990 if (i2c_bus->valid) {
1991 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1992 if (amdgpu_connector->ddc_bus) {
1993 has_aux = true;
1994 ddc = &amdgpu_connector->ddc_bus->adapter;
1995 } else {
1996 drm_err(adev_to_drm(adev),
1997 "eDP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1998 }
1999 }
2000 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
2001 &amdgpu_connector_edp_funcs,
2002 connector_type,
2003 ddc);
2004 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
2005 drm_object_attach_property(&amdgpu_connector->base.base,
2006 dev->mode_config.scaling_mode_property,
2007 DRM_MODE_SCALE_FULLSCREEN);
2008 subpixel_order = SubPixelHorizontalRGB;
2009 connector->interlace_allowed = false;
2010 connector->doublescan_allowed = false;
2011 break;
2012 case DRM_MODE_CONNECTOR_LVDS:
2013 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig);
2014 if (!amdgpu_dig_connector)
2015 goto failed;
2016 amdgpu_connector->con_priv = amdgpu_dig_connector;
2017 if (i2c_bus->valid) {
2018 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
2019 if (!amdgpu_connector->ddc_bus)
2020 drm_err(adev_to_drm(adev),
2021 "LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2022 else
2023 ddc = &amdgpu_connector->ddc_bus->adapter;
2024 }
2025 drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
2026 &amdgpu_connector_lvds_funcs,
2027 connector_type,
2028 ddc);
2029 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
2030 drm_object_attach_property(&amdgpu_connector->base.base,
2031 dev->mode_config.scaling_mode_property,
2032 DRM_MODE_SCALE_FULLSCREEN);
2033 subpixel_order = SubPixelHorizontalRGB;
2034 connector->interlace_allowed = false;
2035 connector->doublescan_allowed = false;
2036 break;
2037 }
2038 }
2039
2040 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2041 if (i2c_bus->valid) {
2042 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2043 DRM_CONNECTOR_POLL_DISCONNECT;
2044 }
2045 } else
2046 connector->polled = DRM_CONNECTOR_POLL_HPD;
2047
2048 connector->display_info.subpixel_order = subpixel_order;
2049
2050 if (has_aux)
2051 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2052
2053 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2054 connector_type == DRM_MODE_CONNECTOR_eDP) {
2055 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
2056 }
2057
2058 return;
2059
2060failed:
2061 drm_connector_cleanup(connector);
2062 kfree(connector);
2063}