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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24#include <linux/list.h>
25#include "amdgpu.h"
26#include "amdgpu_ras_mgr.h"
27
28static const guid_t MCE = CPER_NOTIFY_MCE;
29static const guid_t CMC = CPER_NOTIFY_CMC;
30static const guid_t BOOT = BOOT_TYPE;
31
32static const guid_t CRASHDUMP = AMD_CRASHDUMP;
33static const guid_t RUNTIME = AMD_GPU_NONSTANDARD_ERROR;
34
35#define CPER_SIGNATURE_SZ (sizeof(((struct cper_hdr *)0)->signature))
36
37static void __inc_entry_length(struct cper_hdr *hdr, uint32_t size)
38{
39 hdr->record_length += size;
40}
41
42static void amdgpu_cper_get_timestamp(struct cper_timestamp *timestamp)
43{
44 struct tm tm;
45 time64_t now = ktime_get_real_seconds();
46
47 time64_to_tm(now, 0, &tm);
48 timestamp->seconds = tm.tm_sec;
49 timestamp->minutes = tm.tm_min;
50 timestamp->hours = tm.tm_hour;
51 timestamp->flag = 0;
52 timestamp->day = tm.tm_mday;
53 timestamp->month = 1 + tm.tm_mon;
54 timestamp->year = (1900 + tm.tm_year) % 100;
55 timestamp->century = (1900 + tm.tm_year) / 100;
56}
57
58void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,
59 struct cper_hdr *hdr,
60 enum amdgpu_cper_type type,
61 enum cper_error_severity sev)
62{
63 char record_id[16];
64
65 hdr->signature[0] = 'C';
66 hdr->signature[1] = 'P';
67 hdr->signature[2] = 'E';
68 hdr->signature[3] = 'R';
69 hdr->revision = CPER_HDR_REV_1;
70 hdr->signature_end = 0xFFFFFFFF;
71 hdr->error_severity = sev;
72
73 hdr->valid_bits.platform_id = 1;
74 hdr->valid_bits.timestamp = 1;
75
76 amdgpu_cper_get_timestamp(&hdr->timestamp);
77
78 snprintf(record_id, 9, "%d:%X",
79 (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ?
80 adev->smuio.funcs->get_socket_id(adev) :
81 0,
82 atomic_inc_return(&adev->cper.unique_id));
83 memcpy(hdr->record_id, record_id, 8);
84
85 snprintf(hdr->platform_id, 16, "0x%04X:0x%04X",
86 adev->pdev->vendor, adev->pdev->device);
87 /* pmfw version should be part of creator_id according to CPER spec */
88 snprintf(hdr->creator_id, 16, "%s", CPER_CREATOR_ID_AMDGPU);
89
90 switch (type) {
91 case AMDGPU_CPER_TYPE_BOOT:
92 hdr->notify_type = BOOT;
93 break;
94 case AMDGPU_CPER_TYPE_FATAL:
95 case AMDGPU_CPER_TYPE_BP_THRESHOLD:
96 hdr->notify_type = MCE;
97 break;
98 case AMDGPU_CPER_TYPE_RUNTIME:
99 if (sev == CPER_SEV_NON_FATAL_CORRECTED)
100 hdr->notify_type = CMC;
101 else
102 hdr->notify_type = MCE;
103 break;
104 default:
105 dev_err(adev->dev, "Unknown CPER Type\n");
106 break;
107 }
108
109 __inc_entry_length(hdr, HDR_LEN);
110}
111
112static int amdgpu_cper_entry_fill_section_desc(struct amdgpu_device *adev,
113 struct cper_sec_desc *section_desc,
114 bool bp_threshold,
115 bool poison,
116 enum cper_error_severity sev,
117 guid_t sec_type,
118 uint32_t section_length,
119 uint32_t section_offset)
120{
121 section_desc->revision_minor = CPER_SEC_MINOR_REV_1;
122 section_desc->revision_major = CPER_SEC_MAJOR_REV_22;
123 section_desc->sec_offset = section_offset;
124 section_desc->sec_length = section_length;
125 section_desc->valid_bits.fru_text = 1;
126 section_desc->flag_bits.primary = 1;
127 section_desc->severity = sev;
128 section_desc->sec_type = sec_type;
129
130 snprintf(section_desc->fru_text, 20, "OAM%d",
131 (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ?
132 adev->smuio.funcs->get_socket_id(adev) :
133 0);
134
135 if (bp_threshold)
136 section_desc->flag_bits.exceed_err_threshold = 1;
137 if (poison)
138 section_desc->flag_bits.latent_err = 1;
139
140 return 0;
141}
142
143int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
144 struct cper_hdr *hdr,
145 uint32_t idx,
146 struct cper_sec_crashdump_reg_data reg_data)
147{
148 struct cper_sec_desc *section_desc;
149 struct cper_sec_crashdump_fatal *section;
150
151 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));
152 section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr +
153 FATAL_SEC_OFFSET(hdr->sec_cnt, idx));
154
155 amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false,
156 CPER_SEV_FATAL_UNCORRECTED, CRASHDUMP, FATAL_SEC_LEN,
157 FATAL_SEC_OFFSET(hdr->sec_cnt, idx));
158
159 section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH;
160 section->body.reg_arr_size = sizeof(reg_data);
161 section->body.data = reg_data;
162
163 __inc_entry_length(hdr, SEC_DESC_LEN + FATAL_SEC_LEN);
164
165 return 0;
166}
167
168int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,
169 struct cper_hdr *hdr,
170 uint32_t idx,
171 enum cper_error_severity sev,
172 uint32_t *reg_dump,
173 uint32_t reg_count)
174{
175 struct cper_sec_desc *section_desc;
176 struct cper_sec_nonstd_err *section;
177 bool poison;
178
179 poison = sev != CPER_SEV_NON_FATAL_CORRECTED;
180 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));
181 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +
182 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
183
184 amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, poison,
185 sev, RUNTIME, NONSTD_SEC_LEN,
186 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
187
188 reg_count = umin(reg_count, CPER_ACA_REG_COUNT);
189
190 section->hdr.valid_bits.err_info_cnt = 1;
191 section->hdr.valid_bits.err_context_cnt = 1;
192
193 section->info.error_type = RUNTIME;
194 section->info.ms_chk_bits.err_type_valid = 1;
195 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH;
196 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump);
197
198 memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t));
199
200 __inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN);
201
202 return 0;
203}
204
205int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,
206 struct cper_hdr *hdr,
207 uint32_t idx)
208{
209 struct cper_sec_desc *section_desc;
210 struct cper_sec_nonstd_err *section;
211 uint32_t socket_id;
212
213 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));
214 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +
215 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
216
217 amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false,
218 CPER_SEV_FATAL_UNCORRECTED, RUNTIME, NONSTD_SEC_LEN,
219 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
220
221 section->hdr.valid_bits.err_info_cnt = 1;
222 section->hdr.valid_bits.err_context_cnt = 1;
223
224 section->info.error_type = RUNTIME;
225 section->info.valid_bits.ms_chk = 1;
226 section->info.ms_chk_bits.err_type_valid = 1;
227 section->info.ms_chk_bits.err_type = 1;
228 section->info.ms_chk_bits.pcc = 1;
229 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH;
230 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump);
231
232 /* Hardcoded Reg dump for bad page threshold CPER */
233 socket_id = (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ?
234 adev->smuio.funcs->get_socket_id(adev) :
235 0;
236 section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1;
237 section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0;
238 section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137;
239 section->ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000;
240 section->ctx.reg_dump[CPER_ACA_REG_ADDR_LO] = 0x0;
241 section->ctx.reg_dump[CPER_ACA_REG_ADDR_HI] = 0x0;
242 section->ctx.reg_dump[CPER_ACA_REG_MISC0_LO] = 0x0;
243 section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0;
244 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2;
245 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff;
246 section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = (socket_id / 4) & 0x01;
247 section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x096 | (((socket_id % 4) & 0x3) << 12);
248 section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0;
249 section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0;
250
251 __inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN);
252
253 return 0;
254}
255
256struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,
257 enum amdgpu_cper_type type,
258 uint16_t section_count)
259{
260 struct cper_hdr *hdr;
261 uint32_t size = 0;
262
263 size += HDR_LEN;
264 size += (SEC_DESC_LEN * section_count);
265
266 switch (type) {
267 case AMDGPU_CPER_TYPE_RUNTIME:
268 case AMDGPU_CPER_TYPE_BP_THRESHOLD:
269 size += (NONSTD_SEC_LEN * section_count);
270 break;
271 case AMDGPU_CPER_TYPE_FATAL:
272 size += (FATAL_SEC_LEN * section_count);
273 break;
274 case AMDGPU_CPER_TYPE_BOOT:
275 size += (BOOT_SEC_LEN * section_count);
276 break;
277 default:
278 dev_err(adev->dev, "Unknown CPER Type!\n");
279 return NULL;
280 }
281
282 hdr = kzalloc(size, GFP_KERNEL);
283 if (!hdr)
284 return NULL;
285
286 /* Save this early */
287 hdr->sec_cnt = section_count;
288
289 return hdr;
290}
291
292int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev)
293{
294 struct cper_hdr *bp_threshold = NULL;
295 struct amdgpu_ring *ring = &adev->cper.ring_buf;
296 int ret;
297
298 bp_threshold = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_BP_THRESHOLD, 1);
299 if (!bp_threshold) {
300 dev_err(adev->dev, "fail to alloc cper entry for bad page threshold record\n");
301 return -ENOMEM;
302 }
303
304 amdgpu_cper_entry_fill_hdr(adev, bp_threshold,
305 AMDGPU_CPER_TYPE_BP_THRESHOLD,
306 CPER_SEV_FATAL_UNCORRECTED);
307 ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0);
308 if (ret)
309 return ret;
310
311 amdgpu_cper_ring_write(ring, bp_threshold, bp_threshold->record_length);
312 kfree(bp_threshold);
313
314 return 0;
315}
316
317static bool amdgpu_cper_is_hdr(struct amdgpu_ring *ring, u64 pos)
318{
319 char signature[CPER_SIGNATURE_SZ];
320
321 if ((pos << 2) >= ring->ring_size)
322 return false;
323
324 if ((pos << 2) + CPER_SIGNATURE_SZ <= ring->ring_size) {
325 memcpy(signature, &ring->ring[pos], CPER_SIGNATURE_SZ);
326 } else {
327 u32 chunk = ring->ring_size - (pos << 2);
328
329 memcpy(signature, &ring->ring[pos], chunk);
330 memcpy(signature + chunk, ring->ring, CPER_SIGNATURE_SZ - chunk);
331 }
332
333 return !memcmp(signature, "CPER", CPER_SIGNATURE_SZ);
334}
335
336static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos)
337{
338 struct cper_hdr chdr;
339 u64 p;
340 u32 chunk, rec_len = 0;
341
342 chunk = ring->ring_size - (pos << 2);
343
344 if (amdgpu_cper_is_hdr(ring, pos)) {
345 if (chunk >= sizeof(chdr)) {
346 memcpy(&chdr, &ring->ring[pos], sizeof(chdr));
347 } else {
348 memcpy(&chdr, &ring->ring[pos], chunk);
349 memcpy((u8 *)&chdr + chunk, ring->ring, sizeof(chdr) - chunk);
350 }
351
352 rec_len = chdr.record_length;
353 goto calc;
354 }
355
356 /* ring buffer is not full, no cper data after ring->wptr */
357 if (ring->count_dw)
358 goto calc;
359
360 for (p = pos + 1; p <= ring->buf_mask; p++) {
361 if (amdgpu_cper_is_hdr(ring, p)) {
362 rec_len = (p - pos) << 2;
363 goto calc;
364 }
365 }
366
367calc:
368 if (!rec_len)
369 return chunk;
370 else
371 return umin(rec_len, chunk);
372}
373
374void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count)
375{
376 u64 pos, wptr_old, rptr, next_rptr;
377 int rec_cnt_dw = count >> 2;
378 u32 chunk, ent_sz;
379 u8 *s = (u8 *)src;
380
381 if (count >= ring->ring_size - 4) {
382 dev_err(ring->adev->dev,
383 "CPER data size(%d) is larger than ring size(%d)\n",
384 count, ring->ring_size - 4);
385
386 return;
387 }
388
389 mutex_lock(&ring->adev->cper.ring_lock);
390
391 wptr_old = ring->wptr;
392 rptr = *ring->rptr_cpu_addr & ring->ptr_mask;
393
394 while (count) {
395 ent_sz = amdgpu_cper_ring_get_ent_sz(ring, ring->wptr);
396 chunk = umin(ent_sz, count);
397
398 memcpy(&ring->ring[ring->wptr], s, chunk);
399
400 ring->wptr += (chunk >> 2);
401 ring->wptr &= ring->ptr_mask;
402 count -= chunk;
403 s += chunk;
404 }
405
406 if (ring->count_dw < rec_cnt_dw)
407 ring->count_dw = 0;
408
409 /* the buffer is overflow, adjust rptr */
410 if (((wptr_old < rptr) && (rptr <= ring->wptr)) ||
411 ((ring->wptr < wptr_old) && (wptr_old < rptr)) ||
412 ((rptr <= ring->wptr) && (ring->wptr < wptr_old))) {
413 pos = (ring->wptr + 1) & ring->ptr_mask;
414
415 do {
416 ent_sz = amdgpu_cper_ring_get_ent_sz(ring, pos);
417 next_rptr = rptr;
418 if (ent_sz >= sizeof(u32))
419 next_rptr = (rptr + (ent_sz >> 2)) & ring->ptr_mask;
420
421 if (next_rptr == rptr) {
422 /* Corrupt entry size, reset the ring to avoid an infinite loop. */
423 rptr = ring->wptr;
424 *ring->rptr_cpu_addr = rptr;
425 ring->count_dw = (ring->ring_size - 4) >> 2;
426 goto out_unlock;
427 }
428
429 rptr = next_rptr;
430 *ring->rptr_cpu_addr = rptr;
431
432 pos = rptr;
433 } while (!amdgpu_cper_is_hdr(ring, rptr));
434 }
435
436 if (ring->count_dw >= rec_cnt_dw)
437 ring->count_dw -= rec_cnt_dw;
438
439out_unlock:
440 mutex_unlock(&ring->adev->cper.ring_lock);
441}
442
443static u64 amdgpu_cper_ring_get_rptr(struct amdgpu_ring *ring)
444{
445 return *(ring->rptr_cpu_addr);
446}
447
448static u64 amdgpu_cper_ring_get_wptr(struct amdgpu_ring *ring)
449{
450 return ring->wptr;
451}
452
453static const struct amdgpu_ring_funcs cper_ring_funcs = {
454 .type = AMDGPU_RING_TYPE_CPER,
455 .align_mask = 0xff,
456 .support_64bit_ptrs = false,
457 .get_rptr = amdgpu_cper_ring_get_rptr,
458 .get_wptr = amdgpu_cper_ring_get_wptr,
459};
460
461static int amdgpu_cper_ring_init(struct amdgpu_device *adev)
462{
463 struct amdgpu_ring *ring = &(adev->cper.ring_buf);
464
465 mutex_init(&adev->cper.ring_lock);
466
467 ring->adev = NULL;
468 ring->ring_obj = NULL;
469 ring->use_doorbell = false;
470 ring->no_scheduler = true;
471 ring->funcs = &cper_ring_funcs;
472
473 sprintf(ring->name, "cper");
474 return amdgpu_ring_init(adev, ring, CPER_MAX_RING_SIZE, NULL, 0,
475 AMDGPU_RING_PRIO_DEFAULT, NULL);
476}
477
478int amdgpu_cper_init(struct amdgpu_device *adev)
479{
480 int r;
481
482 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_ras_cper_en(adev))
483 return 0;
484 else if (!amdgpu_sriov_vf(adev) && !amdgpu_uniras_enabled(adev))
485 return 0;
486
487 r = amdgpu_cper_ring_init(adev);
488 if (r) {
489 dev_err(adev->dev, "failed to initialize cper ring, r = %d\n", r);
490 return r;
491 }
492
493 mutex_init(&adev->cper.cper_lock);
494
495 adev->cper.enabled = true;
496 adev->cper.max_count = CPER_MAX_ALLOWED_COUNT;
497
498 return 0;
499}
500
501int amdgpu_cper_deferred_init(struct amdgpu_device *adev)
502{
503 int r;
504
505 if (adev->cper.enabled)
506 return 0;
507
508 r = amdgpu_cper_init(adev);
509 if (r || !adev->cper.enabled)
510 return r;
511
512#if defined(CONFIG_DEBUG_FS)
513 if (adev_to_drm(adev)->primary->debugfs_root)
514 amdgpu_debugfs_ring_init(adev, &adev->cper.ring_buf);
515#endif
516
517 return 0;
518}
519
520int amdgpu_cper_fini(struct amdgpu_device *adev)
521{
522 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_ras_cper_en(adev))
523 return 0;
524
525 adev->cper.enabled = false;
526
527 amdgpu_ring_fini(&(adev->cper.ring_buf));
528 adev->cper.count = 0;
529 adev->cper.wptr = 0;
530
531 return 0;
532}