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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_CTX_H__
24#define __AMDGPU_CTX_H__
25
26#include <linux/ktime.h>
27#include <linux/types.h>
28#include <linux/xarray.h>
29
30#include "amdgpu_ring.h"
31
32struct drm_device;
33struct drm_file;
34struct amdgpu_fpriv;
35struct amdgpu_ctx_mgr;
36
37#define AMDGPU_MAX_ENTITY_NUM 4
38
39struct amdgpu_ctx_entity {
40 uint32_t hw_ip;
41 uint64_t sequence;
42 struct drm_sched_entity entity;
43 struct dma_fence *fences[];
44};
45
46struct amdgpu_ctx {
47 struct kref refcount;
48 spinlock_t ring_lock;
49 unsigned reset_counter;
50 unsigned reset_counter_query;
51 int32_t init_priority;
52 int32_t override_priority;
53 uint32_t stable_pstate;
54 bool preamble_presented;
55 uint64_t generation;
56 unsigned long ras_counter_ce;
57 unsigned long ras_counter_ue;
58 struct amdgpu_ctx_mgr *mgr;
59 struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
60};
61
62struct amdgpu_ctx_mgr {
63 struct amdgpu_device *adev;
64 struct xarray ctx_handles;
65 atomic64_t time_spend[AMDGPU_HW_IP_NUM];
66};
67
68extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
69
70struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
71
72void amdgpu_ctx_fini(struct kref *kref);
73
74static inline void amdgpu_ctx_put(struct amdgpu_ctx *ctx)
75{
76 if (ctx)
77 kref_put(&ctx->refcount, amdgpu_ctx_fini);
78}
79
80int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
81 u32 ring, struct drm_sched_entity **entity);
82uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
83 struct drm_sched_entity *entity,
84 struct dma_fence *fence);
85struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
86 struct drm_sched_entity *entity,
87 uint64_t seq);
88bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
89void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);
90
91int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
92 struct drm_file *filp);
93
94int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
95 struct drm_sched_entity *entity);
96
97void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr,
98 struct amdgpu_device *adev);
99long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
100void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
101void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr,
102 ktime_t usage[AMDGPU_HW_IP_NUM]);
103
104#endif