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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27/**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34#include "amdgpu.h"
35#include "amdgpu_display.h"
36#include "amdgpu_gem.h"
37#include "amdgpu_dma_buf.h"
38#include "amdgpu_xgmi.h"
39#include "amdgpu_vm.h"
40#include "amdgpu_ttm.h"
41#include <drm/amdgpu_drm.h>
42#include <drm/ttm/ttm_tt.h>
43#include <linux/dma-buf.h>
44#include <linux/dma-fence-array.h>
45#include <linux/pci-p2pdma.h>
46#include <linux/pm_runtime.h>
47
48static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops;
49
50/**
51 * dma_buf_attach_adev - Helper to get adev of an attachment
52 *
53 * @attach: attachment
54 *
55 * Returns:
56 * A struct amdgpu_device * if the attaching device is an amdgpu device or
57 * partition, NULL otherwise.
58 */
59static struct amdgpu_device *dma_buf_attach_adev(struct dma_buf_attachment *attach)
60{
61 if (attach->importer_ops == &amdgpu_dma_buf_attach_ops) {
62 struct drm_gem_object *obj = attach->importer_priv;
63 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
64
65 return amdgpu_ttm_adev(bo->tbo.bdev);
66 }
67
68 return NULL;
69}
70
71/**
72 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
73 *
74 * @dmabuf: DMA-buf where we attach to
75 * @attach: attachment to add
76 *
77 * Add the attachment as user to the exported DMA-buf.
78 */
79static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
80 struct dma_buf_attachment *attach)
81{
82 struct amdgpu_device *attach_adev = dma_buf_attach_adev(attach);
83 struct drm_gem_object *obj = dmabuf->priv;
84 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
85 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
86 int r;
87
88 /*
89 * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.
90 * Such buffers cannot be safely accessed over P2P due to device-local
91 * compression metadata. Fallback to system-memory path instead.
92 * Device supports GFX12 (GC 12.x or newer)
93 * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag
94 *
95 */
96 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) &&
97 bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
98 attach->peer2peer = false;
99
100 if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &&
101 pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
102 attach->peer2peer = false;
103
104 /*
105 * Only allow P2P while the exporter is active, and keep it active
106 * until detach. With runtime PM disabled take a plain reference so
107 * the put in detach stays balanced.
108 */
109 if (attach->peer2peer) {
110 struct device *dev = adev_to_drm(adev)->dev;
111 int ret = pm_runtime_get_if_active(dev);
112
113 if (!ret)
114 attach->peer2peer = false;
115 else if (ret < 0)
116 pm_runtime_get_noresume(dev);
117 }
118
119 r = dma_resv_lock(bo->tbo.base.resv, NULL);
120 if (r)
121 goto err_pm_put;
122
123 amdgpu_vm_bo_update_shared(bo);
124
125 dma_resv_unlock(bo->tbo.base.resv);
126
127 return 0;
128
129err_pm_put:
130 if (attach->peer2peer)
131 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
132 return r;
133}
134
135/**
136 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
137 *
138 * @dmabuf: DMA-buf where we remove the attachment from
139 * @attach: the attachment to remove
140 *
141 * Drop the runtime PM reference taken in amdgpu_dma_buf_attach().
142 */
143static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
144 struct dma_buf_attachment *attach)
145{
146 struct drm_gem_object *obj = dmabuf->priv;
147 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
148 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
149
150 if (attach->peer2peer)
151 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
152}
153
154/**
155 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
156 *
157 * @attach: attachment to pin down
158 *
159 * Pin the BO which is backing the DMA-buf so that it can't move any more.
160 */
161static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
162{
163 struct dma_buf *dmabuf = attach->dmabuf;
164 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf->priv);
165 u32 domains = bo->allowed_domains;
166
167 dma_resv_assert_held(dmabuf->resv);
168
169 /* Try pinning into VRAM to allow P2P with RDMA NICs without ODP
170 * support if all attachments can do P2P. If any attachment can't do
171 * P2P just pin into GTT instead.
172 *
173 * To avoid with conflicting pinnings between GPUs and RDMA when move
174 * notifiers are disabled, only allow pinning in VRAM when move
175 * notiers are enabled.
176 */
177 list_for_each_entry(attach, &dmabuf->attachments, node)
178 if (!attach->peer2peer)
179 domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
180
181 if (domains & AMDGPU_GEM_DOMAIN_VRAM)
182 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
183
184 if (WARN_ON(!domains))
185 return -EINVAL;
186
187 return amdgpu_bo_pin(bo, domains);
188}
189
190/**
191 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
192 *
193 * @attach: attachment to unpin
194 *
195 * Unpin a previously pinned BO to make it movable again.
196 */
197static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
198{
199 struct drm_gem_object *obj = attach->dmabuf->priv;
200 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
201
202 amdgpu_bo_unpin(bo);
203}
204
205/**
206 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
207 * @attach: DMA-buf attachment
208 * @dir: DMA direction
209 *
210 * Makes sure that the shared DMA buffer can be accessed by the target device.
211 * For now, simply pins it to the GTT domain, where it should be accessible by
212 * all DMA devices.
213 *
214 * Returns:
215 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
216 * code.
217 */
218static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
219 enum dma_data_direction dir)
220{
221 struct dma_buf *dma_buf = attach->dmabuf;
222 struct drm_gem_object *obj = dma_buf->priv;
223 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
224 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
225 struct sg_table *sgt;
226 long r;
227
228 if (!bo->tbo.pin_count) {
229 /* move buffer into GTT or VRAM */
230 struct ttm_operation_ctx ctx = { false, false };
231 unsigned int domains = AMDGPU_GEM_DOMAIN_GTT;
232
233 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
234 attach->peer2peer) {
235 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
236 domains |= AMDGPU_GEM_DOMAIN_VRAM;
237 }
238 amdgpu_bo_placement_from_domain(bo, domains);
239 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
240 if (r)
241 return ERR_PTR(r);
242 }
243
244 switch (bo->tbo.resource->mem_type) {
245 case TTM_PL_TT:
246 sgt = drm_prime_pages_to_sg(obj->dev,
247 bo->tbo.ttm->pages,
248 bo->tbo.ttm->num_pages);
249 if (IS_ERR(sgt))
250 return sgt;
251
252 if (dma_map_sgtable(attach->dev, sgt, dir,
253 DMA_ATTR_SKIP_CPU_SYNC))
254 goto error_free;
255 break;
256
257 case TTM_PL_VRAM:
258 /* XGMI-accessible memory should never be DMA-mapped */
259 if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible(
260 dma_buf_attach_adev(attach), bo)))
261 return ERR_PTR(-EINVAL);
262
263 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
264 bo->tbo.base.size, attach->dev,
265 dir, &sgt);
266 if (r)
267 return ERR_PTR(r);
268 break;
269
270 case AMDGPU_PL_MMIO_REMAP:
271 r = amdgpu_ttm_mmio_remap_alloc_sgt(adev, bo->tbo.resource,
272 attach->dev, dir, &sgt);
273 if (r)
274 return ERR_PTR(r);
275 break;
276
277 default:
278 return ERR_PTR(-EINVAL);
279 }
280
281 return sgt;
282
283error_free:
284 sg_free_table(sgt);
285 kfree(sgt);
286 return ERR_PTR(-EBUSY);
287}
288
289/**
290 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
291 * @attach: DMA-buf attachment
292 * @sgt: sg_table to unmap
293 * @dir: DMA direction
294 *
295 * This is called when a shared DMA buffer no longer needs to be accessible by
296 * another device. For now, simply unpins the buffer from GTT.
297 */
298static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
299 struct sg_table *sgt,
300 enum dma_data_direction dir)
301{
302 struct drm_gem_object *obj = attach->dmabuf->priv;
303 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
304
305 if (bo->tbo.resource &&
306 bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP) {
307 amdgpu_ttm_mmio_remap_free_sgt(attach->dev, dir, sgt);
308 return;
309 }
310
311 if (sg_page(sgt->sgl)) {
312 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
313 sg_free_table(sgt);
314 kfree(sgt);
315 } else {
316 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
317 }
318}
319
320/**
321 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
322 * @dma_buf: Shared DMA buffer
323 * @direction: Direction of DMA transfer
324 *
325 * This is called before CPU access to the shared DMA buffer's memory. If it's
326 * a read access, the buffer is moved to the GTT domain if possible, for optimal
327 * CPU read performance.
328 *
329 * Returns:
330 * 0 on success or a negative error code on failure.
331 */
332static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
333 enum dma_data_direction direction)
334{
335 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
336 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
337 struct ttm_operation_ctx ctx = { true, false };
338 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
339 int ret;
340 bool reads = (direction == DMA_BIDIRECTIONAL ||
341 direction == DMA_FROM_DEVICE);
342
343 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
344 return 0;
345
346 /* move to gtt */
347 ret = amdgpu_bo_reserve(bo, false);
348 if (unlikely(ret != 0))
349 return ret;
350
351 if (!bo->tbo.pin_count &&
352 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
353 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
354 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
355 }
356
357 amdgpu_bo_unreserve(bo);
358 return ret;
359}
360
361static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map)
362{
363 struct drm_gem_object *obj = dma_buf->priv;
364 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
365 int ret;
366
367 /*
368 * Pin to keep buffer in place while it's vmap'ed. The actual
369 * domain is not that important as long as it's mapable. Using
370 * GTT and VRAM should be compatible with most use cases.
371 */
372 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM);
373 if (ret)
374 return ret;
375 ret = drm_gem_dmabuf_vmap(dma_buf, map);
376 if (ret)
377 amdgpu_bo_unpin(bo);
378
379 return ret;
380}
381
382static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map)
383{
384 struct drm_gem_object *obj = dma_buf->priv;
385 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
386
387 drm_gem_dmabuf_vunmap(dma_buf, map);
388 amdgpu_bo_unpin(bo);
389}
390
391const struct dma_buf_ops amdgpu_dmabuf_ops = {
392 .attach = amdgpu_dma_buf_attach,
393 .detach = amdgpu_dma_buf_detach,
394 .pin = amdgpu_dma_buf_pin,
395 .unpin = amdgpu_dma_buf_unpin,
396 .map_dma_buf = amdgpu_dma_buf_map,
397 .unmap_dma_buf = amdgpu_dma_buf_unmap,
398 .release = drm_gem_dmabuf_release,
399 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
400 .mmap = drm_gem_dmabuf_mmap,
401 .vmap = amdgpu_dma_buf_vmap,
402 .vunmap = amdgpu_dma_buf_vunmap,
403};
404
405/**
406 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
407 * @gobj: GEM BO
408 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
409 *
410 * The main work is done by the &drm_gem_prime_export helper.
411 *
412 * Returns:
413 * Shared DMA buffer representing the GEM BO from the given device.
414 */
415struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
416 int flags)
417{
418 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
419 struct dma_buf *buf;
420 struct ttm_operation_ctx ctx = {
421 .interruptible = true,
422 .no_wait_gpu = true,
423 /* We opt to avoid OOM on system pages allocations */
424 .gfp_retry_mayfail = true,
425 .allow_res_evict = false,
426 };
427 int ret;
428
429 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
430 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
431 return ERR_PTR(-EPERM);
432
433 ret = ttm_bo_setup_export(&bo->tbo, &ctx);
434 if (ret)
435 return ERR_PTR(ret);
436
437 buf = drm_gem_prime_export(gobj, flags);
438 if (!IS_ERR(buf))
439 buf->ops = &amdgpu_dmabuf_ops;
440
441 return buf;
442}
443
444/**
445 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
446 *
447 * @dev: DRM device
448 * @dma_buf: DMA-buf
449 *
450 * Creates an empty SG BO for DMA-buf import.
451 *
452 * Returns:
453 * A new GEM BO of the given DRM device, representing the memory
454 * described by the given DMA-buf attachment and scatter/gather table.
455 */
456static struct drm_gem_object *
457amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
458{
459 struct dma_resv *resv = dma_buf->resv;
460 struct amdgpu_device *adev = drm_to_adev(dev);
461 struct drm_gem_object *gobj;
462 struct amdgpu_bo *bo;
463 uint64_t flags = 0;
464 int ret;
465
466 dma_resv_lock(resv, NULL);
467
468 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
469 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
470
471 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
472 AMDGPU_GEM_CREATE_COHERENT |
473 AMDGPU_GEM_CREATE_EXT_COHERENT |
474 AMDGPU_GEM_CREATE_UNCACHED);
475 }
476
477 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
478 AMDGPU_GEM_DOMAIN_CPU, flags,
479 ttm_bo_type_sg, resv, &gobj, 0);
480 if (ret)
481 goto error;
482
483 bo = gem_to_amdgpu_bo(gobj);
484 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
485 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
486
487 dma_resv_unlock(resv);
488 return gobj;
489
490error:
491 dma_resv_unlock(resv);
492 return ERR_PTR(ret);
493}
494
495/**
496 * amdgpu_dma_buf_move_notify - &attach.invalidate_mappings implementation
497 *
498 * @attach: the DMA-buf attachment
499 *
500 * Invalidate the DMA-buf attachment, making sure that the we re-create the
501 * mapping before the next use.
502 */
503static void
504amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
505{
506 struct drm_gem_object *obj = attach->importer_priv;
507 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
508 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
509 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
510 struct ttm_operation_ctx ctx = { false, false };
511 struct ttm_placement placement = {};
512 struct amdgpu_vm_bo_base *bo_base;
513 int r;
514
515 /* FIXME: This should be after the "if", but needs a fix to make sure
516 * DMABuf imports are initialized in the right VM list.
517 */
518 amdgpu_vm_bo_invalidate(bo, false);
519 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
520 return;
521
522 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
523 if (r) {
524 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
525 return;
526 }
527
528 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
529 struct amdgpu_vm *vm = bo_base->vm;
530 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
531
532 if (ticket) {
533 /* When we get an error here it means that somebody
534 * else is holding the VM lock and updating page tables
535 * So we can just continue here.
536 */
537 r = dma_resv_lock(resv, ticket);
538 if (r)
539 continue;
540
541 } else {
542 /* TODO: This is more problematic and we actually need
543 * to allow page tables updates without holding the
544 * lock.
545 */
546 if (!dma_resv_trylock(resv))
547 continue;
548 }
549
550 /* Reserve fences for two SDMA page table updates */
551 r = dma_resv_reserve_fences(resv, 2);
552 if (!r)
553 r = amdgpu_vm_clear_freed(adev, vm, NULL);
554
555 /* Don't pass 'ticket' to amdgpu_vm_handle_moved: we want the clear=true
556 * path to be used otherwise we might update the PT of another process
557 * while it's using the BO.
558 * With clear=true, amdgpu_vm_bo_update will sync to command submission
559 * from the same VM.
560 */
561 if (!r)
562 r = amdgpu_vm_handle_moved(adev, vm, NULL);
563
564 if (r && r != -EBUSY)
565 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
566 r);
567
568 dma_resv_unlock(resv);
569 }
570}
571
572static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
573 .allow_peer2peer = true,
574 .invalidate_mappings = amdgpu_dma_buf_move_notify
575};
576
577/**
578 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
579 * @dev: DRM device
580 * @dma_buf: Shared DMA buffer
581 *
582 * Import a dma_buf into a the driver and potentially create a new GEM object.
583 *
584 * Returns:
585 * GEM BO representing the shared DMA buffer for the given device.
586 */
587struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
588 struct dma_buf *dma_buf)
589{
590 struct dma_buf_attachment *attach;
591 struct drm_gem_object *obj;
592
593 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
594 obj = dma_buf->priv;
595 if (obj->dev == dev) {
596 /*
597 * Importing dmabuf exported from out own gem increases
598 * refcount on gem itself instead of f_count of dmabuf.
599 */
600 drm_gem_object_get(obj);
601 return obj;
602 }
603 }
604
605 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
606 if (IS_ERR(obj))
607 return obj;
608
609 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
610 &amdgpu_dma_buf_attach_ops, obj);
611 if (IS_ERR(attach)) {
612 drm_gem_object_put(obj);
613 return ERR_CAST(attach);
614 }
615
616 get_dma_buf(dma_buf);
617 obj->import_attach = attach;
618 return obj;
619}
620
621/**
622 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
623 *
624 * @adev: amdgpu_device pointer of the importer
625 * @bo: amdgpu buffer object
626 *
627 * Returns:
628 * True if dmabuf accessible over xgmi, false otherwise.
629 */
630bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
631 struct amdgpu_bo *bo)
632{
633 struct drm_gem_object *obj = &bo->tbo.base;
634 struct drm_gem_object *gobj;
635
636 if (!adev)
637 return false;
638
639 if (drm_gem_is_imported(obj)) {
640 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
641
642 if (dma_buf->ops != &amdgpu_dmabuf_ops)
643 /* No XGMI with non AMD GPUs */
644 return false;
645
646 gobj = dma_buf->priv;
647 bo = gem_to_amdgpu_bo(gobj);
648 }
649
650 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
651 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
652 return true;
653
654 return false;
655}