projects/linux·blob master · refs

99 lines · 3.2 KiB

1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_IDS_H__
24#define __AMDGPU_IDS_H__
25
26#include <linux/types.h>
27#include <linux/mutex.h>
28#include <linux/list.h>
29#include <linux/dma-fence.h>
30
31#include "amdgpu_sync.h"
32
33/* maximum number of VMIDs */
34#define AMDGPU_NUM_VMID 16
35
36struct amdgpu_device;
37struct amdgpu_fpriv;
38struct amdgpu_vm;
39struct amdgpu_ring;
40struct amdgpu_sync;
41struct amdgpu_job;
42
43struct amdgpu_vmid {
44 struct list_head list;
45 struct amdgpu_sync active;
46 struct dma_fence *last_flush;
47 uint64_t owner;
48
49 uint64_t pd_gpu_addr;
50 /* last flushed PD/PT update */
51 uint64_t flushed_updates;
52
53 uint32_t current_gpu_reset_count;
54
55 uint32_t gds_base;
56 uint32_t gds_size;
57 uint32_t gws_base;
58 uint32_t gws_size;
59 uint32_t oa_base;
60 uint32_t oa_size;
61
62 unsigned pasid;
63 struct dma_fence *pasid_mapping;
64};
65
66struct amdgpu_vmid_mgr {
67 struct mutex lock;
68 unsigned num_ids;
69 struct list_head ids_lru;
70 struct amdgpu_vmid ids[AMDGPU_NUM_VMID];
71 bool reserved_vmid;
72};
73
74int amdgpu_pasid_alloc(unsigned int bits, struct amdgpu_fpriv *fpriv);
75void amdgpu_pasid_lock(unsigned long *flags);
76void amdgpu_pasid_unlock(unsigned long flags);
77struct amdgpu_fpriv *amdgpu_pasid_get_fpriv_locked(u32 pasid);
78void amdgpu_pasid_free(u32 pasid);
79void amdgpu_pasid_free_delayed(struct dma_resv *resv,
80 u32 pasid);
81void amdgpu_pasid_mgr_cleanup(void);
82
83bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
84 struct amdgpu_vmid *id);
85bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub);
86int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
87 unsigned vmhub);
88void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
89 unsigned vmhub);
90int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
91 struct amdgpu_job *job, struct dma_fence **fence);
92void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
93 unsigned vmid);
94void amdgpu_vmid_reset_all(struct amdgpu_device *adev);
95
96void amdgpu_vmid_mgr_init(struct amdgpu_device *adev);
97void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev);
98
99#endif