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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29/**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45#include <linux/irq.h>
46#include <linux/pci.h>
47
48#include <drm/drm_vblank.h>
49#include <drm/amdgpu_drm.h>
50#include <drm/drm_drv.h>
51#include "amdgpu.h"
52#include "amdgpu_ih.h"
53#include "atom.h"
54#include "amdgpu_connectors.h"
55#include "amdgpu_trace.h"
56#include "amdgpu_amdkfd.h"
57#include "amdgpu_ras.h"
58
59#include <linux/pm_runtime.h>
60
61#ifdef CONFIG_DRM_AMD_DC
62#include "amdgpu_dm_irq.h"
63#endif
64
65#define AMDGPU_WAIT_IDLE_TIMEOUT 200
66
67const char *soc15_ih_clientid_name[] = {
68 "IH",
69 "SDMA2 or ACP",
70 "ATHUB",
71 "BIF",
72 "SDMA3 or DCE",
73 "SDMA4 or ISP",
74 "VMC1 or PCIE0",
75 "RLC",
76 "SDMA0",
77 "SDMA1",
78 "SE0SH",
79 "SE1SH",
80 "SE2SH",
81 "SE3SH",
82 "VCN1 or UVD1",
83 "THM",
84 "VCN or UVD",
85 "SDMA5 or VCE0",
86 "VMC",
87 "SDMA6 or XDMA",
88 "GRBM_CP",
89 "ATS",
90 "ROM_SMUIO",
91 "DF",
92 "SDMA7 or VCE1",
93 "PWR",
94 "reserved",
95 "UTCL2",
96 "EA",
97 "UTCL2LOG",
98 "MP0",
99 "MP1"
100};
101
102const char *soc_v1_0_ih_clientid_name[] = {
103 "IH",
104 "Reserved",
105 "ATHUB",
106 "BIF",
107 "Reserved",
108 "Reserved",
109 "Reserved",
110 "RLC",
111 "Reserved",
112 "Reserved",
113 "GFX",
114 "IMU",
115 "Reserved",
116 "Reserved",
117 "VCN1 or UVD1",
118 "THM",
119 "VCN or UVD",
120 "Reserved",
121 "VMC",
122 "Reserved",
123 "GRBM_CP",
124 "GC_AID",
125 "ROM_SMUIO",
126 "DF",
127 "Reserved",
128 "PWR",
129 "LSDMA",
130 "GC_UTCL2",
131 "nHT",
132 "Reserved",
133 "MP0",
134 "MP1",
135};
136
137const int node_id_to_phys_map[NODEID_MAX] = {
138 [AID0_NODEID] = 0,
139 [XCD0_NODEID] = 0,
140 [XCD1_NODEID] = 1,
141 [AID1_NODEID] = 1,
142 [XCD2_NODEID] = 2,
143 [XCD3_NODEID] = 3,
144 [AID2_NODEID] = 2,
145 [XCD4_NODEID] = 4,
146 [XCD5_NODEID] = 5,
147 [AID3_NODEID] = 3,
148 [XCD6_NODEID] = 6,
149 [XCD7_NODEID] = 7,
150};
151
152/**
153 * amdgpu_irq_disable_all - disable *all* interrupts
154 *
155 * @adev: amdgpu device pointer
156 *
157 * Disable all types of interrupts from all sources.
158 */
159void amdgpu_irq_disable_all(struct amdgpu_device *adev)
160{
161 unsigned long irqflags;
162 unsigned int i, j, k;
163 int r;
164
165 spin_lock_irqsave(&adev->irq.lock, irqflags);
166 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
167 if (!adev->irq.client[i].sources)
168 continue;
169
170 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
171 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
172
173 if (!src || !src->funcs->set || !src->num_types)
174 continue;
175
176 for (k = 0; k < src->num_types; ++k) {
177 r = src->funcs->set(adev, src, k,
178 AMDGPU_IRQ_STATE_DISABLE);
179 if (r)
180 dev_err(adev->dev,
181 "error disabling interrupt (%d)\n",
182 r);
183 }
184 }
185 }
186 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
187}
188
189/**
190 * amdgpu_irq_handler - IRQ handler
191 *
192 * @irq: IRQ number (unused)
193 * @arg: pointer to DRM device
194 *
195 * IRQ handler for amdgpu driver (all ASICs).
196 *
197 * Returns:
198 * result of handling the IRQ, as defined by &irqreturn_t
199 */
200static irqreturn_t amdgpu_irq_handler(int irq, void *arg)
201{
202 struct drm_device *dev = (struct drm_device *) arg;
203 struct amdgpu_device *adev = drm_to_adev(dev);
204 irqreturn_t ret;
205
206 ret = amdgpu_ih_process(adev, &adev->irq.ih);
207 if (ret == IRQ_HANDLED)
208 pm_runtime_mark_last_busy(dev->dev);
209
210 amdgpu_ras_interrupt_fatal_error_handler(adev);
211
212 return ret;
213}
214
215/**
216 * amdgpu_irq_handle_ih1 - kick of processing for IH1
217 *
218 * @work: work structure in struct amdgpu_irq
219 *
220 * Kick of processing IH ring 1.
221 */
222static void amdgpu_irq_handle_ih1(struct work_struct *work)
223{
224 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
225 irq.ih1_work);
226
227 amdgpu_ih_process(adev, &adev->irq.ih1);
228}
229
230/**
231 * amdgpu_irq_handle_ih2 - kick of processing for IH2
232 *
233 * @work: work structure in struct amdgpu_irq
234 *
235 * Kick of processing IH ring 2.
236 */
237static void amdgpu_irq_handle_ih2(struct work_struct *work)
238{
239 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
240 irq.ih2_work);
241
242 amdgpu_ih_process(adev, &adev->irq.ih2);
243}
244
245/**
246 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
247 *
248 * @work: work structure in struct amdgpu_irq
249 *
250 * Kick of processing IH soft ring.
251 */
252static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
253{
254 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
255 irq.ih_soft_work);
256
257 amdgpu_ih_process(adev, &adev->irq.ih_soft);
258}
259
260/**
261 * amdgpu_msi_ok - check whether MSI functionality is enabled
262 *
263 * @adev: amdgpu device pointer (unused)
264 *
265 * Checks whether MSI functionality has been disabled via module parameter
266 * (all ASICs).
267 *
268 * Returns:
269 * *true* if MSIs are allowed to be enabled or *false* otherwise
270 */
271static bool amdgpu_msi_ok(struct amdgpu_device *adev)
272{
273 if (amdgpu_msi == 1)
274 return true;
275 else if (amdgpu_msi == 0)
276 return false;
277
278 return true;
279}
280
281void amdgpu_restore_msix(struct amdgpu_device *adev)
282{
283 u16 ctrl;
284
285 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
286 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
287 return;
288
289 /* VF FLR */
290 ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
291 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
292 ctrl |= PCI_MSIX_FLAGS_ENABLE;
293 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
294}
295
296/**
297 * amdgpu_irq_init - initialize interrupt handling
298 *
299 * @adev: amdgpu device pointer
300 *
301 * Sets up work functions for hotplug and reset interrupts, enables MSI
302 * functionality, initializes vblank, hotplug and reset interrupt handling.
303 *
304 * Returns:
305 * 0 on success or error code on failure
306 */
307int amdgpu_irq_init(struct amdgpu_device *adev)
308{
309 unsigned int irq, flags;
310 int r;
311
312 /* Enable MSI if not disabled by module parameter */
313 adev->irq.msi_enabled = false;
314
315 if (!amdgpu_msi_ok(adev))
316 flags = PCI_IRQ_INTX;
317 else
318 flags = PCI_IRQ_ALL_TYPES;
319
320 /* we only need one vector */
321 r = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
322 if (r < 0) {
323 dev_err(adev->dev, "Failed to alloc msi vectors\n");
324 return r;
325 }
326
327 if (amdgpu_msi_ok(adev)) {
328 adev->irq.msi_enabled = true;
329 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
330 }
331
332 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
333 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
334 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
335
336 /* Use vector 0 for MSI-X. */
337 r = pci_irq_vector(adev->pdev, 0);
338 if (r < 0)
339 goto free_vectors;
340 irq = r;
341
342 /* PCI devices require shared interrupts. */
343 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name,
344 adev_to_drm(adev));
345 if (r)
346 goto free_vectors;
347
348 adev->irq.installed = true;
349 adev->irq.irq = irq;
350 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
351
352 dev_dbg(adev->dev, "irq initialized.\n");
353 return 0;
354
355free_vectors:
356 if (adev->irq.msi_enabled)
357 pci_free_irq_vectors(adev->pdev);
358
359 adev->irq.msi_enabled = false;
360 return r;
361}
362
363void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
364{
365 if (adev->irq.installed) {
366 free_irq(adev->irq.irq, adev_to_drm(adev));
367 adev->irq.installed = false;
368 if (adev->irq.msi_enabled)
369 pci_free_irq_vectors(adev->pdev);
370 }
371
372 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
373 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
374 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
375 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
376}
377
378/**
379 * amdgpu_irq_fini_sw - shut down interrupt handling
380 *
381 * @adev: amdgpu device pointer
382 *
383 * Tears down work functions for hotplug and reset interrupts, disables MSI
384 * functionality, shuts down vblank, hotplug and reset interrupt handling,
385 * turns off interrupts from all sources (all ASICs).
386 */
387void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
388{
389 unsigned int i, j;
390
391 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
392 if (!adev->irq.client[i].sources)
393 continue;
394
395 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
396 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
397
398 if (!src)
399 continue;
400
401 kfree(src->enabled_types);
402 src->enabled_types = NULL;
403 }
404 kfree(adev->irq.client[i].sources);
405 adev->irq.client[i].sources = NULL;
406 }
407}
408
409/**
410 * amdgpu_irq_add_id - register IRQ source
411 *
412 * @adev: amdgpu device pointer
413 * @client_id: client id
414 * @src_id: source id
415 * @source: IRQ source pointer
416 *
417 * Registers IRQ source on a client.
418 *
419 * Returns:
420 * 0 on success or error code otherwise
421 */
422int amdgpu_irq_add_id(struct amdgpu_device *adev,
423 unsigned int client_id, unsigned int src_id,
424 struct amdgpu_irq_src *source)
425{
426 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
427 return -EINVAL;
428
429 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
430 return -EINVAL;
431
432 if (!source->funcs)
433 return -EINVAL;
434
435 if (!adev->irq.client[client_id].sources) {
436 adev->irq.client[client_id].sources =
437 kzalloc_objs(struct amdgpu_irq_src *,
438 AMDGPU_MAX_IRQ_SRC_ID);
439 if (!adev->irq.client[client_id].sources)
440 return -ENOMEM;
441 }
442
443 if (adev->irq.client[client_id].sources[src_id] != NULL)
444 return -EINVAL;
445
446 if (source->num_types && !source->enabled_types) {
447 atomic_t *types;
448
449 types = kzalloc_objs(atomic_t, source->num_types);
450 if (!types)
451 return -ENOMEM;
452
453 source->enabled_types = types;
454 }
455
456 adev->irq.client[client_id].sources[src_id] = source;
457 return 0;
458}
459
460/**
461 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
462 *
463 * @adev: amdgpu device pointer
464 * @ih: interrupt ring instance
465 *
466 * Dispatches IRQ to IP blocks.
467 */
468void amdgpu_irq_dispatch(struct amdgpu_device *adev,
469 struct amdgpu_ih_ring *ih)
470{
471 u32 ring_index = ih->rptr >> 2;
472 struct amdgpu_iv_entry entry;
473 unsigned int client_id, src_id;
474 struct amdgpu_irq_src *src;
475 bool handled = false;
476 int r;
477
478 entry.ih = ih;
479 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
480
481 /*
482 * timestamp is not supported on some legacy SOCs (cik, cz, iceland,
483 * si and tonga), so initialize timestamp and timestamp_src to 0
484 */
485 entry.timestamp = 0;
486 entry.timestamp_src = 0;
487
488 amdgpu_ih_decode_iv(adev, &entry);
489
490 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
491
492 client_id = entry.client_id;
493 src_id = entry.src_id;
494
495 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
496 dev_dbg(adev->dev, "Invalid client_id in IV: %d\n", client_id);
497
498 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
499 dev_dbg(adev->dev, "Invalid src_id in IV: %d\n", src_id);
500
501 } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) ||
502 (client_id == SOC15_IH_CLIENTID_ISP)) &&
503 adev->irq.virq[src_id]) {
504 generic_handle_domain_irq(adev->irq.domain, src_id);
505
506 } else if (!adev->irq.client[client_id].sources) {
507 dev_dbg(adev->dev,
508 "Unregistered interrupt client_id: %d src_id: %d\n",
509 client_id, src_id);
510
511 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
512 r = src->funcs->process(adev, src, &entry);
513 if (r < 0)
514 dev_err(adev->dev, "error processing interrupt (%d)\n",
515 r);
516 else if (r)
517 handled = true;
518
519 } else {
520 dev_dbg(adev->dev,
521 "Unregistered interrupt src_id: %d of client_id:%d\n",
522 src_id, client_id);
523 }
524
525 /* Send it to amdkfd as well if it isn't already handled */
526 if (!handled)
527 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
528
529 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp))
530 ih->processed_timestamp = entry.timestamp;
531}
532
533/**
534 * amdgpu_irq_delegate - delegate IV to soft IH ring
535 *
536 * @adev: amdgpu device pointer
537 * @entry: IV entry
538 * @num_dw: size of IV
539 *
540 * Delegate the IV to the soft IH ring and schedule processing of it. Used
541 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
542 */
543void amdgpu_irq_delegate(struct amdgpu_device *adev,
544 struct amdgpu_iv_entry *entry,
545 unsigned int num_dw)
546{
547 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);
548 queue_work(system_dfl_wq, &adev->irq.ih_soft_work);
549}
550
551/**
552 * amdgpu_irq_update - update hardware interrupt state
553 *
554 * @adev: amdgpu device pointer
555 * @src: interrupt source pointer
556 * @type: type of interrupt
557 *
558 * Updates interrupt state for the specific source (all ASICs).
559 */
560int amdgpu_irq_update(struct amdgpu_device *adev,
561 struct amdgpu_irq_src *src, unsigned int type)
562{
563 unsigned long irqflags;
564 enum amdgpu_interrupt_state state;
565 int r;
566
567 spin_lock_irqsave(&adev->irq.lock, irqflags);
568
569 /* We need to determine after taking the lock, otherwise
570 * we might disable just enabled interrupts again
571 */
572 if (amdgpu_irq_enabled(adev, src, type))
573 state = AMDGPU_IRQ_STATE_ENABLE;
574 else
575 state = AMDGPU_IRQ_STATE_DISABLE;
576
577 r = src->funcs->set(adev, src, type, state);
578 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
579 return r;
580}
581
582/**
583 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
584 *
585 * @adev: amdgpu device pointer
586 *
587 * Updates state of all types of interrupts on all sources on resume after
588 * reset.
589 */
590void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
591{
592 int i, j, k;
593
594 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
595 amdgpu_restore_msix(adev);
596
597 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
598 if (!adev->irq.client[i].sources)
599 continue;
600
601 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
602 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
603
604 if (!src || !src->funcs || !src->funcs->set)
605 continue;
606 for (k = 0; k < src->num_types; k++)
607 amdgpu_irq_update(adev, src, k);
608 }
609 }
610}
611
612/**
613 * amdgpu_irq_get - enable interrupt
614 *
615 * @adev: amdgpu device pointer
616 * @src: interrupt source pointer
617 * @type: type of interrupt
618 *
619 * Enables specified type of interrupt on the specified source (all ASICs).
620 *
621 * Returns:
622 * 0 on success or error code otherwise
623 */
624int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
625 unsigned int type)
626{
627 if (!adev->irq.installed)
628 return -ENOENT;
629
630 if (type >= src->num_types)
631 return -EINVAL;
632
633 if (!src->enabled_types || !src->funcs->set)
634 return -EINVAL;
635
636 if (atomic_inc_return(&src->enabled_types[type]) == 1)
637 return amdgpu_irq_update(adev, src, type);
638
639 return 0;
640}
641
642/**
643 * amdgpu_irq_put - disable interrupt
644 *
645 * @adev: amdgpu device pointer
646 * @src: interrupt source pointer
647 * @type: type of interrupt
648 *
649 * Enables specified type of interrupt on the specified source (all ASICs).
650 *
651 * Returns:
652 * 0 on success or error code otherwise
653 */
654int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
655 unsigned int type)
656{
657 /* When the threshold is reached,the interrupt source may not be enabled.return -EINVAL */
658 if (amdgpu_ras_is_rma(adev) && !amdgpu_irq_enabled(adev, src, type))
659 return -EINVAL;
660
661 if (!adev->irq.installed)
662 return -ENOENT;
663
664 if (type >= src->num_types)
665 return -EINVAL;
666
667 if (!src->enabled_types || !src->funcs->set)
668 return -EINVAL;
669
670 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))
671 return -EINVAL;
672
673 if (atomic_dec_and_test(&src->enabled_types[type]))
674 return amdgpu_irq_update(adev, src, type);
675
676 return 0;
677}
678
679/**
680 * amdgpu_irq_enabled - check whether interrupt is enabled or not
681 *
682 * @adev: amdgpu device pointer
683 * @src: interrupt source pointer
684 * @type: type of interrupt
685 *
686 * Checks whether the given type of interrupt is enabled on the given source.
687 *
688 * Returns:
689 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
690 * invalid parameters
691 */
692bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
693 unsigned int type)
694{
695 if (!adev->irq.installed)
696 return false;
697
698 if (type >= src->num_types)
699 return false;
700
701 if (!src->enabled_types || !src->funcs->set)
702 return false;
703
704 return !!atomic_read(&src->enabled_types[type]);
705}
706
707/* XXX: Generic IRQ handling */
708static void amdgpu_irq_mask(struct irq_data *irqd)
709{
710 /* XXX */
711}
712
713static void amdgpu_irq_unmask(struct irq_data *irqd)
714{
715 /* XXX */
716}
717
718/* amdgpu hardware interrupt chip descriptor */
719static struct irq_chip amdgpu_irq_chip = {
720 .name = "amdgpu-ih",
721 .irq_mask = amdgpu_irq_mask,
722 .irq_unmask = amdgpu_irq_unmask,
723};
724
725/**
726 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
727 *
728 * @d: amdgpu IRQ domain pointer (unused)
729 * @irq: virtual IRQ number
730 * @hwirq: hardware irq number
731 *
732 * Current implementation assigns simple interrupt handler to the given virtual
733 * IRQ.
734 *
735 * Returns:
736 * 0 on success or error code otherwise
737 */
738static int amdgpu_irqdomain_map(struct irq_domain *d,
739 unsigned int irq, irq_hw_number_t hwirq)
740{
741 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
742 return -EPERM;
743
744 irq_set_chip_and_handler(irq,
745 &amdgpu_irq_chip, handle_simple_irq);
746 return 0;
747}
748
749/* Implementation of methods for amdgpu IRQ domain */
750static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
751 .map = amdgpu_irqdomain_map,
752};
753
754/**
755 * amdgpu_irq_add_domain - create a linear IRQ domain
756 *
757 * @adev: amdgpu device pointer
758 *
759 * Creates an IRQ domain for GPU interrupt sources
760 * that may be driven by another driver (e.g., ACP).
761 *
762 * Returns:
763 * 0 on success or error code otherwise
764 */
765int amdgpu_irq_add_domain(struct amdgpu_device *adev)
766{
767 adev->irq.domain = irq_domain_create_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
768 &amdgpu_hw_irqdomain_ops, adev);
769 if (!adev->irq.domain) {
770 dev_err(adev->dev, "GPU irq add domain failed\n");
771 return -ENODEV;
772 }
773
774 return 0;
775}
776
777/**
778 * amdgpu_irq_remove_domain - remove the IRQ domain
779 *
780 * @adev: amdgpu device pointer
781 *
782 * Removes the IRQ domain for GPU interrupt sources
783 * that may be driven by another driver (e.g., ACP).
784 */
785void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
786{
787 if (adev->irq.domain) {
788 irq_domain_remove(adev->irq.domain);
789 adev->irq.domain = NULL;
790 }
791}
792
793/**
794 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
795 *
796 * @adev: amdgpu device pointer
797 * @src_id: IH source id
798 *
799 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
800 * Use this for components that generate a GPU interrupt, but are driven
801 * by a different driver (e.g., ACP).
802 *
803 * Returns:
804 * Linux IRQ
805 */
806unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id)
807{
808 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
809
810 return adev->irq.virq[src_id];
811}