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1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef AMDGPU_MODE_H
31#define AMDGPU_MODE_H
32
33#include <drm/display/drm_dp_helper.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_encoder.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_framebuffer.h>
38#include <drm/drm_probe_helper.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41#include "amdgpu_irq.h"
42
43#include <drm/display/drm_dp_mst_helper.h>
44#include "modules/inc/mod_freesync.h"
45#include "amdgpu_dm_irq_params.h"
46#include "amdgpu_dm_ism.h"
47
48struct amdgpu_bo;
49struct amdgpu_device;
50struct amdgpu_encoder;
51struct amdgpu_router;
52struct amdgpu_hpd;
53struct edid;
54struct drm_edid;
55
56#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
57#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
58#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
59#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
60
61#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base)
62
63#define AMDGPU_MAX_HPD_PINS 6
64#define AMDGPU_MAX_CRTCS 6
65#define AMDGPU_MAX_PLANES 6
66#define AMDGPU_MAX_AFMT_BLOCKS 9
67
68enum amdgpu_rmx_type {
69 RMX_OFF,
70 RMX_FULL,
71 RMX_CENTER,
72 RMX_ASPECT
73};
74
75enum amdgpu_underscan_type {
76 UNDERSCAN_OFF,
77 UNDERSCAN_ON,
78 UNDERSCAN_AUTO,
79};
80
81#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
82#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
83
84enum amdgpu_hpd_id {
85 AMDGPU_HPD_1 = 0,
86 AMDGPU_HPD_2,
87 AMDGPU_HPD_3,
88 AMDGPU_HPD_4,
89 AMDGPU_HPD_5,
90 AMDGPU_HPD_6,
91 AMDGPU_HPD_NONE = 0xff,
92};
93
94enum amdgpu_crtc_irq {
95 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
96 AMDGPU_CRTC_IRQ_VBLANK2,
97 AMDGPU_CRTC_IRQ_VBLANK3,
98 AMDGPU_CRTC_IRQ_VBLANK4,
99 AMDGPU_CRTC_IRQ_VBLANK5,
100 AMDGPU_CRTC_IRQ_VBLANK6,
101 AMDGPU_CRTC_IRQ_VLINE1,
102 AMDGPU_CRTC_IRQ_VLINE2,
103 AMDGPU_CRTC_IRQ_VLINE3,
104 AMDGPU_CRTC_IRQ_VLINE4,
105 AMDGPU_CRTC_IRQ_VLINE5,
106 AMDGPU_CRTC_IRQ_VLINE6,
107 AMDGPU_CRTC_IRQ_NONE = 0xff
108};
109
110enum amdgpu_pageflip_irq {
111 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
112 AMDGPU_PAGEFLIP_IRQ_D2,
113 AMDGPU_PAGEFLIP_IRQ_D3,
114 AMDGPU_PAGEFLIP_IRQ_D4,
115 AMDGPU_PAGEFLIP_IRQ_D5,
116 AMDGPU_PAGEFLIP_IRQ_D6,
117 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
118};
119
120enum amdgpu_flip_status {
121 AMDGPU_FLIP_NONE,
122 AMDGPU_FLIP_PENDING,
123 AMDGPU_FLIP_SUBMITTED
124};
125
126#define AMDGPU_MAX_I2C_BUS 16
127
128/* amdgpu gpio-based i2c
129 * 1. "mask" reg and bits
130 * grabs the gpio pins for software use
131 * 0=not held 1=held
132 * 2. "a" reg and bits
133 * output pin value
134 * 0=low 1=high
135 * 3. "en" reg and bits
136 * sets the pin direction
137 * 0=input 1=output
138 * 4. "y" reg and bits
139 * input pin value
140 * 0=low 1=high
141 */
142struct amdgpu_i2c_bus_rec {
143 bool valid;
144 /* id used by atom */
145 uint8_t i2c_id;
146 /* id used by atom */
147 enum amdgpu_hpd_id hpd;
148 /* can be used with hw i2c engine */
149 bool hw_capable;
150 /* uses multi-media i2c engine */
151 bool mm_i2c;
152 /* regs and bits */
153 uint32_t mask_clk_reg;
154 uint32_t mask_data_reg;
155 uint32_t a_clk_reg;
156 uint32_t a_data_reg;
157 uint32_t en_clk_reg;
158 uint32_t en_data_reg;
159 uint32_t y_clk_reg;
160 uint32_t y_data_reg;
161 uint32_t mask_clk_mask;
162 uint32_t mask_data_mask;
163 uint32_t a_clk_mask;
164 uint32_t a_data_mask;
165 uint32_t en_clk_mask;
166 uint32_t en_data_mask;
167 uint32_t y_clk_mask;
168 uint32_t y_data_mask;
169};
170
171#define AMDGPU_MAX_BIOS_CONNECTOR 16
172
173/* pll flags */
174#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
175#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
176#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
177#define AMDGPU_PLL_LEGACY (1 << 3)
178#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
179#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
180#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
181#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
182#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
183#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
184#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
185#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
186#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
187#define AMDGPU_PLL_IS_LCD (1 << 13)
188#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
189
190struct amdgpu_pll {
191 /* reference frequency */
192 uint32_t reference_freq;
193
194 /* fixed dividers */
195 uint32_t reference_div;
196 uint32_t post_div;
197
198 /* pll in/out limits */
199 uint32_t pll_in_min;
200 uint32_t pll_in_max;
201 uint32_t pll_out_min;
202 uint32_t pll_out_max;
203 uint32_t lcd_pll_out_min;
204 uint32_t lcd_pll_out_max;
205 uint32_t best_vco;
206
207 /* divider limits */
208 uint32_t min_ref_div;
209 uint32_t max_ref_div;
210 uint32_t min_post_div;
211 uint32_t max_post_div;
212 uint32_t min_feedback_div;
213 uint32_t max_feedback_div;
214 uint32_t min_frac_feedback_div;
215 uint32_t max_frac_feedback_div;
216
217 /* flags for the current clock */
218 uint32_t flags;
219
220 /* pll id */
221 uint32_t id;
222};
223
224struct amdgpu_i2c_chan {
225 struct i2c_adapter adapter;
226 struct drm_device *dev;
227 struct i2c_algo_bit_data bit;
228 struct amdgpu_i2c_bus_rec rec;
229 struct drm_dp_aux aux;
230 bool has_aux;
231 struct mutex mutex;
232};
233
234struct amdgpu_afmt {
235 bool enabled;
236 int offset;
237 bool last_buffer_filled_status;
238 int id;
239 struct amdgpu_audio_pin *pin;
240};
241
242/*
243 * Audio
244 */
245struct amdgpu_audio_pin {
246 int channels;
247 int rate;
248 int bits_per_sample;
249 u8 status_bits;
250 u8 category_code;
251 u32 offset;
252 bool connected;
253 u32 id;
254};
255
256struct amdgpu_audio {
257 bool enabled;
258 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
259 int num_pins;
260};
261
262struct amdgpu_display_funcs {
263 /* display watermarks */
264 void (*bandwidth_update)(struct amdgpu_device *adev);
265 /* get frame count */
266 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
267 /* set backlight level */
268 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
269 u8 level);
270 /* get backlight level */
271 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
272 /* hotplug detect */
273 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
274 void (*hpd_set_polarity)(struct amdgpu_device *adev,
275 enum amdgpu_hpd_id hpd);
276 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
277 /* pageflipping */
278 void (*page_flip)(struct amdgpu_device *adev,
279 int crtc_id, u64 crtc_base, bool async);
280 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
281 u32 *vbl, u32 *position);
282 /* display topology setup */
283 void (*add_encoder)(struct amdgpu_device *adev,
284 uint32_t encoder_enum,
285 uint32_t supported_device,
286 u16 caps);
287 void (*add_connector)(struct amdgpu_device *adev,
288 uint32_t connector_id,
289 uint32_t supported_device,
290 int connector_type,
291 struct amdgpu_i2c_bus_rec *i2c_bus,
292 uint16_t connector_object_id,
293 struct amdgpu_hpd *hpd,
294 struct amdgpu_router *router);
295
296
297};
298
299struct amdgpu_framebuffer {
300 struct drm_framebuffer base;
301
302 uint64_t tiling_flags;
303 bool tmz_surface;
304 bool gfx12_dcc;
305
306 /* caching for later use */
307 uint64_t address;
308};
309
310struct amdgpu_mode_info {
311 struct atom_context *atom_context;
312 struct card_info *atom_card_info;
313 bool mode_config_initialized;
314 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
315 struct drm_plane *planes[AMDGPU_MAX_PLANES];
316 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
317 /* DVI-I properties */
318 struct drm_property *coherent_mode_property;
319 /* DAC enable load detect */
320 struct drm_property *load_detect_property;
321 /* underscan */
322 struct drm_property *underscan_property;
323 struct drm_property *underscan_hborder_property;
324 struct drm_property *underscan_vborder_property;
325 /* audio */
326 struct drm_property *audio_property;
327 /* FMT dithering */
328 struct drm_property *dither_property;
329 /* Adaptive Backlight Modulation (power feature) */
330 struct drm_property *abm_level_property;
331 /* hardcoded DFP edid from BIOS */
332 const struct drm_edid *bios_hardcoded_edid;
333
334 /* firmware flags */
335 u32 firmware_flags;
336 /* pointer to backlight encoder */
337 struct amdgpu_encoder *bl_encoder;
338 u8 bl_level; /* saved backlight level */
339 struct amdgpu_audio audio; /* audio stuff */
340 int num_crtc; /* number of crtcs */
341 int num_hpd; /* number of hpd pins */
342 int num_dig; /* number of dig blocks */
343 bool gpu_vm_support; /* supports display from GTT */
344 int disp_priority;
345 const struct amdgpu_display_funcs *funcs;
346 const enum drm_plane_type *plane_type;
347
348 /* Driver-private color mgmt props */
349
350 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
351 * convert encoded values to light linear values before sampling or
352 * blending.
353 */
354 struct drm_property *plane_degamma_lut_property;
355 /* @plane_degamma_lut_size_property: Plane property to define the max
356 * size of degamma LUT as supported by the driver (read-only).
357 */
358 struct drm_property *plane_degamma_lut_size_property;
359 /**
360 * @plane_degamma_tf_property: Plane pre-defined transfer function to
361 * to go from scanout/encoded values to linear values.
362 */
363 struct drm_property *plane_degamma_tf_property;
364 /**
365 * @plane_hdr_mult_property:
366 */
367 struct drm_property *plane_hdr_mult_property;
368
369 struct drm_property *plane_ctm_property;
370 /**
371 * @plane_shaper_lut_property: Plane property to set pre-blending
372 * shaper LUT that converts color content before 3D LUT.
373 * If plane_shaper_tf_property != Identity TF, AMD color module will
374 * combine the user LUT values with pre-defined TF into the LUT
375 * parameters to be programmed.
376 */
377 struct drm_property *plane_shaper_lut_property;
378 /**
379 * @plane_shaper_lut_size_property: Plane property for the size of
380 * pre-blending shaper LUT as supported by the driver (read-only).
381 */
382 struct drm_property *plane_shaper_lut_size_property;
383 /**
384 * @plane_shaper_tf_property: Plane property to set a predefined
385 * transfer function for pre-blending shaper (before applying 3D LUT)
386 * with or without LUT. There is no shaper ROM, but we can use AMD
387 * color modules to program LUT parameters from predefined TF (or
388 * from a combination of pre-defined TF and the custom 1D LUT).
389 */
390 struct drm_property *plane_shaper_tf_property;
391 /**
392 * @plane_lut3d_property: Plane property for color transformation using
393 * a 3D LUT (pre-blending), a three-dimensional array where each
394 * element is an RGB triplet. Each dimension has the size of
395 * lut3d_size. The array contains samples from the approximated
396 * function. On AMD, values between samples are estimated by
397 * tetrahedral interpolation. The array is accessed with three indices,
398 * one for each input dimension (color channel), blue being the
399 * outermost dimension, red the innermost.
400 */
401 struct drm_property *plane_lut3d_property;
402 /**
403 * @plane_lut3d_size_property: Plane property to define the max size
404 * of 3D LUT as supported by the driver (read-only). The max size is
405 * the max size of one dimension and, therefore, the max number of
406 * entries for 3D LUT array is the 3D LUT size cubed.
407 */
408 struct drm_property *plane_lut3d_size_property;
409 /**
410 * @plane_blend_lut_property: Plane property for output gamma before
411 * blending. Userspace set a blend LUT to convert colors after 3D LUT
412 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they
413 * are sandwiching 3D LUT with two 1D LUT. If plane_blend_tf_property
414 * != Identity TF, AMD color module will combine the user LUT values
415 * with pre-defined TF into the LUT parameters to be programmed.
416 */
417 struct drm_property *plane_blend_lut_property;
418 /**
419 * @plane_blend_lut_size_property: Plane property to define the max
420 * size of blend LUT as supported by the driver (read-only).
421 */
422 struct drm_property *plane_blend_lut_size_property;
423 /**
424 * @plane_blend_tf_property: Plane property to set a predefined
425 * transfer function for pre-blending blend/out_gamma (after applying
426 * 3D LUT) with or without LUT. There is no blend ROM, but we can use
427 * AMD color modules to program LUT parameters from predefined TF (or
428 * from a combination of pre-defined TF and the custom 1D LUT).
429 */
430 struct drm_property *plane_blend_tf_property;
431 /* @regamma_tf_property: Transfer function for CRTC regamma
432 * (post-blending). Possible values are defined by `enum
433 * amdgpu_transfer_function`. There is no regamma ROM, but we can use
434 * AMD color modules to program LUT parameters from predefined TF (or
435 * from a combination of pre-defined TF and the custom 1D LUT).
436 */
437 struct drm_property *regamma_tf_property;
438};
439
440#define AMDGPU_MAX_BL_LEVEL 0xFF
441
442struct amdgpu_backlight_privdata {
443 struct amdgpu_encoder *encoder;
444 uint8_t negative;
445};
446
447struct amdgpu_atom_ss {
448 uint16_t percentage;
449 uint16_t percentage_divider;
450 uint8_t type;
451 uint16_t step;
452 uint8_t delay;
453 uint8_t range;
454 uint8_t refdiv;
455 /* asic_ss */
456 uint16_t rate;
457 uint16_t amount;
458};
459
460struct amdgpu_crtc {
461 struct drm_crtc base;
462 int crtc_id;
463 bool enabled;
464 bool can_tile;
465 uint32_t crtc_offset;
466 struct drm_gem_object *cursor_bo;
467 uint64_t cursor_addr;
468 int cursor_x;
469 int cursor_y;
470 int cursor_hot_x;
471 int cursor_hot_y;
472 int cursor_width;
473 int cursor_height;
474 int max_cursor_width;
475 int max_cursor_height;
476 enum amdgpu_rmx_type rmx_type;
477 u8 h_border;
478 u8 v_border;
479 fixed20_12 vsc;
480 fixed20_12 hsc;
481 struct drm_display_mode native_mode;
482 u32 pll_id;
483 /* page flipping */
484 struct amdgpu_flip_work *pflip_works;
485 enum amdgpu_flip_status pflip_status;
486 int deferred_flip_completion;
487 /* parameters access from DM IRQ handler */
488 struct dm_irq_params dm_irq_params;
489
490 /* DM idle state manager */
491 struct amdgpu_dm_ism ism;
492
493 /* pll sharing */
494 struct amdgpu_atom_ss ss;
495 bool ss_enabled;
496 u32 adjusted_clock;
497 int bpc;
498 u32 pll_reference_div;
499 u32 pll_post_div;
500 u32 pll_flags;
501 struct drm_encoder *encoder;
502 struct drm_connector *connector;
503 /* for dpm */
504 u32 line_time;
505 u32 lb_vblank_lead_lines;
506 struct drm_display_mode hw_mode;
507
508 int otg_inst;
509 struct drm_pending_vblank_event *event;
510
511 bool wb_pending;
512 bool wb_frame_done;
513 bool wb_enabled;
514 struct drm_writeback_connector *wb_conn;
515};
516
517struct amdgpu_encoder_atom_dig {
518 bool linkb;
519 /* atom dig */
520 bool coherent_mode;
521 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
522 /* atom lvds/edp */
523 uint32_t lcd_misc;
524 uint16_t panel_pwr_delay;
525 uint32_t lcd_ss_id;
526 /* panel mode */
527 struct drm_display_mode native_mode;
528 struct backlight_device *bl_dev;
529 int dpms_mode;
530 uint8_t backlight_level;
531 int panel_mode;
532 struct amdgpu_afmt *afmt;
533};
534
535struct amdgpu_encoder {
536 struct drm_encoder base;
537 uint32_t encoder_enum;
538 uint32_t encoder_id;
539 uint32_t devices;
540 uint32_t active_device;
541 uint32_t flags;
542 uint32_t pixel_clock;
543 enum amdgpu_rmx_type rmx_type;
544 enum amdgpu_underscan_type underscan_type;
545 uint32_t underscan_hborder;
546 uint32_t underscan_vborder;
547 struct drm_display_mode native_mode;
548 void *enc_priv;
549 int audio_polling_active;
550 bool is_ext_encoder;
551 u16 caps;
552};
553
554struct amdgpu_connector_atom_dig {
555 /* displayport */
556 u8 dpcd[DP_RECEIVER_CAP_SIZE];
557 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
558 u8 dp_sink_type;
559 int dp_clock;
560 int dp_lane_count;
561 bool edp_on;
562};
563
564struct amdgpu_gpio_rec {
565 bool valid;
566 u8 id;
567 u32 reg;
568 u32 mask;
569 u32 shift;
570};
571
572struct amdgpu_hpd {
573 enum amdgpu_hpd_id hpd;
574 u8 plugged_state;
575 struct amdgpu_gpio_rec gpio;
576};
577
578struct amdgpu_router {
579 u32 router_id;
580 struct amdgpu_i2c_bus_rec i2c_info;
581 u8 i2c_addr;
582 /* i2c mux */
583 bool ddc_valid;
584 u8 ddc_mux_type;
585 u8 ddc_mux_control_pin;
586 u8 ddc_mux_state;
587 /* clock/data mux */
588 bool cd_valid;
589 u8 cd_mux_type;
590 u8 cd_mux_control_pin;
591 u8 cd_mux_state;
592};
593
594enum amdgpu_connector_audio {
595 AMDGPU_AUDIO_DISABLE = 0,
596 AMDGPU_AUDIO_ENABLE = 1,
597 AMDGPU_AUDIO_AUTO = 2
598};
599
600enum amdgpu_connector_dither {
601 AMDGPU_FMT_DITHER_DISABLE = 0,
602 AMDGPU_FMT_DITHER_ENABLE = 1,
603};
604
605struct amdgpu_dm_dp_aux {
606 struct drm_dp_aux aux;
607 struct ddc_service *ddc_service;
608};
609
610struct amdgpu_i2c_adapter {
611 struct i2c_adapter base;
612
613 struct ddc_service *ddc_service;
614 bool oem;
615};
616
617#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
618
619struct amdgpu_connector {
620 struct drm_connector base;
621 uint32_t connector_id;
622 uint32_t devices;
623 struct amdgpu_i2c_chan *ddc_bus;
624 /* some systems have an hdmi and vga port with a shared ddc line */
625 bool shared_ddc;
626 bool use_digital;
627 /* we need to mind the EDID between detect
628 and get modes due to analog/digital/tvencoder */
629 const struct drm_edid *edid;
630 void *con_priv;
631 bool dac_load_detect;
632 bool detected_by_load; /* if the connection status was determined by load */
633 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
634 uint16_t connector_object_id;
635 struct amdgpu_hpd hpd;
636 struct amdgpu_router router;
637 struct amdgpu_i2c_chan *router_bus;
638 enum amdgpu_connector_audio audio;
639 enum amdgpu_connector_dither dither;
640 unsigned pixelclock_for_modeset;
641};
642
643/* TODO: start to use this struct and remove same field from base one */
644struct amdgpu_mst_connector {
645 struct amdgpu_connector base;
646
647 struct drm_dp_mst_topology_mgr mst_mgr;
648 struct amdgpu_dm_dp_aux dm_dp_aux;
649 struct drm_dp_mst_port *mst_output_port;
650 struct amdgpu_connector *mst_root;
651 bool is_mst_connector;
652 struct amdgpu_encoder *mst_encoder;
653};
654
655#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
656 ((em) == ATOM_ENCODER_MODE_DP_MST))
657
658/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
659#define DRM_SCANOUTPOS_VALID (1 << 0)
660#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
661#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
662#define USE_REAL_VBLANKSTART (1 << 30)
663#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
664
665void amdgpu_link_encoder_connector(struct drm_device *dev);
666
667struct drm_connector *
668amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
669struct drm_connector *
670amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
671bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
672 u32 pixel_clock);
673
674u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
675struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
676
677bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
678 bool use_aux);
679
680void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
681
682int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
683 unsigned int pipe, unsigned int flags, int *vpos,
684 int *hpos, ktime_t *stime, ktime_t *etime,
685 const struct drm_display_mode *mode);
686
687int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
688
689void amdgpu_enc_destroy(struct drm_encoder *encoder);
690void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
691bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
692 const struct drm_display_mode *mode,
693 struct drm_display_mode *adjusted_mode);
694void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
695 struct drm_display_mode *adjusted_mode);
696int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
697
698bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
699 bool in_vblank_irq, int *vpos,
700 int *hpos, ktime_t *stime, ktime_t *etime,
701 const struct drm_display_mode *mode);
702
703/* amdgpu_display.c */
704void amdgpu_display_print_display_setup(struct drm_device *dev);
705int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
706int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
707 struct drm_modeset_acquire_ctx *ctx);
708int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
709 struct drm_framebuffer *fb,
710 struct drm_pending_vblank_event *event,
711 uint32_t page_flip_flags, uint32_t target,
712 struct drm_modeset_acquire_ctx *ctx);
713extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
714
715#endif