projects/linux·blob master · refs

984 lines · 30.3 KiB

1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _AMDGPU_RAS_H
25#define _AMDGPU_RAS_H
26
27#include <linux/debugfs.h>
28#include <linux/list.h>
29#include <linux/kfifo.h>
30#include <linux/radix-tree.h>
31#include "ta_ras_if.h"
32#include "amdgpu_ras_eeprom.h"
33#include "amdgpu_smuio.h"
34
35struct amdgpu_iv_entry;
36
37#define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0)
38#define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1)
39#define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2)
40#define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3)
41#define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4)
42#define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5)
43#define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6)
44#define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7)
45#define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8)
46#define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11)
47#define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13)
48#define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x) AMDGPU_GET_REG_FIELD(x, 29, 29)
49#define AMDGPU_RAS_GPU_ERR_GENERIC(x) AMDGPU_GET_REG_FIELD(x, 30, 30)
50
51#define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 100
52#define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA
53#define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF
54
55#define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0)
56/* position of instance value in sub_block_index of
57 * ta_ras_trigger_error_input, the sub block uses lower 12 bits
58 */
59#define AMDGPU_RAS_INST_MASK 0xfffff000
60#define AMDGPU_RAS_INST_SHIFT 0xc
61
62#define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29
63#define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000
64
65/* Reserve 8 physical dram row for possible retirement.
66 * In worst cases, it will lose 8 * 2MB memory in vram domain */
67#define AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT (16ULL << 20)
68/* The high three bits indicates socketid */
69#define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
70
71#define RAS_EVENT_INVALID_ID (BIT_ULL(63))
72#define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63)))
73
74#define RAS_EVENT_LOG(adev, id, fmt, ...) \
75 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__)
76
77#define amdgpu_ras_mark_ras_event(adev, type) \
78 (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0)))
79
80enum amdgpu_ras_block {
81 AMDGPU_RAS_BLOCK__UMC = 0,
82 AMDGPU_RAS_BLOCK__SDMA,
83 AMDGPU_RAS_BLOCK__GFX,
84 AMDGPU_RAS_BLOCK__MMHUB,
85 AMDGPU_RAS_BLOCK__ATHUB,
86 AMDGPU_RAS_BLOCK__PCIE_BIF,
87 AMDGPU_RAS_BLOCK__HDP,
88 AMDGPU_RAS_BLOCK__XGMI_WAFL,
89 AMDGPU_RAS_BLOCK__DF,
90 AMDGPU_RAS_BLOCK__SMN,
91 AMDGPU_RAS_BLOCK__SEM,
92 AMDGPU_RAS_BLOCK__MP0,
93 AMDGPU_RAS_BLOCK__MP1,
94 AMDGPU_RAS_BLOCK__FUSE,
95 AMDGPU_RAS_BLOCK__MCA,
96 AMDGPU_RAS_BLOCK__VCN,
97 AMDGPU_RAS_BLOCK__JPEG,
98 AMDGPU_RAS_BLOCK__IH,
99 AMDGPU_RAS_BLOCK__MPIO,
100 AMDGPU_RAS_BLOCK__MMSCH,
101
102 AMDGPU_RAS_BLOCK__LAST,
103 AMDGPU_RAS_BLOCK__ANY = -1
104};
105
106enum amdgpu_ras_mca_block {
107 AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
108 AMDGPU_RAS_MCA_BLOCK__MP1,
109 AMDGPU_RAS_MCA_BLOCK__MPIO,
110 AMDGPU_RAS_MCA_BLOCK__IOHC,
111
112 AMDGPU_RAS_MCA_BLOCK__LAST
113};
114
115#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
116#define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST
117#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
118
119enum amdgpu_ras_gfx_subblock {
120 /* CPC */
121 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
122 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
123 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
124 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
125 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
126 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
127 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
128 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
129 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
130 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
131 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
132 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
133 /* CPF */
134 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
135 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
136 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
137 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
138 AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
139 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
140 /* CPG */
141 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
142 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
143 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
144 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
145 AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
146 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
147 /* GDS */
148 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
149 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
150 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
151 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
152 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
153 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
154 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
155 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
156 /* SPI */
157 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
158 /* SQ */
159 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
160 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
161 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
162 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
163 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
164 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
165 /* SQC (3 ranges) */
166 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
167 /* SQC range 0 */
168 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
169 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
170 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
171 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
172 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
174 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
175 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
176 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
177 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
178 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
179 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
180 /* SQC range 1 */
181 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
182 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
183 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
184 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
185 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
186 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
187 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
188 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
189 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
190 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
191 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
192 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
193 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
194 /* SQC range 2 */
195 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
196 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
197 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
198 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
199 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
200 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
201 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
202 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
203 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
204 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
205 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
206 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
207 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
208 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
209 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
210 /* TA */
211 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
212 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
213 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
214 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
215 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
216 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
217 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
218 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
219 /* TCA */
220 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
221 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
222 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
223 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
224 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
225 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
226 /* TCC (5 sub-ranges) */
227 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
228 /* TCC range 0 */
229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
230 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
231 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
232 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
233 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
234 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
235 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
236 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
237 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
238 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
239 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
240 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
241 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
242 /* TCC range 1 */
243 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
244 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
245 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
246 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
247 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
248 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
249 /* TCC range 2 */
250 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
251 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
252 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
253 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
254 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
255 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
256 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
257 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
258 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
259 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
260 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
261 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
262 /* TCC range 3 */
263 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
264 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
265 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
266 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
267 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
268 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
269 /* TCC range 4 */
270 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
271 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
272 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
273 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
274 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
275 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
276 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
277 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
278 /* TCI */
279 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
280 /* TCP */
281 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
282 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
283 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
284 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
285 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
286 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
287 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
288 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
289 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
290 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
291 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
292 /* TD */
293 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
294 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
295 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
296 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
297 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
298 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
299 /* EA (3 sub-ranges) */
300 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
301 /* EA range 0 */
302 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
303 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
304 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
305 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
306 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
307 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
308 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
309 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
310 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
311 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
312 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
313 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
314 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
315 /* EA range 1 */
316 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
317 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
318 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
319 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
320 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
321 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
322 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
323 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
324 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
325 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
326 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
327 /* EA range 2 */
328 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
329 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
330 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
331 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
332 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
333 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
334 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
335 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
336 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
337 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
338 /* UTC VM L2 bank */
339 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
340 /* UTC VM walker */
341 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
342 /* UTC ATC L2 2MB cache */
343 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
344 /* UTC ATC L2 4KB cache */
345 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
346 AMDGPU_RAS_BLOCK__GFX_MAX
347};
348
349enum amdgpu_ras_error_type {
350 AMDGPU_RAS_ERROR__NONE = 0,
351 AMDGPU_RAS_ERROR__PARITY = 1,
352 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
353 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
354 AMDGPU_RAS_ERROR__POISON = 8,
355};
356
357enum amdgpu_ras_ret {
358 AMDGPU_RAS_SUCCESS = 0,
359 AMDGPU_RAS_FAIL,
360 AMDGPU_RAS_UE,
361 AMDGPU_RAS_CE,
362 AMDGPU_RAS_PT,
363};
364
365enum amdgpu_ras_error_query_mode {
366 AMDGPU_RAS_INVALID_ERROR_QUERY = 0,
367 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1,
368 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2,
369 AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY = 3,
370};
371
372/* ras error status reisger fields */
373#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
374#define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
375#define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
376#define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
377#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
378#define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
379#define ERR_STATUS__ERR_CNT__SHIFT 0x17
380#define ERR_STATUS__ERR_CNT_MASK 0x03800000L
381
382#define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
383 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
384
385#define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
386 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
387
388#define AMDGPU_RAS_ERR_INFO_VALID (1 << 0)
389#define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1)
390#define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2)
391
392#define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0)
393#define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1)
394
395struct amdgpu_ras_err_status_reg_entry {
396 uint32_t hwip;
397 uint32_t ip_inst;
398 uint32_t seg_lo;
399 uint32_t reg_lo;
400 uint32_t seg_hi;
401 uint32_t reg_hi;
402 uint32_t reg_inst;
403 uint32_t flags;
404 const char *block_name;
405};
406
407struct amdgpu_ras_memory_id_entry {
408 uint32_t memory_id;
409 const char *name;
410};
411
412struct ras_common_if {
413 enum amdgpu_ras_block block;
414 enum amdgpu_ras_error_type type;
415 uint32_t sub_block_index;
416 char name[32];
417};
418
419#define MAX_UMC_CHANNEL_NUM 32
420
421struct ecc_info_per_ch {
422 uint16_t ce_count_lo_chip;
423 uint16_t ce_count_hi_chip;
424 uint64_t mca_umc_status;
425 uint64_t mca_umc_addr;
426 uint64_t mca_ceumc_addr;
427};
428
429struct umc_ecc_info {
430 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
431
432 /* Determine smu ecctable whether support
433 * record correctable error address
434 */
435 int record_ce_addr_supported;
436};
437
438enum ras_event_type {
439 RAS_EVENT_TYPE_INVALID = 0,
440 RAS_EVENT_TYPE_FATAL,
441 RAS_EVENT_TYPE_POISON_CREATION,
442 RAS_EVENT_TYPE_POISON_CONSUMPTION,
443 RAS_EVENT_TYPE_COUNT,
444};
445
446struct ras_event_state {
447 u64 last_seqno;
448 atomic64_t count;
449};
450
451struct ras_event_manager {
452 atomic64_t seqno;
453 struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT];
454};
455
456struct ras_event_id {
457 enum ras_event_type type;
458 u64 event_id;
459};
460
461struct ras_query_context {
462 struct ras_event_id evid;
463};
464
465typedef int (*pasid_notify)(struct amdgpu_device *adev,
466 uint16_t pasid, void *data);
467
468struct ras_err_pages {
469 uint32_t count;
470 uint64_t *pfn;
471};
472
473struct ras_ecc_err {
474 uint64_t status;
475 uint64_t ipid;
476 uint64_t addr;
477 uint64_t pa_pfn;
478 /* save global channel index across all UMC instances */
479 uint32_t channel_idx;
480 struct ras_err_pages err_pages;
481};
482
483struct ras_ecc_log_info {
484 struct mutex lock;
485 struct radix_tree_root de_page_tree;
486};
487
488struct ras_critical_region {
489 struct list_head node;
490 struct amdgpu_bo *bo;
491 uint64_t start;
492 uint64_t size;
493};
494
495struct amdgpu_ras {
496 void *ras_mgr;
497 /* ras infrastructure */
498 /* for ras itself. */
499 uint32_t features;
500 uint32_t schema;
501 struct list_head head;
502 /* sysfs */
503 struct device_attribute features_attr;
504 struct device_attribute version_attr;
505 struct device_attribute schema_attr;
506 struct device_attribute event_state_attr;
507 struct bin_attribute badpages_attr;
508 struct dentry *de_ras_eeprom_table;
509 /* block array */
510 struct ras_manager *objs;
511
512 /* gpu recovery */
513 struct work_struct recovery_work;
514 atomic_t in_recovery;
515 struct amdgpu_device *adev;
516 /* error handler data */
517 struct ras_err_handler_data *eh_data;
518 struct mutex recovery_lock;
519
520 uint32_t flags;
521 bool reboot;
522 struct amdgpu_ras_eeprom_control eeprom_control;
523
524 bool error_query_ready;
525
526 /* bad page count threshold */
527 uint32_t bad_page_cnt_threshold;
528
529 /* disable ras error count harvest in recovery */
530 bool disable_ras_err_cnt_harvest;
531
532 /* is poison mode supported */
533 bool poison_supported;
534
535 /* RAS count errors delayed work */
536 struct delayed_work ras_counte_delay_work;
537 atomic_t ras_ue_count;
538 atomic_t ras_ce_count;
539
540 /* record umc error info queried from smu */
541 struct umc_ecc_info umc_ecc;
542
543 /* Indicates smu whether need update bad channel info */
544 bool update_channel_flag;
545 /* Record status of smu mca debug mode */
546 bool is_mca_debug_mode;
547 bool is_rma;
548
549 /* Record special requirements of gpu reset caller */
550 uint32_t gpu_reset_flags;
551
552 struct mutex page_retirement_lock;
553 struct mutex page_rsv_lock;
554 struct ras_ecc_log_info umc_ecc_log;
555
556 /* ras errors detected */
557 unsigned long ras_err_state;
558
559 /* RAS event manager */
560 struct ras_event_manager __event_mgr;
561 struct ras_event_manager *event_mgr;
562
563 uint64_t reserved_pages_in_bytes;
564
565 pid_t init_task_pid;
566 char init_task_comm[TASK_COMM_LEN];
567
568 int bad_page_num;
569
570 struct list_head critical_region_head;
571 struct mutex critical_region_lock;
572
573 /* Disable/Enable uniras switch */
574 bool uniras_enabled;
575};
576
577struct ras_fs_data {
578 char sysfs_name[48];
579 char debugfs_name[32];
580};
581
582struct ras_err_info {
583 struct amdgpu_smuio_mcm_config_info mcm_info;
584 u64 ce_count;
585 u64 ue_count;
586 u64 de_count;
587};
588
589struct ras_err_node {
590 struct list_head node;
591 struct ras_err_info err_info;
592};
593
594struct ras_err_data {
595 unsigned long ue_count;
596 unsigned long ce_count;
597 unsigned long de_count;
598 unsigned long err_addr_cnt;
599 struct eeprom_table_record *err_addr;
600 unsigned long err_addr_len;
601 u32 err_list_count;
602 struct list_head err_node_list;
603};
604
605#define for_each_ras_error(err_node, err_data) \
606 list_for_each_entry(err_node, &(err_data)->err_node_list, node)
607
608struct ras_err_handler_data {
609 /* point to bad page records array */
610 struct eeprom_table_record *bps;
611 /* the count of entries */
612 int count;
613 int count_saved;
614 /* the space can place new entries */
615 int space_left;
616};
617
618typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
619 void *err_data,
620 struct amdgpu_iv_entry *entry);
621
622struct ras_ih_data {
623 /* interrupt bottom half */
624 struct work_struct ih_work;
625 int inuse;
626 /* IP callback */
627 ras_ih_cb cb;
628 /* full of entries */
629 unsigned char *ring;
630 unsigned int ring_size;
631 unsigned int element_size;
632 unsigned int aligned_element_size;
633 unsigned int rptr;
634 unsigned int wptr;
635};
636
637struct ras_manager {
638 struct ras_common_if head;
639 /* reference count */
640 int use;
641 /* ras block link */
642 struct list_head node;
643 /* the device */
644 struct amdgpu_device *adev;
645 /* sysfs */
646 struct device_attribute sysfs_attr;
647 int attr_inuse;
648
649 /* fs node name */
650 struct ras_fs_data fs_data;
651
652 /* IH data */
653 struct ras_ih_data ih_data;
654
655 struct ras_err_data err_data;
656};
657
658struct ras_badpage {
659 unsigned int bp;
660 unsigned int size;
661 unsigned int flags;
662};
663
664/* interfaces for IP */
665struct ras_fs_if {
666 struct ras_common_if head;
667 const char* sysfs_name;
668 char debugfs_name[32];
669};
670
671struct ras_query_if {
672 struct ras_common_if head;
673 unsigned long ue_count;
674 unsigned long ce_count;
675 unsigned long de_count;
676};
677
678struct ras_inject_if {
679 struct ras_common_if head;
680 uint64_t address;
681 uint64_t value;
682 uint32_t instance_mask;
683};
684
685struct ras_cure_if {
686 struct ras_common_if head;
687 uint64_t address;
688};
689
690struct ras_ih_if {
691 struct ras_common_if head;
692 ras_ih_cb cb;
693};
694
695struct ras_dispatch_if {
696 struct ras_common_if head;
697 struct amdgpu_iv_entry *entry;
698};
699
700struct ras_debug_if {
701 union {
702 struct ras_common_if head;
703 struct ras_inject_if inject;
704 };
705 int op;
706};
707
708struct amdgpu_ras_block_object {
709 struct ras_common_if ras_comm;
710
711 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
712 enum amdgpu_ras_block block, uint32_t sub_block_index);
713 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
714 void (*ras_suspend)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
715 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
716 ras_ih_cb ras_cb;
717 const struct amdgpu_ras_block_hw_ops *hw_ops;
718};
719
720struct amdgpu_ras_block_hw_ops {
721 int (*ras_error_inject)(struct amdgpu_device *adev,
722 void *inject_if, uint32_t instance_mask);
723 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
724 void (*query_ras_error_status)(struct amdgpu_device *adev);
725 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
726 void (*reset_ras_error_count)(struct amdgpu_device *adev);
727 void (*reset_ras_error_status)(struct amdgpu_device *adev);
728 bool (*query_poison_status)(struct amdgpu_device *adev);
729 bool (*handle_poison_consumption)(struct amdgpu_device *adev);
730};
731
732/* work flow
733 * vbios
734 * 1: ras feature enable (enabled by default)
735 * psp
736 * 2: ras framework init (in ip_init)
737 * IP
738 * 3: IH add
739 * 4: debugfs/sysfs create
740 * 5: query/inject
741 * 6: debugfs/sysfs remove
742 * 7: IH remove
743 * 8: feature disable
744 */
745
746int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev);
747int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info);
748
749void amdgpu_ras_resume(struct amdgpu_device *adev);
750void amdgpu_ras_suspend(struct amdgpu_device *adev);
751
752int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
753 unsigned long *ce_count,
754 unsigned long *ue_count,
755 struct ras_query_if *query_info);
756
757/* error handling functions */
758int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
759 struct eeprom_table_record *bps, int pages, bool from_rom);
760
761int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
762 unsigned long *new_cnt);
763
764static inline enum ta_ras_block
765amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
766 switch (block) {
767 case AMDGPU_RAS_BLOCK__UMC:
768 return TA_RAS_BLOCK__UMC;
769 case AMDGPU_RAS_BLOCK__SDMA:
770 return TA_RAS_BLOCK__SDMA;
771 case AMDGPU_RAS_BLOCK__GFX:
772 return TA_RAS_BLOCK__GFX;
773 case AMDGPU_RAS_BLOCK__MMHUB:
774 return TA_RAS_BLOCK__MMHUB;
775 case AMDGPU_RAS_BLOCK__ATHUB:
776 return TA_RAS_BLOCK__ATHUB;
777 case AMDGPU_RAS_BLOCK__PCIE_BIF:
778 return TA_RAS_BLOCK__PCIE_BIF;
779 case AMDGPU_RAS_BLOCK__HDP:
780 return TA_RAS_BLOCK__HDP;
781 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
782 return TA_RAS_BLOCK__XGMI_WAFL;
783 case AMDGPU_RAS_BLOCK__DF:
784 return TA_RAS_BLOCK__DF;
785 case AMDGPU_RAS_BLOCK__SMN:
786 return TA_RAS_BLOCK__SMN;
787 case AMDGPU_RAS_BLOCK__SEM:
788 return TA_RAS_BLOCK__SEM;
789 case AMDGPU_RAS_BLOCK__MP0:
790 return TA_RAS_BLOCK__MP0;
791 case AMDGPU_RAS_BLOCK__MP1:
792 return TA_RAS_BLOCK__MP1;
793 case AMDGPU_RAS_BLOCK__FUSE:
794 return TA_RAS_BLOCK__FUSE;
795 case AMDGPU_RAS_BLOCK__MCA:
796 return TA_RAS_BLOCK__MCA;
797 case AMDGPU_RAS_BLOCK__VCN:
798 return TA_RAS_BLOCK__VCN;
799 case AMDGPU_RAS_BLOCK__JPEG:
800 return TA_RAS_BLOCK__JPEG;
801 case AMDGPU_RAS_BLOCK__IH:
802 return TA_RAS_BLOCK__IH;
803 case AMDGPU_RAS_BLOCK__MPIO:
804 return TA_RAS_BLOCK__MPIO;
805 case AMDGPU_RAS_BLOCK__MMSCH:
806 return TA_RAS_BLOCK__MMSCH;
807 default:
808 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
809 return TA_RAS_BLOCK__UMC;
810 }
811}
812
813static inline enum ta_ras_error_type
814amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
815 switch (error) {
816 case AMDGPU_RAS_ERROR__NONE:
817 return TA_RAS_ERROR__NONE;
818 case AMDGPU_RAS_ERROR__PARITY:
819 return TA_RAS_ERROR__PARITY;
820 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
821 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
822 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
823 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
824 case AMDGPU_RAS_ERROR__POISON:
825 return TA_RAS_ERROR__POISON;
826 default:
827 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
828 return TA_RAS_ERROR__NONE;
829 }
830}
831
832/* called in ip_init and ip_fini */
833int amdgpu_ras_init(struct amdgpu_device *adev);
834int amdgpu_ras_late_init(struct amdgpu_device *adev);
835int amdgpu_ras_fini(struct amdgpu_device *adev);
836int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
837
838int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
839 struct ras_common_if *ras_block);
840
841void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
842 struct ras_common_if *ras_block);
843
844int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
845 struct ras_common_if *head, bool enable);
846
847int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
848 struct ras_common_if *head, bool enable);
849
850int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
851 struct ras_common_if *head);
852
853int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
854 struct ras_common_if *head);
855
856void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
857
858int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
859 struct ras_query_if *info);
860
861int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
862 enum amdgpu_ras_block block);
863int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
864 enum amdgpu_ras_block block);
865
866int amdgpu_ras_error_inject(struct amdgpu_device *adev,
867 struct ras_inject_if *info);
868
869int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
870 struct ras_common_if *head);
871
872int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
873 struct ras_common_if *head);
874
875int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
876 struct ras_dispatch_if *info);
877
878struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
879 struct ras_common_if *head);
880
881extern atomic_t amdgpu_ras_in_intr;
882
883static inline bool amdgpu_ras_intr_triggered(void)
884{
885 return !!atomic_read(&amdgpu_ras_in_intr);
886}
887
888static inline void amdgpu_ras_intr_cleared(void)
889{
890 atomic_set(&amdgpu_ras_in_intr, 0);
891}
892
893int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
894
895void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
896
897bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
898
899void amdgpu_release_ras_context(struct amdgpu_device *adev);
900
901int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
902
903const char *get_ras_block_str(struct ras_common_if *ras_block);
904
905bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
906
907int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
908
909int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
910
911struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
912
913int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
914
915int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
916bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev);
917bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
918 unsigned int *mode);
919
920int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
921 struct amdgpu_ras_block_object *ras_block_obj);
922void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
923void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
924bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
925 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
926 uint32_t instance,
927 uint32_t *memory_id);
928bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
929 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
930 uint32_t instance,
931 unsigned long *err_cnt);
932void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
933 const struct amdgpu_ras_err_status_reg_entry *reg_list,
934 uint32_t reg_list_size,
935 const struct amdgpu_ras_memory_id_entry *mem_list,
936 uint32_t mem_list_size,
937 uint32_t instance,
938 uint32_t err_type,
939 unsigned long *err_count);
940void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
941 const struct amdgpu_ras_err_status_reg_entry *reg_list,
942 uint32_t reg_list_size,
943 uint32_t instance);
944
945int amdgpu_ras_error_data_init(struct ras_err_data *err_data);
946void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);
947int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
948 struct amdgpu_smuio_mcm_config_info *mcm_info,
949 u64 count);
950int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
951 struct amdgpu_smuio_mcm_config_info *mcm_info,
952 u64 count);
953void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);
954
955void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
956bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
957void amdgpu_ras_set_err_poison(struct amdgpu_device *adev,
958 enum amdgpu_ras_block block);
959void amdgpu_ras_clear_err_state(struct amdgpu_device *adev);
960bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block);
961
962u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);
963int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,
964 const void *caller);
965
966int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);
967
968int amdgpu_ras_add_critical_region(struct amdgpu_device *adev, struct amdgpu_bo *bo);
969bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr);
970
971bool amdgpu_ras_in_recovery(struct amdgpu_device *adev);
972
973__printf(3, 4)
974void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
975 const char *fmt, ...);
976
977bool amdgpu_ras_is_rma(struct amdgpu_device *adev);
978
979void amdgpu_ras_pre_reset(struct amdgpu_device *adev,
980 struct list_head *device_list);
981void amdgpu_ras_post_reset(struct amdgpu_device *adev,
982 struct list_head *device_list);
983int amdgpu_ras_resume_after_reset(struct amdgpu_device *adev);
984#endif