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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _AMDGPU_RAS_EEPROM_H
25#define _AMDGPU_RAS_EEPROM_H
26
27#include <linux/i2c.h>
28
29#define RAS_TABLE_VER_V1 0x00010000
30#define RAS_TABLE_VER_V2_1 0x00021000
31#define RAS_TABLE_VER_V3 0x00030000
32
33struct amdgpu_device;
34
35enum amdgpu_ras_gpu_health_status {
36 GPU_HEALTH_USABLE = 0,
37 GPU_RETIRED__ECC_REACH_THRESHOLD = 2,
38};
39
40enum amdgpu_ras_eeprom_err_type {
41 AMDGPU_RAS_EEPROM_ERR_NA,
42 AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
43 AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE,
44 AMDGPU_RAS_EEPROM_ERR_COUNT,
45};
46
47struct amdgpu_ras_eeprom_table_header {
48 uint32_t header;
49 uint32_t version;
50 uint32_t first_rec_offset;
51 uint32_t tbl_size;
52 uint32_t checksum;
53} __packed;
54
55struct amdgpu_ras_eeprom_table_ras_info {
56 u8 rma_status;
57 u8 health_percent;
58 u16 ecc_page_threshold;
59 u32 padding[64 - 1];
60} __packed;
61
62struct amdgpu_ras_eeprom_control {
63 struct amdgpu_ras_eeprom_table_header tbl_hdr;
64
65 struct amdgpu_ras_eeprom_table_ras_info tbl_rai;
66
67 /* Base I2C EEPPROM 19-bit memory address,
68 * where the table is located. For more information,
69 * see top of amdgpu_eeprom.c.
70 */
71 u32 i2c_address;
72
73 /* The byte offset off of @i2c_address
74 * where the table header is found,
75 * and where the records start--always
76 * right after the header.
77 */
78 u32 ras_header_offset;
79 u32 ras_info_offset;
80 u32 ras_record_offset;
81
82 /* Number of records in the table.
83 */
84 u32 ras_num_recs;
85
86 /* the bad page number is ras_num_recs or
87 * ras_num_recs * umc.retire_unit
88 */
89 u32 ras_num_bad_pages;
90
91 /* Number of records store mca address */
92 u32 ras_num_mca_recs;
93
94 /* Number of records store physical address */
95 u32 ras_num_pa_recs;
96
97 /* First record index to read, 0-based.
98 * Range is [0, num_recs-1]. This is
99 * an absolute index, starting right after
100 * the table header.
101 */
102 u32 ras_fri;
103
104 /* Maximum possible number of records
105 * we could store, i.e. the maximum capacity
106 * of the table.
107 */
108 u32 ras_max_record_count;
109
110 /* Protect table access via this mutex.
111 */
112 struct mutex ras_tbl_mutex;
113
114 /* Record channel info which occurred bad pages
115 */
116 u32 bad_channel_bitmap;
117
118 bool is_eeprom_valid;
119};
120
121/*
122 * Represents single table record. Packed to be easily serialized into byte
123 * stream.
124 */
125struct eeprom_table_record {
126
127 union {
128 uint64_t address;
129 uint64_t offset;
130 };
131
132 uint64_t retired_page;
133 uint64_t ts;
134
135 enum amdgpu_ras_eeprom_err_type err_type;
136
137 union {
138 unsigned char bank;
139 unsigned char cu;
140 };
141
142 unsigned char mem_channel;
143 unsigned char mcumc_id;
144} __packed;
145
146int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
147
148int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
149
150bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
151
152int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
153 struct eeprom_table_record *records, const u32 num);
154
155int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
156 struct eeprom_table_record *records, const u32 num);
157
158uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control);
159
160void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);
161
162int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control);
163
164void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev);
165
166int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control,
167 struct eeprom_table_record *record, u32 rec_idx,
168 const u32 num);
169
170void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev);
171
172extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
173extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;
174
175#endif // _AMDGPU_RAS_EEPROM_H