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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24#ifndef __AMDGPU_RING_H__
25#define __AMDGPU_RING_H__
26
27#include <drm/amdgpu_drm.h>
28#include <drm/gpu_scheduler.h>
29#include <drm/drm_print.h>
30#include <drm/drm_suballoc.h>
31
32struct amdgpu_device;
33struct amdgpu_ring;
34struct amdgpu_ib;
35struct amdgpu_cs_parser;
36struct amdgpu_job;
37struct amdgpu_vm;
38
39/* max number of rings */
40#define AMDGPU_MAX_RINGS 149
41#define AMDGPU_MAX_HWIP_RINGS 64
42#define AMDGPU_MAX_GFX_RINGS 2
43#define AMDGPU_MAX_SW_GFX_RINGS 2
44#define AMDGPU_MAX_COMPUTE_RINGS 8
45#define AMDGPU_MAX_VCE_RINGS 3
46#define AMDGPU_MAX_UVD_ENC_RINGS 2
47#define AMDGPU_MAX_VPE_RINGS 2
48
49enum amdgpu_ring_priority_level {
50 AMDGPU_RING_PRIO_0,
51 AMDGPU_RING_PRIO_1,
52 AMDGPU_RING_PRIO_DEFAULT = 1,
53 AMDGPU_RING_PRIO_2,
54 AMDGPU_RING_PRIO_MAX
55};
56
57/* some special values for the owner field */
58#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
59#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
60#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
61
62#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
63#define AMDGPU_FENCE_FLAG_INT (1 << 1)
64#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
65
66/* Ensure the execution in case of preemption or reset */
67#define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
68
69#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
70
71enum amdgpu_ring_type {
72 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
73 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
74 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
75 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
76 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
77 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
78 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
79 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
80 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
81 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE,
82 AMDGPU_RING_TYPE_KIQ,
83 AMDGPU_RING_TYPE_MES,
84 AMDGPU_RING_TYPE_UMSCH_MM,
85 AMDGPU_RING_TYPE_CPER,
86 AMDGPU_RING_TYPE_MAX,
87};
88
89enum amdgpu_ib_pool_type {
90 /* Normal submissions to the top of the pipeline. */
91 AMDGPU_IB_POOL_DELAYED,
92 /* Immediate submissions to the bottom of the pipeline. */
93 AMDGPU_IB_POOL_IMMEDIATE,
94 /* Direct submission to the ring buffer during init and reset. */
95 AMDGPU_IB_POOL_DIRECT,
96
97 AMDGPU_IB_POOL_MAX
98};
99
100struct amdgpu_ib {
101 struct drm_suballoc *sa_bo;
102 uint32_t length_dw;
103 uint64_t gpu_addr;
104 uint32_t *ptr;
105 uint32_t flags;
106};
107
108struct amdgpu_sched {
109 u32 num_scheds;
110 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
111};
112
113/*
114 * Fences.
115 */
116struct amdgpu_fence_driver {
117 uint64_t gpu_addr;
118 uint32_t *cpu_addr;
119 /* sync_seq is protected by ring emission lock */
120 uint32_t sync_seq;
121 atomic_t last_seq;
122 bool initialized;
123 struct amdgpu_irq_src *irq_src;
124 unsigned irq_type;
125 struct timer_list fallback_timer;
126 unsigned num_fences_mask;
127 spinlock_t lock;
128 struct dma_fence **fences;
129};
130
131/*
132 * Fences mark an event in the GPUs pipeline and are used
133 * for GPU/CPU synchronization. When the fence is written,
134 * it is expected that all buffers associated with that fence
135 * are no longer in use by the associated ring on the GPU and
136 * that the relevant GPU caches have been flushed.
137 */
138
139struct amdgpu_fence {
140 struct dma_fence base;
141
142 /* RB, DMA, etc. */
143 struct amdgpu_ring *ring;
144 ktime_t start_timestamp;
145
146 /* location and size of the IB */
147 u64 ib_wptr;
148 unsigned int ib_dw_size;
149 unsigned int skip_ib_dw_start_offset;
150 unsigned int skip_ib_dw_end_offset;
151 /* fence context for resets */
152 u64 context;
153 /* idx for ring backups */
154 unsigned int backup_idx;
155};
156
157extern const struct drm_sched_backend_ops amdgpu_sched_ops;
158
159void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
160void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring,
161 struct dma_fence *timedout_fence);
162void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
163 struct amdgpu_fence *guilty_fence);
164
165int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
166int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
167 struct amdgpu_irq_src *irq_src,
168 unsigned irq_type);
169void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
170void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
171int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
172void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
173void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,
174 unsigned int flags);
175int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
176 uint32_t timeout);
177bool amdgpu_fence_process(struct amdgpu_ring *ring);
178int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
179signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
180 uint32_t wait_seq,
181 signed long timeout);
182unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
183
184void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
185
186u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
187void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
188 ktime_t timestamp);
189
190/*
191 * Rings.
192 */
193
194/* provided by hw blocks that expose a ring buffer for commands */
195struct amdgpu_ring_funcs {
196 /**
197 * @type:
198 *
199 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER
200 * use ring buffers. The type field just identifies which component the
201 * ring buffer is associated with.
202 */
203 enum amdgpu_ring_type type;
204 uint32_t align_mask;
205
206 /**
207 * @nop:
208 *
209 * Every block in the amdgpu has no-op instructions (e.g., GFX 10
210 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP,
211 * etc). This field receives the specific no-op for the component
212 * that initializes the ring.
213 */
214 u32 nop;
215 bool support_64bit_ptrs;
216 bool no_user_fence;
217 bool secure_submission_supported;
218
219 /**
220 * @extra_bytes:
221 *
222 * Optional extra space in bytes that is added to the ring size
223 * when allocating the BO that holds the contents of the ring.
224 * This space isn't used for command submission to the ring,
225 * but is just there to satisfy some hardware requirements or
226 * implement workarounds. It's up to the implementation of each
227 * specific ring to initialize this space.
228 */
229 unsigned extra_bytes;
230
231 /* ring read/write ptr handling */
232 u64 (*get_rptr)(struct amdgpu_ring *ring);
233 u64 (*get_wptr)(struct amdgpu_ring *ring);
234 void (*set_wptr)(struct amdgpu_ring *ring);
235 /* validating and patching of IBs */
236 int (*parse_cs)(struct amdgpu_cs_parser *p,
237 struct amdgpu_job *job,
238 struct amdgpu_ib *ib);
239 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
240 struct amdgpu_job *job,
241 struct amdgpu_ib *ib);
242 /* constants to calculate how many DW are needed for an emit */
243 unsigned emit_frame_size;
244 unsigned emit_ib_size;
245 /* command emit functions */
246 void (*emit_ib)(struct amdgpu_ring *ring,
247 struct amdgpu_job *job,
248 struct amdgpu_ib *ib,
249 uint32_t flags);
250 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
251 uint64_t seq, unsigned flags);
252 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
253 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
254 uint64_t pd_addr);
255 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
256 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
257 uint32_t gds_base, uint32_t gds_size,
258 uint32_t gws_base, uint32_t gws_size,
259 uint32_t oa_base, uint32_t oa_size);
260 /* testing functions */
261 int (*test_ring)(struct amdgpu_ring *ring);
262 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
263 /* insert NOP packets */
264 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
265 void (*insert_start)(struct amdgpu_ring *ring);
266 void (*insert_end)(struct amdgpu_ring *ring);
267 /* pad the indirect buffer to the necessary number of dw */
268 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
269 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr);
270 /* note usage for clock and power gating */
271 void (*begin_use)(struct amdgpu_ring *ring);
272 void (*end_use)(struct amdgpu_ring *ring);
273 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
274 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
275 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
276 u64 gds_va, bool init_shadow, int vmid);
277 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
278 uint32_t reg_val_offs);
279 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
280 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
281 uint32_t val, uint32_t mask);
282 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
283 uint32_t reg0, uint32_t reg1,
284 uint32_t ref, uint32_t mask);
285 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
286 bool secure);
287 /* Try to soft recover the ring to make the fence signal */
288 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
289 int (*preempt_ib)(struct amdgpu_ring *ring);
290 void (*emit_mem_sync)(struct amdgpu_ring *ring);
291 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
292 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
293 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
294 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
295 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid,
296 struct amdgpu_fence *timedout_fence);
297 void (*emit_cleaner_shader)(struct amdgpu_ring *ring);
298};
299
300/**
301 * amdgpu_ring - Holds ring information
302 */
303struct amdgpu_ring {
304 struct amdgpu_device *adev;
305 const struct amdgpu_ring_funcs *funcs;
306 struct amdgpu_fence_driver fence_drv;
307 struct drm_gpu_scheduler sched;
308
309 struct amdgpu_bo *ring_obj;
310 uint32_t *ring;
311 /* backups for resets */
312 uint32_t *ring_backup;
313 unsigned int ring_backup_entries_to_copy;
314 bool reemit;
315 struct amdgpu_fence *guilty_fence;
316 unsigned rptr_offs;
317 u64 rptr_gpu_addr;
318 u32 *rptr_cpu_addr;
319
320 /**
321 * @wptr:
322 *
323 * This is part of the Ring buffer implementation and represents the
324 * write pointer. The wptr determines where the host has written.
325 */
326 u64 wptr;
327
328 /**
329 * @wptr_old:
330 *
331 * Before update wptr with the new value, usually the old value is
332 * stored in the wptr_old.
333 */
334 u64 wptr_old;
335 unsigned ring_size;
336
337 /**
338 * @max_dw:
339 *
340 * Maximum number of DWords for ring allocation. This information is
341 * provided at the ring initialization time, and each IP block can
342 * specify a specific value. Check places that invoke
343 * amdgpu_ring_init() to see the maximum size per block.
344 */
345 unsigned max_dw;
346
347 /**
348 * @count_dw:
349 *
350 * This value starts with the maximum amount of DWords supported by the
351 * ring. This value is updated based on the ring manipulation.
352 */
353 int count_dw;
354 uint64_t gpu_addr;
355
356 /**
357 * @ptr_mask:
358 *
359 * Some IPs provide support for 64-bit pointers and others for 32-bit
360 * only; this behavior is component-specific and defined by the field
361 * support_64bit_ptr. If the IP block supports 64-bits, the mask
362 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask.
363 * Notice that this field is used to keep wptr under a valid range.
364 */
365 uint64_t ptr_mask;
366
367 /**
368 * @buf_mask:
369 *
370 * Buffer mask is a value used to keep wptr count under its
371 * thresholding. Buffer mask initialized during the ring buffer
372 * initialization time, and it is defined as (ring_size / 4) -1.
373 */
374 uint32_t buf_mask;
375 u32 idx;
376 u32 xcc_id;
377 u32 xcp_id;
378 u32 me;
379 u32 pipe;
380 u32 queue;
381 struct amdgpu_bo *mqd_obj;
382 uint64_t mqd_gpu_addr;
383 void *mqd_ptr;
384 unsigned mqd_size;
385 uint64_t eop_gpu_addr;
386 u32 doorbell_index;
387 bool use_doorbell;
388 bool use_pollmem;
389 unsigned wptr_offs;
390 u64 wptr_gpu_addr;
391
392 /**
393 * @wptr_cpu_addr:
394 *
395 * This is the CPU address pointer in the writeback slot. This is used
396 * to commit changes to the GPU.
397 */
398 u32 *wptr_cpu_addr;
399 unsigned fence_offs;
400 u64 fence_gpu_addr;
401 u32 *fence_cpu_addr;
402 uint64_t current_ctx;
403 char name[16];
404 u32 trail_seq;
405 unsigned trail_fence_offs;
406 u64 trail_fence_gpu_addr;
407 u32 *trail_fence_cpu_addr;
408 unsigned cond_exe_offs;
409 u64 cond_exe_gpu_addr;
410 u32 *cond_exe_cpu_addr;
411 unsigned int set_q_mode_offs;
412 u32 *set_q_mode_ptr;
413 u64 set_q_mode_token;
414 unsigned vm_hub;
415 unsigned vm_inv_eng;
416 struct dma_fence *vmid_wait;
417 bool has_compute_vm_bug;
418 bool no_scheduler;
419 bool no_user_submission;
420 int hw_prio;
421 unsigned num_hw_submission;
422 atomic_t *sched_score;
423
424 bool is_sw_ring;
425 unsigned int entry_index;
426 /* store the cached rptr to restore after reset */
427 uint64_t cached_rptr;
428};
429
430#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
431#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
432#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
433#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
434#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
435#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
436#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
437#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
438#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
439#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
440#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
441#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
442#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
443#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
444#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
445#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
446#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
447#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
448#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
449#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
450#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
451#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
452#define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))
453#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
454#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
455#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
456#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
457#define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f))
458
459unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
460int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
461void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
462void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
463void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
464void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
465void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
466
467void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
468void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
469void amdgpu_ring_commit(struct amdgpu_ring *ring);
470void amdgpu_ring_undo(struct amdgpu_ring *ring);
471int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
472 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
473 unsigned int irq_type, unsigned int hw_prio,
474 atomic_t *sched_score);
475void amdgpu_ring_fini(struct amdgpu_ring *ring);
476void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
477 uint32_t reg0, uint32_t val0,
478 uint32_t reg1, uint32_t val1);
479bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
480 struct dma_fence *fence);
481
482static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
483 bool cond_exec)
484{
485 *ring->cond_exe_cpu_addr = cond_exec;
486}
487
488static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
489{
490 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1);
491}
492
493static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
494{
495 ring->ring[ring->wptr++ & ring->buf_mask] = v;
496 ring->wptr &= ring->ptr_mask;
497 ring->count_dw--;
498}
499
500static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
501 void *src, int count_dw)
502{
503 unsigned occupied, chunk1, chunk2;
504
505 occupied = ring->wptr & ring->buf_mask;
506 chunk1 = ring->buf_mask + 1 - occupied;
507 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1;
508 chunk2 = count_dw - chunk1;
509 chunk1 <<= 2;
510 chunk2 <<= 2;
511
512 if (chunk1)
513 memcpy(&ring->ring[occupied], src, chunk1);
514
515 if (chunk2) {
516 src += chunk1;
517 memcpy(ring->ring, src, chunk2);
518 }
519
520 ring->wptr += count_dw;
521 ring->wptr &= ring->ptr_mask;
522 ring->count_dw -= count_dw;
523}
524
525static inline unsigned int amdgpu_ring_get_dw_distance(struct amdgpu_ring *ring,
526 u64 start_wptr, u64 end_wptr)
527{
528 unsigned int start = start_wptr & ring->buf_mask;
529 unsigned int end = end_wptr & ring->buf_mask;
530
531 if (end < start)
532 end += ring->ring_size >> 2;
533 return end - start;
534}
535
536/**
537 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
538 * @ring: amdgpu_ring structure
539 * @offset: offset returned by amdgpu_ring_init_cond_exec
540 *
541 * Calculate the dw count and patch it into a cond_exec command.
542 */
543static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring,
544 unsigned int offset)
545{
546 if (!ring->funcs->init_cond_exec)
547 return;
548
549 WARN_ON(offset > ring->buf_mask);
550 WARN_ON(ring->ring[offset] != 0);
551
552 ring->ring[offset] = amdgpu_ring_get_dw_distance(ring, offset, ring->wptr - 1);
553}
554
555int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
556
557void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
558 struct amdgpu_ring *ring);
559
560int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
561
562static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, uint32_t idx)
563{
564 if (idx < ib->length_dw)
565 return ib->ptr[idx];
566 return 0;
567}
568
569static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, uint32_t idx,
570 uint32_t value)
571{
572 if (idx < ib->length_dw)
573 ib->ptr[idx] = value;
574}
575
576int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
577 unsigned size,
578 enum amdgpu_ib_pool_type pool,
579 struct amdgpu_ib *ib);
580void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f);
581int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
582 struct amdgpu_ib *ibs, struct amdgpu_job *job,
583 struct dma_fence **f);
584int amdgpu_ib_pool_init(struct amdgpu_device *adev);
585void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
586gfp_t amdgpu_ib_pool_gfp_flags(struct amdgpu_device *adev,
587 enum amdgpu_ib_pool_type type);
588int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
589bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);
590void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
591 struct amdgpu_fence *guilty_fence);
592struct amdgpu_fence *
593amdgpu_ring_find_guilty_fence(struct amdgpu_ring *ring);
594void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
595 struct amdgpu_fence *guilty_fence);
596int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
597 struct amdgpu_fence *guilty_fence);
598void amdgpu_multi_ring_reset_helper_begin(const u32 ring_type_mask,
599 struct amdgpu_ring *guilty_ring,
600 struct amdgpu_fence *guilty_fence);
601int amdgpu_multi_ring_reset_helper_end(const u32 ring_type_mask,
602 struct amdgpu_ring *guilty_ring, int ret);
603bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,
604 u32 reset_type);
605#endif