| 1 | |
| 2 | * Copyright 2019 Advanced Micro Devices, Inc.
|
| 3 | *
|
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
|
| 5 | * copy of this software and associated documentation files (the "Software"),
|
| 6 | * to deal in the Software without restriction, including without limitation
|
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
| 8 | * and/or sell copies of the Software, and to permit persons to whom the
|
| 9 | * Software is furnished to do so, subject to the following conditions:
|
| 10 | *
|
| 11 | * The above copyright notice and this permission notice shall be included in
|
| 12 | * all copies or substantial portions of the Software.
|
| 13 | *
|
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
| 20 | * OTHER DEALINGS IN THE SOFTWARE.
|
| 21 | *
|
| 22 |
|
| 23 | #ifndef __AMDGPU_SOCBB_H__
|
| 24 | #define __AMDGPU_SOCBB_H__
|
| 25 |
|
| 26 | struct gpu_info_voltage_scaling_v1_0 {
|
| 27 | uint32_t state;
|
| 28 | uint32_t dscclk_mhz;
|
| 29 | uint32_t dcfclk_mhz;
|
| 30 | uint32_t socclk_mhz;
|
| 31 | uint32_t dram_speed_mts;
|
| 32 | uint32_t fabricclk_mhz;
|
| 33 | uint32_t dispclk_mhz;
|
| 34 | uint32_t phyclk_mhz;
|
| 35 | uint32_t dppclk_mhz;
|
| 36 | };
|
| 37 |
|
| 38 | struct gpu_info_soc_bounding_box_v1_0 {
|
| 39 | uint32_t sr_exit_time_us;
|
| 40 | uint32_t sr_enter_plus_exit_time_us;
|
| 41 | uint32_t urgent_latency_us;
|
| 42 | uint32_t urgent_latency_pixel_data_only_us;
|
| 43 | uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
|
| 44 | uint32_t urgent_latency_vm_data_only_us;
|
| 45 | uint32_t writeback_latency_us;
|
| 46 | uint32_t ideal_dram_bw_after_urgent_percent;
|
| 47 | uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; |
| 48 | uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
|
| 49 | uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
|
| 50 | uint32_t max_avg_sdp_bw_use_normal_percent;
|
| 51 | uint32_t max_avg_dram_bw_use_normal_percent;
|
| 52 | uint32_t max_request_size_bytes;
|
| 53 | uint32_t downspread_percent;
|
| 54 | uint32_t dram_page_open_time_ns;
|
| 55 | uint32_t dram_rw_turnaround_time_ns;
|
| 56 | uint32_t dram_return_buffer_per_channel_bytes;
|
| 57 | uint32_t dram_channel_width_bytes;
|
| 58 | uint32_t fabric_datapath_to_dcn_data_return_bytes;
|
| 59 | uint32_t dcn_downspread_percent;
|
| 60 | uint32_t dispclk_dppclk_vco_speed_mhz;
|
| 61 | uint32_t dfs_vco_period_ps;
|
| 62 | uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
|
| 63 | uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
|
| 64 | uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes;
|
| 65 | uint32_t round_trip_ping_latency_dcfclk_cycles;
|
| 66 | uint32_t urgent_out_of_order_return_per_channel_bytes;
|
| 67 | uint32_t channel_interleave_bytes;
|
| 68 | uint32_t num_banks;
|
| 69 | uint32_t num_chans;
|
| 70 | uint32_t vmm_page_size_bytes;
|
| 71 | uint32_t dram_clock_change_latency_us;
|
| 72 | uint32_t writeback_dram_clock_change_latency_us;
|
| 73 | uint32_t return_bus_width_bytes;
|
| 74 | uint32_t voltage_override;
|
| 75 | uint32_t xfc_bus_transport_time_us;
|
| 76 | uint32_t xfc_xbuf_latency_tolerance_us;
|
| 77 | uint32_t use_urgent_burst_bw;
|
| 78 | uint32_t num_states;
|
| 79 | struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
|
| 80 | };
|
| 81 |
|
| 82 | #endif
|