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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#if !defined(_AMDGPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
25#define _AMDGPU_TRACE_H_
26
27#include <linux/stringify.h>
28#include <linux/types.h>
29#include <linux/tracepoint.h>
30
31#include "amdgpu_userq_fence.h"
32
33#undef TRACE_SYSTEM
34#define TRACE_SYSTEM amdgpu
35#define TRACE_INCLUDE_FILE amdgpu_trace
36
37#define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
38 job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
39
40TRACE_EVENT(amdgpu_device_rreg,
41 TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
42 TP_ARGS(did, reg, value),
43 TP_STRUCT__entry(
44 __field(unsigned, did)
45 __field(uint32_t, reg)
46 __field(uint32_t, value)
47 ),
48 TP_fast_assign(
49 __entry->did = did;
50 __entry->reg = reg;
51 __entry->value = value;
52 ),
53 TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
54 (unsigned long)__entry->did,
55 (unsigned long)__entry->reg,
56 (unsigned long)__entry->value)
57);
58
59TRACE_EVENT(amdgpu_device_wreg,
60 TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
61 TP_ARGS(did, reg, value),
62 TP_STRUCT__entry(
63 __field(unsigned, did)
64 __field(uint32_t, reg)
65 __field(uint32_t, value)
66 ),
67 TP_fast_assign(
68 __entry->did = did;
69 __entry->reg = reg;
70 __entry->value = value;
71 ),
72 TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
73 (unsigned long)__entry->did,
74 (unsigned long)__entry->reg,
75 (unsigned long)__entry->value)
76);
77
78TRACE_EVENT(amdgpu_iv,
79 TP_PROTO(unsigned ih, struct amdgpu_iv_entry *iv),
80 TP_ARGS(ih, iv),
81 TP_STRUCT__entry(
82 __field(unsigned, ih)
83 __field(unsigned, client_id)
84 __field(unsigned, src_id)
85 __field(unsigned, ring_id)
86 __field(unsigned, vmid)
87 __field(unsigned, vmid_src)
88 __field(uint64_t, timestamp)
89 __field(unsigned, timestamp_src)
90 __field(unsigned, pasid)
91 __array(unsigned, src_data, 4)
92 ),
93 TP_fast_assign(
94 __entry->ih = ih;
95 __entry->client_id = iv->client_id;
96 __entry->src_id = iv->src_id;
97 __entry->ring_id = iv->ring_id;
98 __entry->vmid = iv->vmid;
99 __entry->vmid_src = iv->vmid_src;
100 __entry->timestamp = iv->timestamp;
101 __entry->timestamp_src = iv->timestamp_src;
102 __entry->pasid = iv->pasid;
103 __entry->src_data[0] = iv->src_data[0];
104 __entry->src_data[1] = iv->src_data[1];
105 __entry->src_data[2] = iv->src_data[2];
106 __entry->src_data[3] = iv->src_data[3];
107 ),
108 TP_printk("ih:%u client_id:%u src_id:%u ring:%u vmid:%u "
109 "timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
110 __entry->ih, __entry->client_id, __entry->src_id,
111 __entry->ring_id, __entry->vmid,
112 __entry->timestamp, __entry->pasid,
113 __entry->src_data[0], __entry->src_data[1],
114 __entry->src_data[2], __entry->src_data[3])
115);
116
117
118TRACE_EVENT(amdgpu_bo_create,
119 TP_PROTO(struct amdgpu_bo *bo),
120 TP_ARGS(bo),
121 TP_STRUCT__entry(
122 __field(struct amdgpu_bo *, bo)
123 __field(u32, pages)
124 __field(u32, type)
125 __field(u32, prefer)
126 __field(u32, allow)
127 __field(u32, visible)
128 ),
129
130 TP_fast_assign(
131 __entry->bo = bo;
132 __entry->pages = PFN_UP(bo->tbo.resource->size);
133 __entry->type = bo->tbo.resource->mem_type;
134 __entry->prefer = bo->preferred_domains;
135 __entry->allow = bo->allowed_domains;
136 __entry->visible = bo->flags;
137 ),
138
139 TP_printk("bo=%p, pages=%u, type=%d, preferred=%d, allowed=%d, visible=%d",
140 __entry->bo, __entry->pages, __entry->type,
141 __entry->prefer, __entry->allow, __entry->visible)
142);
143
144TRACE_EVENT(amdgpu_cs,
145 TP_PROTO(struct amdgpu_cs_parser *p,
146 struct amdgpu_job *job,
147 struct amdgpu_ib *ib),
148 TP_ARGS(p, job, ib),
149 TP_STRUCT__entry(
150 __field(struct amdgpu_bo_list *, bo_list)
151 __field(u32, ring)
152 __field(u32, dw)
153 __field(u32, fences)
154 ),
155
156 TP_fast_assign(
157 __entry->bo_list = p->bo_list;
158 __entry->ring = to_amdgpu_ring(job->base.entity->rq->sched)->idx;
159 __entry->dw = ib->length_dw;
160 __entry->fences = amdgpu_fence_count_emitted(
161 to_amdgpu_ring(job->base.entity->rq->sched));
162 ),
163 TP_printk("bo_list=%p, ring=%u, dw=%u, fences=%u",
164 __entry->bo_list, __entry->ring, __entry->dw,
165 __entry->fences)
166);
167
168TRACE_EVENT(amdgpu_cs_ioctl,
169 TP_PROTO(struct amdgpu_job *job),
170 TP_ARGS(job),
171 TP_STRUCT__entry(
172 __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
173 __field(u64, context)
174 __field(u64, seqno)
175 __field(struct dma_fence *, fence)
176 __string(ring, to_amdgpu_ring(job->base.sched)->name)
177 __field(u32, num_ibs)
178 ),
179
180 TP_fast_assign(
181 __assign_str(timeline);
182 __entry->context = job->base.s_fence->finished.context;
183 __entry->seqno = job->base.s_fence->finished.seqno;
184 __assign_str(ring);
185 __entry->num_ibs = job->num_ibs;
186 ),
187 TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u",
188 __get_str(timeline), __entry->context,
189 __entry->seqno, __get_str(ring), __entry->num_ibs)
190);
191
192TRACE_EVENT(amdgpu_sched_run_job,
193 TP_PROTO(struct amdgpu_job *job),
194 TP_ARGS(job),
195 TP_STRUCT__entry(
196 __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
197 __field(u64, context)
198 __field(u64, seqno)
199 __string(ring, to_amdgpu_ring(job->base.sched)->name)
200 __field(u32, num_ibs)
201 ),
202
203 TP_fast_assign(
204 __assign_str(timeline);
205 __entry->context = job->base.s_fence->finished.context;
206 __entry->seqno = job->base.s_fence->finished.seqno;
207 __assign_str(ring);
208 __entry->num_ibs = job->num_ibs;
209 ),
210 TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u",
211 __get_str(timeline), __entry->context,
212 __entry->seqno, __get_str(ring), __entry->num_ibs)
213);
214
215
216TRACE_EVENT(amdgpu_vm_grab_id,
217 TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
218 struct amdgpu_job *job),
219 TP_ARGS(vm, ring, job),
220 TP_STRUCT__entry(
221 __field(u32, pasid)
222 __string(ring, ring->name)
223 __field(u32, ring)
224 __field(u32, vmid)
225 __field(u32, vm_hub)
226 __field(u64, pd_addr)
227 __field(u32, needs_flush)
228 ),
229
230 TP_fast_assign(
231 __entry->pasid = vm->pasid;
232 __assign_str(ring);
233 __entry->vmid = job->vmid;
234 __entry->vm_hub = ring->vm_hub,
235 __entry->pd_addr = job->vm_pd_addr;
236 __entry->needs_flush = job->vm_needs_flush;
237 ),
238 TP_printk("pasid=%d, ring=%s, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u",
239 __entry->pasid, __get_str(ring), __entry->vmid,
240 __entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
241);
242
243TRACE_EVENT(amdgpu_vm_bo_map,
244 TP_PROTO(struct amdgpu_bo_va *bo_va,
245 struct amdgpu_bo_va_mapping *mapping),
246 TP_ARGS(bo_va, mapping),
247 TP_STRUCT__entry(
248 __field(struct amdgpu_bo *, bo)
249 __field(long, start)
250 __field(long, last)
251 __field(u64, offset)
252 __field(u64, flags)
253 ),
254
255 TP_fast_assign(
256 __entry->bo = bo_va ? bo_va->base.bo : NULL;
257 __entry->start = mapping->start;
258 __entry->last = mapping->last;
259 __entry->offset = mapping->offset;
260 __entry->flags = mapping->flags;
261 ),
262 TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
263 __entry->bo, __entry->start, __entry->last,
264 __entry->offset, __entry->flags)
265);
266
267TRACE_EVENT(amdgpu_vm_bo_unmap,
268 TP_PROTO(struct amdgpu_bo_va *bo_va,
269 struct amdgpu_bo_va_mapping *mapping),
270 TP_ARGS(bo_va, mapping),
271 TP_STRUCT__entry(
272 __field(struct amdgpu_bo *, bo)
273 __field(long, start)
274 __field(long, last)
275 __field(u64, offset)
276 __field(u64, flags)
277 ),
278
279 TP_fast_assign(
280 __entry->bo = bo_va ? bo_va->base.bo : NULL;
281 __entry->start = mapping->start;
282 __entry->last = mapping->last;
283 __entry->offset = mapping->offset;
284 __entry->flags = mapping->flags;
285 ),
286 TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
287 __entry->bo, __entry->start, __entry->last,
288 __entry->offset, __entry->flags)
289);
290
291DECLARE_EVENT_CLASS(amdgpu_vm_mapping,
292 TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
293 TP_ARGS(mapping),
294 TP_STRUCT__entry(
295 __field(u64, soffset)
296 __field(u64, eoffset)
297 __field(u64, flags)
298 ),
299
300 TP_fast_assign(
301 __entry->soffset = mapping->start;
302 __entry->eoffset = mapping->last + 1;
303 __entry->flags = mapping->flags;
304 ),
305 TP_printk("soffs=%010llx, eoffs=%010llx, flags=%llx",
306 __entry->soffset, __entry->eoffset, __entry->flags)
307);
308
309DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_update,
310 TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
311 TP_ARGS(mapping)
312);
313
314DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping,
315 TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
316 TP_ARGS(mapping)
317);
318
319DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs,
320 TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
321 TP_ARGS(mapping)
322);
323
324TRACE_EVENT(amdgpu_vm_update_ptes,
325 TP_PROTO(struct amdgpu_vm_update_params *p,
326 uint64_t start, uint64_t end,
327 unsigned int nptes, uint64_t dst,
328 uint64_t incr, uint64_t flags,
329 pid_t pid, uint64_t vm_ctx),
330 TP_ARGS(p, start, end, nptes, dst, incr, flags, pid, vm_ctx),
331 TP_STRUCT__entry(
332 __field(u64, start)
333 __field(u64, end)
334 __field(u64, flags)
335 __field(unsigned int, nptes)
336 __field(u64, incr)
337 __field(pid_t, pid)
338 __field(u64, vm_ctx)
339 __dynamic_array(u64, dst, nptes)
340 ),
341
342 TP_fast_assign(
343 unsigned int i;
344
345 __entry->start = start;
346 __entry->end = end;
347 __entry->flags = flags;
348 __entry->incr = incr;
349 __entry->nptes = nptes;
350 __entry->pid = pid;
351 __entry->vm_ctx = vm_ctx;
352 for (i = 0; i < nptes; ++i) {
353 u64 addr = p->pages_addr ? amdgpu_vm_map_gart(
354 p->pages_addr, dst) : dst;
355
356 ((u64 *)__get_dynamic_array(dst))[i] = addr;
357 dst += incr;
358 }
359 ),
360 TP_printk("pid:%u vm_ctx:0x%llx start:0x%010llx end:0x%010llx,"
361 " flags:0x%llx, incr:%llu, dst:\n%s", __entry->pid,
362 __entry->vm_ctx, __entry->start, __entry->end,
363 __entry->flags, __entry->incr, __print_array(
364 __get_dynamic_array(dst), __entry->nptes, 8))
365);
366
367TRACE_EVENT(amdgpu_vm_set_ptes,
368 TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
369 uint32_t incr, uint64_t flags, bool immediate),
370 TP_ARGS(pe, addr, count, incr, flags, immediate),
371 TP_STRUCT__entry(
372 __field(u64, pe)
373 __field(u64, addr)
374 __field(u32, count)
375 __field(u32, incr)
376 __field(u64, flags)
377 __field(bool, immediate)
378 ),
379
380 TP_fast_assign(
381 __entry->pe = pe;
382 __entry->addr = addr;
383 __entry->count = count;
384 __entry->incr = incr;
385 __entry->flags = flags;
386 __entry->immediate = immediate;
387 ),
388 TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u, "
389 "immediate=%d", __entry->pe, __entry->addr, __entry->incr,
390 __entry->flags, __entry->count, __entry->immediate)
391);
392
393TRACE_EVENT(amdgpu_vm_copy_ptes,
394 TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool immediate),
395 TP_ARGS(pe, src, count, immediate),
396 TP_STRUCT__entry(
397 __field(u64, pe)
398 __field(u64, src)
399 __field(u32, count)
400 __field(bool, immediate)
401 ),
402
403 TP_fast_assign(
404 __entry->pe = pe;
405 __entry->src = src;
406 __entry->count = count;
407 __entry->immediate = immediate;
408 ),
409 TP_printk("pe=%010Lx, src=%010Lx, count=%u, immediate=%d",
410 __entry->pe, __entry->src, __entry->count,
411 __entry->immediate)
412);
413
414TRACE_EVENT(amdgpu_vm_flush,
415 TP_PROTO(struct amdgpu_ring *ring, unsigned vmid,
416 uint64_t pd_addr),
417 TP_ARGS(ring, vmid, pd_addr),
418 TP_STRUCT__entry(
419 __string(ring, ring->name)
420 __field(u32, vmid)
421 __field(u32, vm_hub)
422 __field(u64, pd_addr)
423 ),
424
425 TP_fast_assign(
426 __assign_str(ring);
427 __entry->vmid = vmid;
428 __entry->vm_hub = ring->vm_hub;
429 __entry->pd_addr = pd_addr;
430 ),
431 TP_printk("ring=%s, id=%u, hub=%u, pd_addr=%010Lx",
432 __get_str(ring), __entry->vmid,
433 __entry->vm_hub, __entry->pd_addr)
434);
435
436DECLARE_EVENT_CLASS(amdgpu_pasid,
437 TP_PROTO(unsigned pasid),
438 TP_ARGS(pasid),
439 TP_STRUCT__entry(
440 __field(unsigned, pasid)
441 ),
442 TP_fast_assign(
443 __entry->pasid = pasid;
444 ),
445 TP_printk("pasid=%u", __entry->pasid)
446);
447
448DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_allocated,
449 TP_PROTO(unsigned pasid),
450 TP_ARGS(pasid)
451);
452
453DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_freed,
454 TP_PROTO(unsigned pasid),
455 TP_ARGS(pasid)
456);
457
458TRACE_EVENT(amdgpu_isolation,
459 TP_PROTO(void *prev, void *next),
460 TP_ARGS(prev, next),
461 TP_STRUCT__entry(
462 __field(void *, prev)
463 __field(void *, next)
464 ),
465
466 TP_fast_assign(
467 __entry->prev = prev;
468 __entry->next = next;
469 ),
470 TP_printk("prev=%p, next=%p",
471 __entry->prev,
472 __entry->next)
473);
474
475TRACE_EVENT(amdgpu_cleaner_shader,
476 TP_PROTO(struct amdgpu_ring *ring, struct dma_fence *fence),
477 TP_ARGS(ring, fence),
478 TP_STRUCT__entry(
479 __string(ring, ring->name)
480 __field(u64, seqno)
481 ),
482
483 TP_fast_assign(
484 __assign_str(ring);
485 __entry->seqno = fence->seqno;
486 ),
487 TP_printk("ring=%s, seqno=%Lu", __get_str(ring), __entry->seqno)
488);
489
490TRACE_EVENT(amdgpu_bo_list_set,
491 TP_PROTO(struct amdgpu_bo_list *list, struct amdgpu_bo *bo),
492 TP_ARGS(list, bo),
493 TP_STRUCT__entry(
494 __field(struct amdgpu_bo_list *, list)
495 __field(struct amdgpu_bo *, bo)
496 __field(u64, bo_size)
497 ),
498
499 TP_fast_assign(
500 __entry->list = list;
501 __entry->bo = bo;
502 __entry->bo_size = amdgpu_bo_size(bo);
503 ),
504 TP_printk("list=%p, bo=%p, bo_size=%Ld",
505 __entry->list,
506 __entry->bo,
507 __entry->bo_size)
508);
509
510TRACE_EVENT(amdgpu_cs_bo_status,
511 TP_PROTO(uint64_t total_bo, uint64_t total_size),
512 TP_ARGS(total_bo, total_size),
513 TP_STRUCT__entry(
514 __field(u64, total_bo)
515 __field(u64, total_size)
516 ),
517
518 TP_fast_assign(
519 __entry->total_bo = total_bo;
520 __entry->total_size = total_size;
521 ),
522 TP_printk("total_bo_size=%Ld, total_bo_count=%Ld",
523 __entry->total_bo, __entry->total_size)
524);
525
526TRACE_EVENT(amdgpu_bo_move,
527 TP_PROTO(struct amdgpu_bo *bo, uint32_t new_placement, uint32_t old_placement),
528 TP_ARGS(bo, new_placement, old_placement),
529 TP_STRUCT__entry(
530 __field(struct amdgpu_bo *, bo)
531 __field(u64, bo_size)
532 __field(u32, new_placement)
533 __field(u32, old_placement)
534 ),
535
536 TP_fast_assign(
537 __entry->bo = bo;
538 __entry->bo_size = amdgpu_bo_size(bo);
539 __entry->new_placement = new_placement;
540 __entry->old_placement = old_placement;
541 ),
542 TP_printk("bo=%p, from=%d, to=%d, size=%Ld",
543 __entry->bo, __entry->old_placement,
544 __entry->new_placement, __entry->bo_size)
545);
546
547TRACE_EVENT(amdgpu_ib_pipe_sync,
548 TP_PROTO(struct amdgpu_job *sched_job, struct dma_fence *fence),
549 TP_ARGS(sched_job, fence),
550 TP_STRUCT__entry(
551 __string(ring, sched_job->base.sched->name)
552 __field(struct dma_fence *, fence)
553 __field(u64, ctx)
554 __field(u64, seqno)
555 ),
556
557 TP_fast_assign(
558 __assign_str(ring);
559 __entry->fence = fence;
560 __entry->ctx = fence->context;
561 __entry->seqno = fence->seqno;
562 ),
563 TP_printk("job ring=%s need pipe sync to fence=%llu:%llu",
564 __get_str(ring), __entry->ctx, __entry->seqno)
565);
566
567TRACE_EVENT(amdgpu_reset_reg_dumps,
568 TP_PROTO(uint32_t address, uint32_t value),
569 TP_ARGS(address, value),
570 TP_STRUCT__entry(
571 __field(uint32_t, address)
572 __field(uint32_t, value)
573 ),
574 TP_fast_assign(
575 __entry->address = address;
576 __entry->value = value;
577 ),
578 TP_printk("amdgpu register dump 0x%x: 0x%x",
579 __entry->address,
580 __entry->value)
581);
582
583DECLARE_EVENT_CLASS(amdgpu_userq_queue,
584 TP_PROTO(struct amdgpu_usermode_queue *queue),
585 TP_ARGS(queue),
586 TP_STRUCT__entry(
587 __field(void *, queue)
588 __field(u64, doorbell_index)
589 __field(int, queue_type)
590 __field(int, state)
591 __field(u32, xcp_id)
592 ),
593 TP_fast_assign(
594 __entry->queue = queue;
595 __entry->doorbell_index = queue->doorbell_index;
596 __entry->queue_type = queue->queue_type;
597 __entry->state = queue->state;
598 __entry->xcp_id = queue->xcp_id;
599 ),
600 TP_printk("queue=%p, doorbell=%llu, type=%d, state=%d, xcp_id=%u",
601 __entry->queue, __entry->doorbell_index,
602 __entry->queue_type, __entry->state, __entry->xcp_id)
603);
604DEFINE_EVENT(amdgpu_userq_queue, amdgpu_userq_create_start,
605 TP_PROTO(struct amdgpu_usermode_queue *queue),
606 TP_ARGS(queue));
607DEFINE_EVENT(amdgpu_userq_queue, amdgpu_userq_destroy_start,
608 TP_PROTO(struct amdgpu_usermode_queue *queue),
609 TP_ARGS(queue));
610DECLARE_EVENT_CLASS(amdgpu_userq_queue_result,
611 TP_PROTO(struct amdgpu_usermode_queue *queue, int result),
612 TP_ARGS(queue, result),
613 TP_STRUCT__entry(
614 __field(void *, queue)
615 __field(u64, doorbell_index)
616 __field(int, queue_type)
617 __field(int, state)
618 __field(u32, xcp_id)
619 __field(int, result)
620 ),
621 TP_fast_assign(
622 __entry->queue = queue;
623 __entry->doorbell_index = queue->doorbell_index;
624 __entry->queue_type = queue->queue_type;
625 __entry->state = queue->state;
626 __entry->xcp_id = queue->xcp_id;
627 __entry->result = result;
628 ),
629 TP_printk("queue=%p, doorbell=%llu, type=%d, state=%d, xcp_id=%u, result=%d",
630 __entry->queue, __entry->doorbell_index,
631 __entry->queue_type, __entry->state,
632 __entry->xcp_id, __entry->result)
633);
634DEFINE_EVENT(amdgpu_userq_queue_result, amdgpu_userq_create_end,
635 TP_PROTO(struct amdgpu_usermode_queue *queue, int result),
636 TP_ARGS(queue, result));
637DEFINE_EVENT(amdgpu_userq_queue_result, amdgpu_userq_destroy_end,
638 TP_PROTO(struct amdgpu_usermode_queue *queue, int result),
639 TP_ARGS(queue, result));
640
641TRACE_EVENT(amdgpu_userq_emit_fence,
642 TP_PROTO(struct device *device, struct amdgpu_usermode_queue *queue, struct amdgpu_userq_fence *fence),
643 TP_ARGS(device, queue, fence),
644 TP_STRUCT__entry(
645 __field(u64, fence_context)
646 __field(u64, fence_seqno)
647 __string(dev, dev_name(device))
648 __field(u64, doorbell_index)
649 __field(u64, client_id)
650 __field(u32, queue_type)
651 ),
652 TP_fast_assign(
653 __entry->fence_context = fence->base.context;
654 __entry->fence_seqno = fence->base.seqno;
655 __assign_str(dev);
656 __entry->doorbell_index = queue->doorbell_index;
657 __entry->client_id = queue->userq_mgr->file->client_id;
658 __entry->queue_type = queue->queue_type;
659 ),
660 TP_printk("dev=%s, client_id=%llu, type=%u, doorbell=%llu, fence=%llu:%llu",
661 __get_str(dev), __entry->client_id, __entry->queue_type, __entry->doorbell_index,
662 __entry->fence_context,
663 __entry->fence_seqno)
664);
665
666TRACE_EVENT(amdgpu_userq_wait_deps,
667 TP_PROTO(struct device *device, struct amdgpu_usermode_queue *queue, struct amdgpu_userq_fence *dep),
668 TP_ARGS(device, queue, dep),
669 TP_STRUCT__entry(
670 __field(u64, context)
671 __field(u64, dep_context)
672 __field(u64, dep_seqno)
673 __string(dev, dev_name(device))
674 __field(u64, doorbell_index)
675 __field(u64, client_id)
676 __field(u32, queue_type)
677 ),
678 TP_fast_assign(
679 __assign_str(dev);
680 __entry->doorbell_index = queue->doorbell_index;
681 __entry->queue_type = queue->queue_type;
682 __entry->client_id = queue->userq_mgr->file->client_id;
683 __entry->context = queue->fence_drv->context;
684 __entry->dep_context = dep->base.context;
685 __entry->dep_seqno = dep->base.seqno;
686 ),
687 TP_printk("dev=%s, client_id=%llu, type=%u, doorbell=%llu, context=%llu depends on fence=%llu:%llu",
688 __get_str(dev), __entry->client_id, __entry->queue_type, __entry->doorbell_index, __entry->context,
689 __entry->dep_context,
690 __entry->dep_seqno)
691);
692
693TRACE_EVENT(amdgpu_userq_state_start,
694 TP_PROTO(struct amdgpu_usermode_queue *queue),
695 TP_ARGS(queue),
696 TP_STRUCT__entry(
697 __field(u64, doorbell_index)
698 __field(u64, client_id)
699 __field(u32, queue_type)
700 __field(u32, from)
701 ),
702 TP_fast_assign(
703 __entry->doorbell_index = queue->doorbell_index;
704 __entry->queue_type = queue->queue_type;
705 __entry->client_id = queue->userq_mgr->file->client_id;
706 __entry->from = queue->state;
707 ),
708 TP_printk("client_id=%llu, type=%u, doorbell=%llu, from=%d",
709 __entry->client_id, __entry->queue_type, __entry->doorbell_index, __entry->from)
710);
711
712TRACE_EVENT(amdgpu_userq_state_changed,
713 TP_PROTO(struct amdgpu_usermode_queue *queue, enum amdgpu_userq_state new_state),
714 TP_ARGS(queue, new_state),
715 TP_STRUCT__entry(
716 __field(u64, doorbell_index)
717 __field(u64, client_id)
718 __field(u32, queue_type)
719 __field(u32, to)
720 ),
721 TP_fast_assign(
722 __entry->doorbell_index = queue->doorbell_index;
723 __entry->queue_type = queue->queue_type;
724 __entry->client_id = queue->userq_mgr->file->client_id;
725 __entry->to = new_state;
726 ),
727 TP_printk("client_id=%llu, type=%u, doorbell=%llu, to=%d",
728 __entry->client_id, __entry->queue_type, __entry->doorbell_index, __entry->to)
729);
730
731#undef AMDGPU_JOB_GET_TIMELINE_NAME
732#endif
733
734/* This part must be outside protection */
735#undef TRACE_INCLUDE_PATH
736#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu
737#include <trace/define_trace.h>