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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_TTM_H__
25#define __AMDGPU_TTM_H__
26
27#include <linux/dma-direction.h>
28#include <drm/gpu_scheduler.h>
29#include <drm/ttm/ttm_placement.h>
30#include "amdgpu_vram_mgr.h"
31#include "amdgpu_hmm.h"
32#include "amdgpu_gmc.h"
33
34#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
35#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
36#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
37#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
38#define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4)
39#define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5)
40#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
41
42#define AMDGPU_GTT_MAX_TRANSFER_SIZE (1ULL << 22)
43
44extern const struct attribute_group amdgpu_vram_mgr_attr_group;
45extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
46
47struct hmm_range;
48
49struct amdgpu_gtt_mgr {
50 struct ttm_resource_manager manager;
51 struct drm_mm mm;
52 spinlock_t lock;
53};
54
55struct amdgpu_ttm_buffer_entity {
56 struct drm_sched_entity base;
57 struct mutex lock;
58 struct drm_mm_node gart_node;
59 u64 gart_window_offs[2];
60};
61
62enum amdgpu_resv_region_id {
63 AMDGPU_RESV_STOLEN_VGA,
64 AMDGPU_RESV_STOLEN_EXTENDED,
65 AMDGPU_RESV_STOLEN_RESERVED,
66 AMDGPU_RESV_FW,
67 AMDGPU_RESV_FW_EXTEND,
68 AMDGPU_RESV_FW_VRAM_USAGE,
69 AMDGPU_RESV_DRV_VRAM_USAGE,
70 AMDGPU_RESV_MEM_TRAIN,
71 AMDGPU_RESV_MAX
72};
73
74struct amdgpu_vram_resv {
75 uint64_t offset;
76 uint64_t size;
77 struct amdgpu_bo *bo;
78 void *cpu_ptr;
79 bool needs_cpu_map;
80};
81
82struct amdgpu_mman {
83 struct ttm_device bdev;
84 struct ttm_pool *ttm_pools;
85 bool initialized;
86 void __iomem *aper_base_kaddr;
87
88 /* buffer handling */
89 const struct amdgpu_buffer_funcs *buffer_funcs;
90 struct drm_gpu_scheduler *buffer_funcs_scheds[AMDGPU_MAX_RINGS];
91 u32 num_buffer_funcs_scheds;
92 bool buffer_funcs_enabled;
93
94 /* @default_entity: for workarounds, has no gart windows */
95 struct amdgpu_ttm_buffer_entity default_entity;
96 struct amdgpu_ttm_buffer_entity *clear_entities;
97 atomic_t next_clear_entity;
98 u32 num_clear_entities;
99 struct amdgpu_ttm_buffer_entity move_entities[TTM_NUM_MOVE_FENCES];
100 atomic_t next_move_entity;
101 u32 num_move_entities;
102
103 struct amdgpu_vram_mgr vram_mgr;
104 struct amdgpu_gtt_mgr gtt_mgr;
105 struct ttm_resource_manager preempt_mgr;
106
107 bool keep_stolen_vga_memory;
108
109 struct amdgpu_vram_resv resv_region[AMDGPU_RESV_MAX];
110
111 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
112 struct amdgpu_bo *sdma_access_bo;
113 void *sdma_access_ptr;
114};
115
116struct amdgpu_copy_mem {
117 struct ttm_buffer_object *bo;
118 struct ttm_resource *mem;
119 unsigned long offset;
120};
121
122#define AMDGPU_COPY_FLAGS_TMZ (1 << 0)
123#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1)
124#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2)
125#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3
126#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03
127#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT 5
128#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
129#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
130#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
131#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
132#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
133
134#define AMDGPU_COPY_FLAGS_SET(field, value) \
135 (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)
136#define AMDGPU_COPY_FLAGS_GET(value, field) \
137 (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK)
138
139int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
140void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
141int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
142void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
143void amdgpu_preempt_mgr_sysfs_fini(struct amdgpu_device *adev);
144int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
145void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
146
147bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
148void amdgpu_gtt_mgr_mark_bo_teardown(struct ttm_buffer_object *tbo);
149void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
150
151int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr,
152 struct drm_mm_node *mm_node,
153 u64 num_pages,
154 enum drm_mm_insert_mode mode);
155void amdgpu_gtt_mgr_free_entries(struct amdgpu_gtt_mgr *mgr,
156 struct drm_mm_node *mm_node);
157uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
158
159u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
160int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
161 struct ttm_resource *mem,
162 u64 offset, u64 size,
163 struct device *dev,
164 enum dma_data_direction dir,
165 struct sg_table **sgt);
166void amdgpu_vram_mgr_free_sgt(struct device *dev,
167 enum dma_data_direction dir,
168 struct sg_table *sgt);
169uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
170int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
171 uint64_t start, uint64_t size);
172int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
173 uint64_t start);
174void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev);
175
176bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
177 struct ttm_resource *res);
178
179void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev,
180 enum amdgpu_resv_region_id id,
181 uint64_t offset, uint64_t size,
182 bool needs_cpu_map);
183int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev,
184 enum amdgpu_resv_region_id id);
185void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev,
186 enum amdgpu_resv_region_id id);
187
188int amdgpu_ttm_init(struct amdgpu_device *adev);
189void amdgpu_ttm_fini(struct amdgpu_device *adev);
190void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev);
191void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev);
192int amdgpu_copy_buffer(struct amdgpu_device *adev,
193 struct amdgpu_ttm_buffer_entity *entity,
194 uint64_t src_offset,
195 uint64_t dst_offset, uint32_t byte_count,
196 struct dma_resv *resv,
197 struct dma_fence **fence,
198 bool vm_needs_flush, uint32_t copy_flags);
199int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity,
200 struct amdgpu_bo *bo,
201 struct dma_resv *resv,
202 struct dma_fence **out_fence,
203 bool consider_clear_status,
204 u64 k_job_id);
205struct amdgpu_ttm_buffer_entity *amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev);
206
207int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
208void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
209uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
210
211#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
212int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
213 struct amdgpu_hmm_range *range);
214#else
215static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
216 struct amdgpu_hmm_range *range)
217{
218 return -EPERM;
219}
220#endif
221
222/**
223 * amdgpu_compute_gart_address() - Returns GART address of an entity's window
224 * @gmc: The &struct amdgpu_gmc instance to use
225 * @entity: The &struct amdgpu_ttm_buffer_entity owning the GART window
226 * @index: The window to use (must be 0 or 1)
227 */
228static inline u64 amdgpu_compute_gart_address(struct amdgpu_gmc *gmc,
229 struct amdgpu_ttm_buffer_entity *entity,
230 int index)
231{
232 return gmc->gart_start + entity->gart_window_offs[index];
233}
234
235/**
236 * amdgpu_gtt_node_to_byte_offset() - Returns a byte offset of a gtt node
237 */
238static inline u64 amdgpu_gtt_node_to_byte_offset(const struct drm_mm_node *gtt_node)
239{
240 return gtt_node->start * (u64)PAGE_SIZE;
241}
242
243void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range);
244int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
245 uint64_t *user_addr);
246int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
247 uint64_t addr, uint32_t flags);
248bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
249struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
250bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
251 unsigned long end, unsigned long *userptr);
252bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
253 int *last_invalidated);
254bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
255bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
256uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
257uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
258 struct ttm_resource *mem);
259int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
260
261void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
262
263int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev,
264 struct ttm_resource *res,
265 struct device *dev,
266 enum dma_data_direction dir,
267 struct sg_table **sgt);
268void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev,
269 enum dma_data_direction dir,
270 struct sg_table *sgt);
271
272#endif