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1/*
2 * Copyright 2016-2024 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_VCN_H__
25#define __AMDGPU_VCN_H__
26
27#include "amdgpu_ras.h"
28
29#define AMDGPU_VCN_STACK_SIZE (128*1024)
30#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)
31
32#define AMDGPU_VCN_FIRMWARE_OFFSET 256
33#define AMDGPU_VCN_MAX_ENC_RINGS 3
34
35#define AMDGPU_MAX_VCN_INSTANCES 4
36#define AMDGPU_MAX_VCN_ENC_RINGS (AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES)
37
38#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
39#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
40
41#define VCN_DEC_KMD_CMD 0x80000000
42#define VCN_DEC_CMD_FENCE 0x00000000
43#define VCN_DEC_CMD_TRAP 0x00000001
44#define VCN_DEC_CMD_WRITE_REG 0x00000004
45#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
46#define VCN_DEC_CMD_PACKET_START 0x0000000a
47#define VCN_DEC_CMD_PACKET_END 0x0000000b
48
49#define VCN_DEC_SW_CMD_NO_OP 0x00000000
50#define VCN_DEC_SW_CMD_END 0x00000001
51#define VCN_DEC_SW_CMD_IB 0x00000002
52#define VCN_DEC_SW_CMD_FENCE 0x00000003
53#define VCN_DEC_SW_CMD_TRAP 0x00000004
54#define VCN_DEC_SW_CMD_IB_AUTO 0x00000005
55#define VCN_DEC_SW_CMD_SEMAPHORE 0x00000006
56#define VCN_DEC_SW_CMD_PREEMPT_FENCE 0x00000009
57#define VCN_DEC_SW_CMD_REG_WRITE 0x0000000b
58#define VCN_DEC_SW_CMD_REG_WAIT 0x0000000c
59
60#define VCN_ENC_CMD_NO_OP 0x00000000
61#define VCN_ENC_CMD_END 0x00000001
62#define VCN_ENC_CMD_IB 0x00000002
63#define VCN_ENC_CMD_FENCE 0x00000003
64#define VCN_ENC_CMD_TRAP 0x00000004
65#define VCN_ENC_CMD_REG_WRITE 0x0000000b
66#define VCN_ENC_CMD_REG_WAIT 0x0000000c
67
68#define VCN_AON_SOC_ADDRESS_2_0 0x1f800
69#define VCN_VID_IP_ADDRESS_2_0 0x0
70#define VCN_AON_IP_ADDRESS_2_0 0x30000
71
72#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
73#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
74#define mmUVD_REG_XX_MASK 0x026c
75#define mmUVD_REG_XX_MASK_BASE_IDX 1
76
77/* 1 second timeout */
78#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
79
80#define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \
81 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
83 UVD_DPG_LMA_CTL__MASK_EN_MASK | \
84 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
85 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
86 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
87 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
88 })
89
90#define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \
91 do { \
92 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
95 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
96 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
97 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
98 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
99 } while (0)
100
101#define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \
102 ({ \
103 /* To avoid a -Wunused-but-set-variable warning. */ \
104 uint32_t internal_reg_offset __maybe_unused, addr; \
105 bool video_range, video1_range, aon_range, aon1_range; \
106 \
107 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
108 addr <<= 2; \
109 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
110 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
111 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && \
112 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600))))); \
113 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \
114 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \
115 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && \
116 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600))))); \
117 if (video_range) \
118 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \
119 (VCN_VID_IP_ADDRESS_2_0)); \
120 else if (aon_range) \
121 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \
122 (VCN_AON_IP_ADDRESS_2_0)); \
123 else if (video1_range) \
124 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + \
125 (VCN_VID_IP_ADDRESS_2_0)); \
126 else if (aon1_range) \
127 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + \
128 (VCN_AON_IP_ADDRESS_2_0)); \
129 else \
130 internal_reg_offset = (0xFFFFF & addr); \
131 \
132 internal_reg_offset >>= 2; \
133 })
134
135#define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \
136 ({ \
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
138 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
139 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
140 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
142 })
143
144#define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \
145 do { \
146 if (!indirect) { \
147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
148 mmUVD_DPG_LMA_DATA, value); \
149 WREG32_SOC15( \
150 VCN, GET_INST(VCN, inst_idx), \
151 mmUVD_DPG_LMA_CTL, \
152 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
153 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
154 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
155 } else { \
156 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
157 offset; \
158 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
159 value; \
160 } \
161 } while (0)
162
163#define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \
164 ({ \
165 /* To avoid a -Wunused-but-set-variable warning. */ \
166 uint32_t internal_reg_offset __maybe_unused, addr; \
167 bool video_range, video1_range, aon_range, aon1_range; \
168 \
169 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
170 addr <<= 2; \
171 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS)) && \
172 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS + 0x2600))))); \
173 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS)) && \
174 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS + 0x2600))))); \
175 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS)) && \
176 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS + 0x600))))); \
177 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS)) && \
178 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS + 0x600))))); \
179 if (video_range) \
180 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS) + \
181 (VCN_VID_IP_ADDRESS)); \
182 else if (aon_range) \
183 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS) + \
184 (VCN_AON_IP_ADDRESS)); \
185 else if (video1_range) \
186 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS) + \
187 (VCN_VID_IP_ADDRESS)); \
188 else if (aon1_range) \
189 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS) + \
190 (VCN_AON_IP_ADDRESS)); \
191 else \
192 internal_reg_offset = (0xFFFFF & addr); \
193 \
194 internal_reg_offset >>= 2; \
195 })
196
197#define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \
198 do { \
199 if (!indirect) { \
200 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
201 regUVD_DPG_LMA_DATA, value); \
202 WREG32_SOC15( \
203 VCN, GET_INST(VCN, inst_idx), \
204 regUVD_DPG_LMA_CTL, \
205 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
206 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
207 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
208 } else { \
209 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
210 offset; \
211 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
212 value; \
213 } \
214 } while (0)
215
216#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)
217#define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4)
218#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)
219#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)
220#define AMDGPU_VCN_SW_RING_FLAG (1 << 9)
221#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
222#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
223#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
224#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
225#define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG (1 << 15)
226
227#define MAX_NUM_VCN_RB_SETUP 4
228
229#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
230#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
231
232#define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0)
233#define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1)
234#define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2)
235#define VCN_CODEC_DISABLE_MASK_H264 (1 << 3)
236
237#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0)
238#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1)
239
240#define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2
241
242struct amdgpu_hwip_reg_entry;
243
244enum amdgpu_vcn_caps {
245 AMDGPU_VCN_RRMT_ENABLED,
246};
247
248#define AMDGPU_VCN_CAPS(caps) BIT(AMDGPU_VCN_##caps)
249
250enum fw_queue_mode {
251 FW_QUEUE_RING_RESET = 1,
252 FW_QUEUE_DPG_HOLD_OFF = 2,
253};
254
255enum engine_status_constants {
256 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
257 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
258 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
259 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
260 UVD_STATUS__UVD_BUSY = 0x00000004,
261 GB_ADDR_CONFIG_DEFAULT = 0x26010011,
262 UVD_STATUS__IDLE = 0x2,
263 UVD_STATUS__BUSY = 0x5,
264 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
265 UVD_STATUS__RBC_BUSY = 0x1,
266 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
267};
268
269enum internal_dpg_state {
270 VCN_DPG_STATE__UNPAUSE = 0,
271 VCN_DPG_STATE__PAUSE,
272};
273
274struct dpg_pause_state {
275 enum internal_dpg_state fw_based;
276 enum internal_dpg_state jpeg;
277};
278
279struct amdgpu_vcn_reg{
280 unsigned data0;
281 unsigned data1;
282 unsigned cmd;
283 unsigned nop;
284 unsigned context_id;
285 unsigned ib_vmid;
286 unsigned ib_bar_low;
287 unsigned ib_bar_high;
288 unsigned ib_size;
289 unsigned gp_scratch8;
290 unsigned scratch9;
291};
292
293struct amdgpu_vcn_fw_shared {
294 void *cpu_addr;
295 uint64_t gpu_addr;
296 uint32_t mem_size;
297 uint32_t log_offset;
298};
299
300struct amdgpu_vcn_inst {
301 struct amdgpu_device *adev;
302 int inst;
303 struct amdgpu_bo *vcpu_bo;
304 void *cpu_addr;
305 uint64_t gpu_addr;
306 void *saved_bo;
307 struct amdgpu_ring ring_dec;
308 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
309 atomic_t sched_score;
310 struct amdgpu_irq_src irq;
311 struct amdgpu_irq_src ras_poison_irq;
312 struct amdgpu_vcn_reg external;
313 struct amdgpu_bo *dpg_sram_bo;
314 struct dpg_pause_state pause_state;
315 void *dpg_sram_cpu_addr;
316 uint64_t dpg_sram_gpu_addr;
317 uint32_t *dpg_sram_curr_addr;
318 atomic_t dpg_enc_submission_cnt;
319 struct amdgpu_vcn_fw_shared fw_shared;
320 uint8_t aid_id;
321 const struct firmware *fw; /* VCN firmware */
322 uint8_t vcn_config;
323 uint32_t vcn_codec_disable_mask;
324 atomic_t total_submission_cnt;
325 struct mutex vcn_pg_lock;
326 enum amd_powergating_state cur_state;
327 struct delayed_work idle_work;
328 unsigned fw_version;
329 unsigned num_enc_rings;
330 bool indirect_sram;
331 struct amdgpu_vcn_reg internal;
332 struct mutex vcn1_jpeg1_workaround;
333 int (*pause_dpg_mode)(struct amdgpu_vcn_inst *vinst,
334 struct dpg_pause_state *new_state);
335 int (*set_pg_state)(struct amdgpu_vcn_inst *vinst,
336 enum amd_powergating_state state);
337 int (*reset)(struct amdgpu_vcn_inst *vinst);
338 bool using_unified_queue;
339 struct mutex engine_reset_mutex;
340};
341
342struct amdgpu_vcn_ras {
343 struct amdgpu_ras_block_object ras_block;
344};
345
346struct amdgpu_vcn {
347 uint8_t num_vcn_inst;
348 struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
349
350 unsigned harvest_config;
351
352 struct ras_common_if *ras_if;
353 struct amdgpu_vcn_ras *ras;
354
355 uint16_t inst_mask;
356 uint8_t num_inst_per_aid;
357
358 /* IP reg dump */
359 uint32_t *ip_dump;
360
361 uint32_t supported_reset;
362 uint32_t caps;
363
364 bool per_inst_fw;
365 unsigned fw_version;
366
367 bool workload_profile_active;
368 struct mutex workload_profile_mutex;
369 u32 reg_count;
370 const struct amdgpu_hwip_reg_entry *reg_list;
371
372 bool disable_uq;
373 bool disable_kq;
374};
375
376struct amdgpu_fw_shared_rb_ptrs_struct {
377 /* to WA DPG R/W ptr issues.*/
378 uint32_t rptr;
379 uint32_t wptr;
380};
381
382struct amdgpu_fw_shared_multi_queue {
383 uint8_t decode_queue_mode;
384 uint8_t encode_generalpurpose_queue_mode;
385 uint8_t encode_lowlatency_queue_mode;
386 uint8_t encode_realtime_queue_mode;
387 uint8_t padding[4];
388};
389
390struct amdgpu_fw_shared_sw_ring {
391 uint8_t is_enabled;
392 uint8_t padding[3];
393};
394
395struct amdgpu_fw_shared_unified_queue_struct {
396 uint8_t is_enabled;
397 uint8_t queue_mode;
398 uint8_t queue_status;
399 uint8_t padding[5];
400};
401
402struct amdgpu_fw_shared_fw_logging {
403 uint8_t is_enabled;
404 uint32_t addr_lo;
405 uint32_t addr_hi;
406 uint32_t size;
407};
408
409struct amdgpu_fw_shared_smu_interface_info {
410 uint8_t smu_interface_type;
411 uint8_t padding[3];
412};
413
414struct amdgpu_fw_shared {
415 uint32_t present_flag_0;
416 uint8_t pad[44];
417 struct amdgpu_fw_shared_rb_ptrs_struct rb;
418 uint8_t pad1[1];
419 struct amdgpu_fw_shared_multi_queue multi_queue;
420 struct amdgpu_fw_shared_sw_ring sw_ring;
421 struct amdgpu_fw_shared_fw_logging fw_log;
422 struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
423};
424
425struct amdgpu_vcn_rb_setup_info {
426 uint32_t rb_addr_lo;
427 uint32_t rb_addr_hi;
428 uint32_t rb_size;
429};
430
431struct amdgpu_fw_shared_rb_setup {
432 uint32_t is_rb_enabled_flags;
433
434 union {
435 struct {
436 uint32_t rb_addr_lo;
437 uint32_t rb_addr_hi;
438 uint32_t rb_size;
439 uint32_t rb4_addr_lo;
440 uint32_t rb4_addr_hi;
441 uint32_t rb4_size;
442 uint32_t reserved[6];
443 };
444
445 struct {
446 struct amdgpu_vcn_rb_setup_info rb_info[MAX_NUM_VCN_RB_SETUP];
447 };
448 };
449};
450
451struct amdgpu_fw_shared_drm_key_wa {
452 uint8_t method;
453 uint8_t reserved[3];
454};
455
456struct amdgpu_fw_shared_queue_decouple {
457 uint8_t is_enabled;
458 uint8_t reserved[7];
459};
460
461struct amdgpu_vcn4_fw_shared {
462 uint32_t present_flag_0;
463 uint8_t pad[12];
464 struct amdgpu_fw_shared_unified_queue_struct sq;
465 uint8_t pad1[8];
466 struct amdgpu_fw_shared_fw_logging fw_log;
467 uint8_t pad2[20];
468 struct amdgpu_fw_shared_rb_setup rb_setup;
469 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
470 struct amdgpu_fw_shared_drm_key_wa drm_key_wa;
471 uint8_t pad3[9];
472 struct amdgpu_fw_shared_queue_decouple decouple;
473};
474
475struct amdgpu_vcn_fwlog {
476 uint32_t rptr;
477 uint32_t wptr;
478 uint32_t buffer_size;
479 uint32_t header_size;
480 uint8_t wrapped;
481};
482
483struct amdgpu_vcn_decode_buffer {
484 uint32_t valid_buf_flag;
485 uint32_t msg_buffer_address_hi;
486 uint32_t msg_buffer_address_lo;
487 uint32_t pad[30];
488};
489
490struct amdgpu_vcn_rb_metadata {
491 uint32_t size;
492 uint32_t present_flag_0;
493
494 uint8_t version;
495 uint8_t ring_id;
496 uint8_t pad[26];
497};
498
499struct amdgpu_vcn5_fw_shared {
500 uint32_t present_flag_0;
501 uint8_t pad[12];
502 struct amdgpu_fw_shared_unified_queue_struct sq;
503 uint8_t pad1[8];
504 struct amdgpu_fw_shared_fw_logging fw_log;
505 uint8_t pad2[20];
506 struct amdgpu_fw_shared_rb_setup rb_setup;
507 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
508 struct amdgpu_fw_shared_drm_key_wa drm_key_wa;
509 uint8_t pad3[404];
510};
511
512#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
513#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
514#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
515
516enum vcn_ring_type {
517 VCN_ENCODE_RING,
518 VCN_DECODE_RING,
519 VCN_UNIFIED_RING,
520};
521
522int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i);
523int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i);
524void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i);
525int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i);
526int amdgpu_vcn_resume(struct amdgpu_device *adev, int i);
527void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
528void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
529
530bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
531 enum vcn_ring_type type, uint32_t vcn_instance);
532
533int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
534int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
535int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
536int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
537int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout);
538
539int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
540int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
541
542enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
543
544void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i);
545
546void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
547void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
548 uint8_t i, struct amdgpu_vcn_inst *vcn);
549
550int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
551 struct amdgpu_irq_src *source,
552 struct amdgpu_iv_entry *entry);
553int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev,
554 struct ras_common_if *ras_block);
555int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
556
557int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
558 enum AMDGPU_UCODE_ID ucode_id);
559int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev);
560int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev);
561void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev);
562void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev);
563
564int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,
565 enum amd_powergating_state state);
566int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,
567 unsigned int vmid,
568 struct amdgpu_fence *guilty_fence);
569int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev,
570 const struct amdgpu_hwip_reg_entry *reg, u32 count);
571void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block);
572void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p);
573void amdgpu_vcn_get_profile(struct amdgpu_device *adev);
574void amdgpu_vcn_put_profile(struct amdgpu_device *adev);
575
576#endif