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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: [email protected]
23 */
24#ifndef AMDGPU_VIRT_H
25#define AMDGPU_VIRT_H
26
27#include "amdgv_sriovmsg.h"
28
29#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34#define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36/* flags for indirect register access path supported by rlcg for sriov */
37#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
38#define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
39#define AMDGPU_RLCG_GC_READ (0x1 << 28)
40#define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
41
42/* error code for indirect register access path supported by rlcg for sriov */
43#define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
44#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
45#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
46
47#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
48#define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000
49
50#define AMDGPU_RLCG_VFI_CMD__WR 0x0
51#define AMDGPU_RLCG_VFI_CMD__RD 0x1
52
53#define AMDGPU_RLCG_VFI_STAT__BUSY 0x0
54#define AMDGPU_RLCG_VFI_STAT__DONE 0x1
55#define AMDGPU_RLCG_VFI_STAT__INV_CMD 0x2
56#define AMDGPU_RLCG_VFI_STAT__INV_ADDR 0x3
57#define AMDGPU_RLCG_VFI_STAT__ERR 0xFF
58
59/* all asic after AI use this offset */
60#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
61/* tonga/fiji use this offset */
62#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
63
64#define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2
65
66/* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */
67#define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA"
68#define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN 4
69
70#define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)->valid_tables & (1 << (id)))
71
72enum amdgpu_sriov_vf_mode {
73 SRIOV_VF_MODE_BARE_METAL = 0,
74 SRIOV_VF_MODE_ONE_VF,
75 SRIOV_VF_MODE_MULTI_VF,
76};
77
78struct amdgpu_mm_table {
79 struct amdgpu_bo *bo;
80 uint32_t *cpu_addr;
81 uint64_t gpu_addr;
82};
83
84#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
85
86/* struct error_entry - amdgpu VF error information. */
87struct amdgpu_vf_error_buffer {
88 struct mutex lock;
89 int read_count;
90 int write_count;
91 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
92 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
93 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
94};
95
96enum idh_request;
97
98/**
99 * struct amdgpu_virt_ops - amdgpu device virt operations
100 */
101struct amdgpu_virt_ops {
102 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
103 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
104 int (*req_init_data)(struct amdgpu_device *adev);
105 int (*reset_gpu)(struct amdgpu_device *adev);
106 void (*ready_to_reset)(struct amdgpu_device *adev);
107 int (*wait_reset)(struct amdgpu_device *adev);
108 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
109 u32 data1, u32 data2, u32 data3);
110 void (*ras_poison_handler)(struct amdgpu_device *adev,
111 enum amdgpu_ras_block block);
112 bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
113 int (*req_ras_err_count)(struct amdgpu_device *adev);
114 int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);
115 int (*req_bad_pages)(struct amdgpu_device *adev);
116 int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr);
117 int (*req_remote_ras_cmd)(struct amdgpu_device *adev,
118 u32 param1, u32 param2, u32 param3);
119 int (*req_ptl_update)(struct amdgpu_device *adev,
120 u32 req_code, u32 ptl_state, u32 fmt1, u32 fmt2);
121};
122
123/*
124 * Firmware Reserve Frame buffer
125 */
126struct amdgpu_virt_fw_reserve {
127 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
128 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
129 void *ras_telemetry;
130 unsigned int checksum_key;
131};
132
133/*
134 * Legacy GIM header
135 *
136 * Defination between PF and VF
137 * Structures forcibly aligned to 4 to keep the same style as PF.
138 */
139#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
140
141#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
142 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
143
144enum AMDGIM_FEATURE_FLAG {
145 /* GIM supports feature of Error log collecting */
146 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
147 /* GIM supports feature of loading uCodes */
148 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
149 /* VRAM LOST by GIM */
150 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
151 /* MM bandwidth */
152 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
153 /* PP ONE VF MODE in GIM */
154 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
155 /* Indirect Reg Access enabled */
156 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
157 /* AV1 Support MODE*/
158 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
159 /* VCN RB decouple */
160 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),
161 /* MES info */
162 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8),
163 AMDGIM_FEATURE_RAS_CAPS = (1 << 9),
164 AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10),
165 AMDGIM_FEATURE_RAS_CPER = (1 << 11),
166 AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12),
167 AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13),
168 AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14),
169 AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15),
170};
171
172enum AMDGIM_REG_ACCESS_FLAG {
173 /* Use PSP to program IH_RB_CNTL */
174 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
175 /* Use RLC to program MMHUB regs */
176 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
177 /* Use RLC to program GC regs */
178 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
179 /* Use PSP to program L1_TLB_CNTL */
180 AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 << 3),
181 /* Use RLCG to program SQ_CONFIG1 */
182 AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 << 4),
183};
184
185struct amdgim_pf2vf_info_v1 {
186 /* header contains size and version */
187 struct amd_sriov_msg_pf2vf_info_header header;
188 /* max_width * max_height */
189 unsigned int uvd_enc_max_pixels_count;
190 /* 16x16 pixels/sec, codec independent */
191 unsigned int uvd_enc_max_bandwidth;
192 /* max_width * max_height */
193 unsigned int vce_enc_max_pixels_count;
194 /* 16x16 pixels/sec, codec independent */
195 unsigned int vce_enc_max_bandwidth;
196 /* MEC FW position in kb from the start of visible frame buffer */
197 unsigned int mecfw_kboffset;
198 /* The features flags of the GIM driver supports. */
199 unsigned int feature_flags;
200 /* use private key from mailbox 2 to create chueksum */
201 unsigned int checksum;
202} __aligned(4);
203
204struct amdgim_vf2pf_info_v1 {
205 /* header contains size and version */
206 struct amd_sriov_msg_vf2pf_info_header header;
207 /* driver version */
208 char driver_version[64];
209 /* driver certification, 1=WHQL, 0=None */
210 unsigned int driver_cert;
211 /* guest OS type and version: need a define */
212 unsigned int os_info;
213 /* in the unit of 1M */
214 unsigned int fb_usage;
215 /* guest gfx engine usage percentage */
216 unsigned int gfx_usage;
217 /* guest gfx engine health percentage */
218 unsigned int gfx_health;
219 /* guest compute engine usage percentage */
220 unsigned int compute_usage;
221 /* guest compute engine health percentage */
222 unsigned int compute_health;
223 /* guest vce engine usage percentage. 0xffff means N/A. */
224 unsigned int vce_enc_usage;
225 /* guest vce engine health percentage. 0xffff means N/A. */
226 unsigned int vce_enc_health;
227 /* guest uvd engine usage percentage. 0xffff means N/A. */
228 unsigned int uvd_enc_usage;
229 /* guest uvd engine usage percentage. 0xffff means N/A. */
230 unsigned int uvd_enc_health;
231 unsigned int checksum;
232} __aligned(4);
233
234struct amdgim_vf2pf_info_v2 {
235 /* header contains size and version */
236 struct amd_sriov_msg_vf2pf_info_header header;
237 uint32_t checksum;
238 /* driver version */
239 uint8_t driver_version[64];
240 /* driver certification, 1=WHQL, 0=None */
241 uint32_t driver_cert;
242 /* guest OS type and version: need a define */
243 uint32_t os_info;
244 /* in the unit of 1M */
245 uint32_t fb_usage;
246 /* guest gfx engine usage percentage */
247 uint32_t gfx_usage;
248 /* guest gfx engine health percentage */
249 uint32_t gfx_health;
250 /* guest compute engine usage percentage */
251 uint32_t compute_usage;
252 /* guest compute engine health percentage */
253 uint32_t compute_health;
254 /* guest vce engine usage percentage. 0xffff means N/A. */
255 uint32_t vce_enc_usage;
256 /* guest vce engine health percentage. 0xffff means N/A. */
257 uint32_t vce_enc_health;
258 /* guest uvd engine usage percentage. 0xffff means N/A. */
259 uint32_t uvd_enc_usage;
260 /* guest uvd engine usage percentage. 0xffff means N/A. */
261 uint32_t uvd_enc_health;
262 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
263} __aligned(4);
264
265struct amdgpu_virt_ras_err_handler_data {
266 /* point to bad page records array */
267 struct eeprom_table_record *bps;
268 /* point to reserved bo array */
269 struct amdgpu_bo **bps_bo;
270 /* number of slots in bps[] / bps_bo[] (always >= count) */
271 int capacity;
272 /* the count of entries */
273 int count;
274 /* last reserved entry's index + 1 */
275 int last_reserved;
276};
277
278struct amdgpu_virt_ras {
279 struct ratelimit_state ras_error_cnt_rs;
280 struct ratelimit_state ras_cper_dump_rs;
281 struct ratelimit_state ras_chk_criti_rs;
282 struct mutex ras_telemetry_mutex;
283 uint64_t cper_rptr;
284};
285
286#define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT)
287
288DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST);
289
290struct amdgpu_virt_region {
291 uint32_t offset;
292 uint32_t size_kb;
293};
294
295/* GPU virtualization */
296struct amdgpu_virt {
297 uint32_t caps;
298 struct amdgpu_bo *csa_obj;
299 void *csa_cpu_addr;
300 bool chained_ib_support;
301 uint32_t reg_val_offs;
302 struct amdgpu_irq_src ack_irq;
303 struct amdgpu_irq_src rcv_irq;
304
305 struct work_struct flr_work;
306 struct work_struct req_bad_pages_work;
307 struct work_struct handle_bad_pages_work;
308
309 struct amdgpu_mm_table mm_table;
310 const struct amdgpu_virt_ops *ops;
311 struct amdgpu_vf_error_buffer vf_errors;
312 struct amdgpu_virt_fw_reserve fw_reserve;
313 struct amdgpu_virt_caps virt_caps;
314 uint32_t gim_feature;
315 uint32_t reg_access_mode;
316 int req_init_data_ver;
317 bool tdr_debug;
318 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
319 bool ras_init_done;
320 uint32_t reg_access;
321
322 /* dynamic(v2) critical regions */
323 struct amdgpu_virt_region init_data_header;
324 struct amdgpu_virt_region crit_regn;
325 struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID];
326 bool is_dynamic_crit_regn_enabled;
327
328 /* vf2pf message */
329 struct delayed_work vf2pf_work;
330 uint32_t vf2pf_update_interval_ms;
331 int vf2pf_update_retry_cnt;
332
333 /* multimedia bandwidth config */
334 bool is_mm_bw_enabled;
335 uint32_t decode_max_dimension_pixels;
336 uint32_t decode_max_frame_pixels;
337 uint32_t encode_max_dimension_pixels;
338 uint32_t encode_max_frame_pixels;
339
340 /* the ucode id to signal the autoload */
341 uint32_t autoload_ucode_id;
342
343 /* Spinlock to protect access to the RLCG register interface */
344 spinlock_t rlcg_reg_lock;
345
346 /* PTL (Performance Throttle Limiter) response from host */
347 uint32_t ptl_state;
348 uint32_t ptl_pref_format1;
349 uint32_t ptl_pref_format2;
350
351 struct mutex access_req_mutex;
352
353 union amd_sriov_ras_caps ras_en_caps;
354 union amd_sriov_ras_caps ras_telemetry_en_caps;
355 struct amdgpu_virt_ras ras;
356 struct amd_sriov_ras_telemetry_error_count count_cache;
357
358 /* hibernate and resume with different VF feature for xgmi enabled system */
359 bool is_xgmi_node_migrate_enabled;
360};
361
362struct amdgpu_video_codec_info;
363
364#define amdgpu_sriov_enabled(adev) \
365((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
366
367#define amdgpu_sriov_vf(adev) \
368((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
369
370#define amdgpu_sriov_bios(adev) \
371((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
372
373#define amdgpu_sriov_runtime(adev) \
374((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
375
376#define amdgpu_sriov_fullaccess(adev) \
377(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
378
379#define amdgpu_sriov_reg_indirect_en(adev) \
380(amdgpu_sriov_vf((adev)) && \
381 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
382
383#define amdgpu_sriov_reg_indirect_ih(adev) \
384(amdgpu_sriov_vf((adev)) && \
385 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
386
387#define amdgpu_sriov_reg_indirect_mmhub(adev) \
388(amdgpu_sriov_vf((adev)) && \
389 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
390
391#define amdgpu_sriov_reg_indirect_gc(adev) \
392(amdgpu_sriov_vf((adev)) && \
393 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
394
395#define amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev) \
396(amdgpu_sriov_vf((adev)) && \
397 ((adev)->virt.reg_access & (AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN)))
398
399#define amdgpu_sriov_rlcg_error_report_enabled(adev) \
400 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
401
402#define amdgpu_sriov_reg_access_sq_config(adev) \
403(amdgpu_sriov_vf((adev)) && \
404 ((adev)->virt.reg_access & (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG)))
405
406#define amdgpu_passthrough(adev) \
407((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
408
409#define amdgpu_sriov_vf_mmio_access_protection(adev) \
410((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
411
412#define amdgpu_sriov_ras_caps_en(adev) \
413((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS)
414
415#define amdgpu_sriov_ras_telemetry_en(adev) \
416(((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry)
417
418#define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \
419(amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk))
420
421#define amdgpu_sriov_ras_cper_en(adev) \
422((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER)
423
424#define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \
425((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK)
426
427#define amdgpu_sriov_xgmi_connected_to_cpu(adev) \
428((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU)
429
430static inline bool is_virtual_machine(void)
431{
432#if defined(CONFIG_X86)
433 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
434#elif defined(CONFIG_ARM64)
435 return !is_kernel_in_hyp_mode();
436#else
437 return false;
438#endif
439}
440
441#define amdgpu_sriov_is_pp_one_vf(adev) \
442 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
443#define amdgpu_sriov_multi_vf_mode(adev) \
444 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
445#define amdgpu_sriov_is_debug(adev) \
446 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
447#define amdgpu_sriov_is_normal(adev) \
448 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
449#define amdgpu_sriov_is_av1_support(adev) \
450 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
451#define amdgpu_sriov_is_vcn_rb_decouple(adev) \
452 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
453#define amdgpu_sriov_is_mes_info_enable(adev) \
454 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
455#define amdgpu_sriov_is_unitid_support(adev) \
456 ((adev)->virt.gim_feature & AMDGIM_FEATURE_UNITID_SUPPORT)
457#define amdgpu_sriov_ptl_support(adev) \
458 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PTL_SUPPORT)
459
460#define amdgpu_virt_xgmi_migrate_enabled(adev) \
461 ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0)
462
463bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
464void amdgpu_virt_init_setting(struct amdgpu_device *adev);
465int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
466int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
467int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
468void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
469int amdgpu_virt_ptl_request(struct amdgpu_device *adev, u32 req_code,
470 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2);
471void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev);
472int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
473int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
474void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
475bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);
476void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
477void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
478void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
479void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
480void amdgpu_virt_init(struct amdgpu_device *adev);
481
482int amdgpu_virt_init_critical_region(struct amdgpu_device *adev);
483int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev,
484 int data_id, uint8_t *binary, u32 *size);
485
486bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
487int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
488void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
489
490enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
491
492void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
493 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
494 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
495void amdgpu_sriov_wreg(struct amdgpu_device *adev,
496 u32 offset, u32 value,
497 u32 acc_flags, u32 hwip, u32 xcc_id);
498u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
499 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
500bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
501 uint32_t ucode_id);
502void amdgpu_virt_pre_reset(struct amdgpu_device *adev);
503void amdgpu_virt_post_reset(struct amdgpu_device *adev);
504bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
505bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
506 u32 acc_flags, u32 hwip,
507 bool write, u32 *rlcg_flag);
508u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
509bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);
510int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block,
511 struct ras_err_data *err_data);
512int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update);
513int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev);
514bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,
515 enum amdgpu_ras_block block);
516void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev);
517int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit);
518int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev,
519 uint64_t buf, uint32_t buf_len);
520#endif