| 1 | |
| 2 | * Copyright 2022 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 |
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| 22 |
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| 23 | #ifndef __AMDGPU_VPE_H__
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| 24 | #define __AMDGPU_VPE_H__
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| 25 |
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| 26 | #include "amdgpu_ring.h"
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| 27 | #include "amdgpu_irq.h"
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| 28 | #include "vpe_6_1_fw_if.h"
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| 29 |
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| 30 | #define AMDGPU_MAX_VPE_INSTANCES 2
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| 31 |
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| 32 | struct amdgpu_vpe;
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| 33 |
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| 34 | struct vpe_funcs {
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| 35 | uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);
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| 36 | int (*set_regs)(struct amdgpu_vpe *vpe);
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| 37 | int (*irq_init)(struct amdgpu_vpe *vpe);
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| 38 | int (*init_microcode)(struct amdgpu_vpe *vpe);
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| 39 | int (*load_microcode)(struct amdgpu_vpe *vpe);
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| 40 | int (*ring_init)(struct amdgpu_vpe *vpe);
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| 41 | int (*ring_start)(struct amdgpu_vpe *vpe);
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| 42 | int (*ring_stop)(struct amdgpu_vpe *vpe);
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| 43 | int (*ring_fini)(struct amdgpu_vpe *vpe);
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| 44 | };
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| 45 |
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| 46 | struct vpe_regs {
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| 47 | uint32_t queue0_rb_rptr_lo;
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| 48 | uint32_t queue0_rb_rptr_hi;
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| 49 | uint32_t queue0_rb_wptr_lo;
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| 50 | uint32_t queue0_rb_wptr_hi;
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| 51 | uint32_t queue0_preempt;
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| 52 |
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| 53 | uint32_t dpm_enable;
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| 54 | uint32_t dpm_pratio;
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| 55 | uint32_t dpm_request_interval;
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| 56 | uint32_t dpm_decision_threshold;
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| 57 | uint32_t dpm_busy_clamp_threshold;
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| 58 | uint32_t dpm_idle_clamp_threshold;
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| 59 | uint32_t dpm_request_lv;
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| 60 | uint32_t context_indicator;
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| 61 | };
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| 62 |
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| 63 | struct amdgpu_vpe {
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| 64 | struct amdgpu_ring ring;
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| 65 | struct amdgpu_irq_src trap_irq;
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| 66 |
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| 67 | const struct vpe_funcs *funcs;
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| 68 | struct vpe_regs regs;
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| 69 |
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| 70 | const struct firmware *fw;
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| 71 | uint32_t fw_version;
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| 72 | uint32_t feature_version;
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| 73 |
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| 74 | struct amdgpu_bo *cmdbuf_obj;
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| 75 | uint64_t cmdbuf_gpu_addr;
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| 76 | uint32_t *cmdbuf_cpu_addr;
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| 77 | struct delayed_work idle_work;
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| 78 | bool context_started;
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| 79 |
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| 80 | uint32_t num_instances;
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| 81 | bool collaborate_mode;
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| 82 | uint32_t supported_reset;
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| 83 | };
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| 84 |
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| 85 | int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);
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| 86 | int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);
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| 87 | int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);
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| 88 | int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);
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| 89 | int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);
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| 90 | void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev);
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| 91 | int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev);
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| 92 |
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| 93 | #define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ? (vpe)->funcs->ring_init((vpe)) : 0)
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| 94 | #define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ? (vpe)->funcs->ring_start((vpe)) : 0)
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| 95 | #define vpe_ring_stop(vpe) ((vpe)->funcs->ring_stop ? (vpe)->funcs->ring_stop((vpe)) : 0)
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| 96 | #define vpe_ring_fini(vpe) ((vpe)->funcs->ring_fini ? (vpe)->funcs->ring_fini((vpe)) : 0)
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| 97 |
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| 98 | #define vpe_get_reg_offset(vpe, inst, offset) \
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| 99 | ((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)
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| 100 | #define vpe_set_regs(vpe) \
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| 101 | ((vpe)->funcs->set_regs ? (vpe)->funcs->set_regs((vpe)) : 0)
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| 102 | #define vpe_irq_init(vpe) \
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| 103 | ((vpe)->funcs->irq_init ? (vpe)->funcs->irq_init((vpe)) : 0)
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| 104 | #define vpe_init_microcode(vpe) \
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| 105 | ((vpe)->funcs->init_microcode ? (vpe)->funcs->init_microcode((vpe)) : 0)
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| 106 | #define vpe_load_microcode(vpe) \
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| 107 | ((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0)
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| 108 |
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| 109 | extern const struct amdgpu_ip_block_version vpe_v6_1_ip_block;
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| 110 | extern const struct amdgpu_ip_block_version vpe_v2_0_ip_block;
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| 111 |
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| 112 | #endif
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