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1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "cikd.h"
29
30#include "bif/bif_4_1_d.h"
31#include "bif/bif_4_1_sh_mask.h"
32
33#include "oss/oss_2_0_d.h"
34#include "oss/oss_2_0_sh_mask.h"
35
36/*
37 * Interrupts
38 * Starting with r6xx, interrupts are handled via a ring buffer.
39 * Ring buffers are areas of GPU accessible memory that the GPU
40 * writes interrupt vectors into and the host reads vectors out of.
41 * There is a rptr (read pointer) that determines where the
42 * host is currently reading, and a wptr (write pointer)
43 * which determines where the GPU has written. When the
44 * pointers are equal, the ring is idle. When the GPU
45 * writes vectors to the ring buffer, it increments the
46 * wptr. When there is an interrupt, the host then starts
47 * fetching commands and processing them until the pointers are
48 * equal again at which point it updates the rptr.
49 */
50
51static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
52
53/**
54 * cik_ih_enable_interrupts - Enable the interrupt ring buffer
55 *
56 * @adev: amdgpu_device pointer
57 *
58 * Enable the interrupt ring buffer (CIK).
59 */
60static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
61{
62 u32 ih_cntl = RREG32(mmIH_CNTL);
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
64
65 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
66 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
67 WREG32(mmIH_CNTL, ih_cntl);
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
69 adev->irq.ih.enabled = true;
70}
71
72/**
73 * cik_ih_disable_interrupts - Disable the interrupt ring buffer
74 *
75 * @adev: amdgpu_device pointer
76 *
77 * Disable the interrupt ring buffer (CIK).
78 */
79static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
80{
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
82 u32 ih_cntl = RREG32(mmIH_CNTL);
83
84 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
85 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
87 WREG32(mmIH_CNTL, ih_cntl);
88 /* set rptr, wptr to 0 */
89 WREG32(mmIH_RB_RPTR, 0);
90 WREG32(mmIH_RB_WPTR, 0);
91 adev->irq.ih.enabled = false;
92 adev->irq.ih.rptr = 0;
93}
94
95/**
96 * cik_ih_irq_init - init and enable the interrupt ring
97 *
98 * @adev: amdgpu_device pointer
99 *
100 * Allocate a ring buffer for the interrupt controller,
101 * enable the RLC, disable interrupts, enable the IH
102 * ring buffer and enable it (CIK).
103 * Called at device load and reume.
104 * Returns 0 for success, errors for failure.
105 */
106static int cik_ih_irq_init(struct amdgpu_device *adev)
107{
108 struct amdgpu_ih_ring *ih = &adev->irq.ih;
109 int rb_bufsz;
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
111
112 /* disable irqs */
113 cik_ih_disable_interrupts(adev);
114
115 /* setup interrupt control */
116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
118 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
119 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
120 */
121 interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
122 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
123 interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
125
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
128
129 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
130 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
131 (rb_bufsz << 1));
132
133 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
134
135 /* set the writeback address whether it's enabled or not */
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
138
139 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
140
141 /* set rptr, wptr to 0 */
142 WREG32(mmIH_RB_RPTR, 0);
143 WREG32(mmIH_RB_WPTR, 0);
144
145 /* Default settings for IH_CNTL (disabled at first) */
146 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
147 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
148 (0 << IH_CNTL__MC_VMID__SHIFT);
149 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
150 if (adev->irq.msi_enabled)
151 ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
152 WREG32(mmIH_CNTL, ih_cntl);
153
154 pci_set_master(adev->pdev);
155
156 /* enable irqs */
157 cik_ih_enable_interrupts(adev);
158
159 if (adev->irq.ih_soft.ring_size)
160 adev->irq.ih_soft.enabled = true;
161
162 return 0;
163}
164
165/**
166 * cik_ih_irq_disable - disable interrupts
167 *
168 * @adev: amdgpu_device pointer
169 *
170 * Disable interrupts on the hw (CIK).
171 */
172static void cik_ih_irq_disable(struct amdgpu_device *adev)
173{
174 cik_ih_disable_interrupts(adev);
175 /* Wait and acknowledge irq */
176 mdelay(1);
177}
178
179/**
180 * cik_ih_get_wptr - get the IH ring buffer wptr
181 *
182 * @adev: amdgpu_device pointer
183 * @ih: IH ring buffer to fetch wptr
184 *
185 * Get the IH ring buffer wptr from either the register
186 * or the writeback memory buffer (CIK). Also check for
187 * ring buffer overflow and deal with it.
188 * Used by cik_irq_process().
189 * Returns the value of the wptr.
190 */
191static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
192 struct amdgpu_ih_ring *ih)
193{
194 u32 wptr, tmp;
195
196 wptr = le32_to_cpu(*ih->wptr_cpu);
197
198 if (ih == &adev->irq.ih_soft)
199 goto out;
200
201 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
202 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
203 /* When a ring buffer overflow happen start parsing interrupt
204 * from the last not overwritten vector (wptr + 16). Hopefully
205 * this should allow us to catchup.
206 */
207 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
208 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
209 ih->rptr = (wptr + 16) & ih->ptr_mask;
210 tmp = RREG32(mmIH_RB_CNTL);
211 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
212 WREG32(mmIH_RB_CNTL, tmp);
213
214 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
215 * can be detected.
216 */
217 tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
218 WREG32(mmIH_RB_CNTL, tmp);
219 }
220
221out:
222 return (wptr & ih->ptr_mask);
223}
224
225/* CIK IV Ring
226 * Each IV ring entry is 128 bits:
227 * [7:0] - interrupt source id
228 * [31:8] - reserved
229 * [59:32] - interrupt source data
230 * [63:60] - reserved
231 * [71:64] - RINGID
232 * CP:
233 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
234 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
235 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
236 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
237 * PIPE_ID - ME0 0=3D
238 * - ME1&2 compute dispatcher (4 pipes each)
239 * SDMA:
240 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
241 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
242 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
243 * [79:72] - VMID
244 * [95:80] - PASID
245 * [127:96] - reserved
246 */
247
248 /**
249 * cik_ih_decode_iv - decode an interrupt vector
250 *
251 * @adev: amdgpu_device pointer
252 *
253 * Decodes the interrupt vector at the current rptr
254 * position and also advance the position.
255 */
256static void cik_ih_decode_iv(struct amdgpu_device *adev,
257 struct amdgpu_ih_ring *ih,
258 struct amdgpu_iv_entry *entry)
259{
260 /* wptr/rptr are in bytes! */
261 u32 ring_index = ih->rptr >> 2;
262 uint32_t dw[4];
263
264 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
265 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
266 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
267 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
268
269 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
270 entry->src_id = dw[0] & 0xff;
271 entry->src_data[0] = dw[1] & 0xfffffff;
272 entry->ring_id = dw[2] & 0xff;
273 entry->vmid = (dw[2] >> 8) & 0xff;
274 entry->pasid = (dw[2] >> 16) & 0xffff;
275
276 /* wptr/rptr are in bytes! */
277 ih->rptr += 16;
278}
279
280/**
281 * cik_ih_set_rptr - set the IH ring buffer rptr
282 *
283 * @adev: amdgpu_device pointer
284 * @ih: IH ring buffer to set wptr
285 *
286 * Set the IH ring buffer rptr.
287 */
288static void cik_ih_set_rptr(struct amdgpu_device *adev,
289 struct amdgpu_ih_ring *ih)
290{
291 WREG32(mmIH_RB_RPTR, ih->rptr);
292}
293
294static int cik_ih_early_init(struct amdgpu_ip_block *ip_block)
295{
296 struct amdgpu_device *adev = ip_block->adev;
297 int ret;
298
299 ret = amdgpu_irq_add_domain(adev);
300 if (ret)
301 return ret;
302
303 cik_ih_set_interrupt_funcs(adev);
304
305 return 0;
306}
307
308static int cik_ih_sw_init(struct amdgpu_ip_block *ip_block)
309{
310 int r;
311 struct amdgpu_device *adev = ip_block->adev;
312
313 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
314 if (r)
315 return r;
316
317 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
318 if (r)
319 return r;
320
321 r = amdgpu_irq_init(adev);
322
323 return r;
324}
325
326static int cik_ih_sw_fini(struct amdgpu_ip_block *ip_block)
327{
328 struct amdgpu_device *adev = ip_block->adev;
329
330 amdgpu_irq_fini_sw(adev);
331 amdgpu_irq_remove_domain(adev);
332
333 return 0;
334}
335
336static int cik_ih_hw_init(struct amdgpu_ip_block *ip_block)
337{
338 struct amdgpu_device *adev = ip_block->adev;
339
340 return cik_ih_irq_init(adev);
341}
342
343static int cik_ih_hw_fini(struct amdgpu_ip_block *ip_block)
344{
345 cik_ih_irq_disable(ip_block->adev);
346
347 return 0;
348}
349
350static int cik_ih_suspend(struct amdgpu_ip_block *ip_block)
351{
352 return cik_ih_hw_fini(ip_block);
353}
354
355static int cik_ih_resume(struct amdgpu_ip_block *ip_block)
356{
357 return cik_ih_hw_init(ip_block);
358}
359
360static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)
361{
362 struct amdgpu_device *adev = ip_block->adev;
363 u32 tmp = RREG32(mmSRBM_STATUS);
364
365 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
366 return false;
367
368 return true;
369}
370
371static int cik_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
372{
373 unsigned i;
374 u32 tmp;
375 struct amdgpu_device *adev = ip_block->adev;
376
377 for (i = 0; i < adev->usec_timeout; i++) {
378 /* read MC_STATUS */
379 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
380 if (!tmp)
381 return 0;
382 udelay(1);
383 }
384 return -ETIMEDOUT;
385}
386
387static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block)
388{
389 struct amdgpu_device *adev = ip_block->adev;
390
391 u32 srbm_soft_reset = 0;
392 u32 tmp = RREG32(mmSRBM_STATUS);
393
394 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
395 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
396
397 if (srbm_soft_reset) {
398 tmp = RREG32(mmSRBM_SOFT_RESET);
399 tmp |= srbm_soft_reset;
400 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
401 WREG32(mmSRBM_SOFT_RESET, tmp);
402 tmp = RREG32(mmSRBM_SOFT_RESET);
403
404 udelay(50);
405
406 tmp &= ~srbm_soft_reset;
407 WREG32(mmSRBM_SOFT_RESET, tmp);
408 tmp = RREG32(mmSRBM_SOFT_RESET);
409
410 /* Wait a little for things to settle down */
411 udelay(50);
412 }
413
414 return 0;
415}
416
417static int cik_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
418 enum amd_clockgating_state state)
419{
420 return 0;
421}
422
423static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
424 enum amd_powergating_state state)
425{
426 return 0;
427}
428
429static const struct amd_ip_funcs cik_ih_ip_funcs = {
430 .name = "cik_ih",
431 .early_init = cik_ih_early_init,
432 .sw_init = cik_ih_sw_init,
433 .sw_fini = cik_ih_sw_fini,
434 .hw_init = cik_ih_hw_init,
435 .hw_fini = cik_ih_hw_fini,
436 .suspend = cik_ih_suspend,
437 .resume = cik_ih_resume,
438 .is_idle = cik_ih_is_idle,
439 .wait_for_idle = cik_ih_wait_for_idle,
440 .soft_reset = cik_ih_soft_reset,
441 .set_clockgating_state = cik_ih_set_clockgating_state,
442 .set_powergating_state = cik_ih_set_powergating_state,
443};
444
445static const struct amdgpu_ih_funcs cik_ih_funcs = {
446 .get_wptr = cik_ih_get_wptr,
447 .decode_iv = cik_ih_decode_iv,
448 .set_rptr = cik_ih_set_rptr
449};
450
451static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
452{
453 adev->irq.ih_funcs = &cik_ih_funcs;
454}
455
456const struct amdgpu_ip_block_version cik_ih_ip_block = {
457 .type = AMD_IP_BLOCK_TYPE_IH,
458 .major = 2,
459 .minor = 0,
460 .rev = 0,
461 .funcs = &cik_ih_ip_funcs,
462};