| 1 | |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 | * Authors: Alex Deucher
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| 23 |
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| 24 | #ifndef CIK_H
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| 25 | #define CIK_H
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| 26 |
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| 27 | #define MC_SEQ_MISC0__MT__MASK 0xf0000000
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| 28 | #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
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| 29 | #define MC_SEQ_MISC0__MT__DDR2 0x20000000
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| 30 | #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
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| 31 | #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
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| 32 | #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
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| 33 | #define MC_SEQ_MISC0__MT__HBM 0x60000000
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| 34 | #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
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| 35 |
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| 36 | #define CP_ME_TABLE_SIZE 96
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| 37 |
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| 38 |
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| 39 | #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
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| 40 | #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
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| 41 | #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c)
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| 42 | #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c)
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| 43 | #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c)
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| 44 | #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c)
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| 45 |
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| 46 |
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| 47 | #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
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| 48 | #define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
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| 49 | #define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
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| 50 | #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
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| 51 | #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
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| 52 | #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
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| 53 |
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| 54 |
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| 55 | #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
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| 56 | #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
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| 57 | #define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
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| 58 | #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
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| 59 | #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
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| 60 | #define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
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| 61 | #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
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| 62 |
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| 63 | #define PIPEID(x) ((x) << 0)
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| 64 | #define MEID(x) ((x) << 2)
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| 65 | #define VMID(x) ((x) << 4)
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| 66 | #define QUEUEID(x) ((x) << 8)
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| 67 |
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| 68 | #define mmCC_DRM_ID_STRAPS 0x1559
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| 69 | #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
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| 70 |
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| 71 | #define mmCHUB_CONTROL 0x619
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| 72 | #define BYPASS_VM (1 << 0)
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| 73 |
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| 74 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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| 75 |
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| 76 | #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02
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| 77 | #define LUT_10BIT_BYPASS_EN (1 << 8)
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| 78 |
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| 79 | # define CURSOR_MONO 0
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| 80 | # define CURSOR_24_1 1
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| 81 | # define CURSOR_24_8_PRE_MULT 2
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| 82 | # define CURSOR_24_8_UNPRE_MULT 3
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| 83 | # define CURSOR_URGENT_ALWAYS 0
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| 84 | # define CURSOR_URGENT_1_8 1
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| 85 | # define CURSOR_URGENT_1_4 2
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| 86 | # define CURSOR_URGENT_3_8 3
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| 87 | # define CURSOR_URGENT_1_2 4
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| 88 |
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| 89 | # define GRPH_DEPTH_8BPP 0
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| 90 | # define GRPH_DEPTH_16BPP 1
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| 91 | # define GRPH_DEPTH_32BPP 2
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| 92 |
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| 93 | # define GRPH_FORMAT_INDEXED 0
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| 94 |
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| 95 | # define GRPH_FORMAT_ARGB1555 0
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| 96 | # define GRPH_FORMAT_ARGB565 1
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| 97 | # define GRPH_FORMAT_ARGB4444 2
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| 98 | # define GRPH_FORMAT_AI88 3
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| 99 | # define GRPH_FORMAT_MONO16 4
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| 100 | # define GRPH_FORMAT_BGRA5551 5
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| 101 |
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| 102 | # define GRPH_FORMAT_ARGB8888 0
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| 103 | # define GRPH_FORMAT_ARGB2101010 1
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| 104 | # define GRPH_FORMAT_32BPP_DIG 2
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| 105 | # define GRPH_FORMAT_8B_ARGB2101010 3
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| 106 | # define GRPH_FORMAT_BGRA1010102 4
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| 107 | # define GRPH_FORMAT_8B_BGRA1010102 5
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| 108 | # define GRPH_FORMAT_RGB111110 6
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| 109 | # define GRPH_FORMAT_BGR101111 7
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| 110 | # define ADDR_SURF_MACRO_TILE_ASPECT_1 0
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| 111 | # define ADDR_SURF_MACRO_TILE_ASPECT_2 1
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| 112 | # define ADDR_SURF_MACRO_TILE_ASPECT_4 2
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| 113 | # define ADDR_SURF_MACRO_TILE_ASPECT_8 3
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| 114 | # define GRPH_ARRAY_LINEAR_GENERAL 0
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| 115 | # define GRPH_ARRAY_LINEAR_ALIGNED 1
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| 116 | # define GRPH_ARRAY_1D_TILED_THIN1 2
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| 117 | # define GRPH_ARRAY_2D_TILED_THIN1 4
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| 118 | # define DISPLAY_MICRO_TILING 0
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| 119 | # define THIN_MICRO_TILING 1
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| 120 | # define DEPTH_MICRO_TILING 2
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| 121 | # define ROTATED_MICRO_TILING 4
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| 122 | # define GRPH_ENDIAN_NONE 0
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| 123 | # define GRPH_ENDIAN_8IN16 1
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| 124 | # define GRPH_ENDIAN_8IN32 2
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| 125 | # define GRPH_ENDIAN_8IN64 3
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| 126 | # define GRPH_RED_SEL_R 0
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| 127 | # define GRPH_RED_SEL_G 1
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| 128 | # define GRPH_RED_SEL_B 2
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| 129 | # define GRPH_RED_SEL_A 3
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| 130 | # define GRPH_GREEN_SEL_G 0
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| 131 | # define GRPH_GREEN_SEL_B 1
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| 132 | # define GRPH_GREEN_SEL_A 2
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| 133 | # define GRPH_GREEN_SEL_R 3
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| 134 | # define GRPH_BLUE_SEL_B 0
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| 135 | # define GRPH_BLUE_SEL_A 1
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| 136 | # define GRPH_BLUE_SEL_R 2
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| 137 | # define GRPH_BLUE_SEL_G 3
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| 138 | # define GRPH_ALPHA_SEL_A 0
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| 139 | # define GRPH_ALPHA_SEL_R 1
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| 140 | # define GRPH_ALPHA_SEL_G 2
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| 141 | # define GRPH_ALPHA_SEL_B 3
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| 142 | # define INPUT_GAMMA_USE_LUT 0
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| 143 | # define INPUT_GAMMA_BYPASS 1
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| 144 | # define INPUT_GAMMA_SRGB_24 2
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| 145 | # define INPUT_GAMMA_XVYCC_222 3
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| 146 |
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| 147 | # define INPUT_CSC_BYPASS 0
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| 148 | # define INPUT_CSC_PROG_COEFF 1
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| 149 | # define INPUT_CSC_PROG_SHARED_MATRIXA 2
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| 150 |
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| 151 | # define OUTPUT_CSC_BYPASS 0
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| 152 | # define OUTPUT_CSC_TV_RGB 1
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| 153 | # define OUTPUT_CSC_YCBCR_601 2
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| 154 | # define OUTPUT_CSC_YCBCR_709 3
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| 155 | # define OUTPUT_CSC_PROG_COEFF 4
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| 156 | # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5
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| 157 |
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| 158 | # define DEGAMMA_BYPASS 0
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| 159 | # define DEGAMMA_SRGB_24 1
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| 160 | # define DEGAMMA_XVYCC_222 2
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| 161 | # define GAMUT_REMAP_BYPASS 0
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| 162 | # define GAMUT_REMAP_PROG_COEFF 1
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| 163 | # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2
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| 164 | # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3
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| 165 |
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| 166 | # define REGAMMA_BYPASS 0
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| 167 | # define REGAMMA_SRGB_24 1
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| 168 | # define REGAMMA_XVYCC_222 2
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| 169 | # define REGAMMA_PROG_A 3
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| 170 | # define REGAMMA_PROG_B 4
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| 171 |
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| 172 | # define FMT_CLAMP_6BPC 0
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| 173 | # define FMT_CLAMP_8BPC 1
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| 174 | # define FMT_CLAMP_10BPC 2
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| 175 |
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| 176 | # define HDMI_24BIT_DEEP_COLOR 0
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| 177 | # define HDMI_30BIT_DEEP_COLOR 1
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| 178 | # define HDMI_36BIT_DEEP_COLOR 2
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| 179 | # define HDMI_ACR_HW 0
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| 180 | # define HDMI_ACR_32 1
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| 181 | # define HDMI_ACR_44 2
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| 182 | # define HDMI_ACR_48 3
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| 183 | # define HDMI_ACR_X1 1
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| 184 | # define HDMI_ACR_X2 2
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| 185 | # define HDMI_ACR_X4 4
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| 186 | # define AFMT_AVI_INFO_Y_RGB 0
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| 187 | # define AFMT_AVI_INFO_Y_YCBCR422 1
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| 188 | # define AFMT_AVI_INFO_Y_YCBCR444 2
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| 189 |
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| 190 | #define NO_AUTO 0
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| 191 | #define ES_AUTO 1
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| 192 | #define GS_AUTO 2
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| 193 | #define ES_AND_GS_AUTO 3
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| 194 |
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| 195 | # define ARRAY_MODE(x) ((x) << 2)
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| 196 | # define PIPE_CONFIG(x) ((x) << 6)
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| 197 | # define TILE_SPLIT(x) ((x) << 11)
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| 198 | # define MICRO_TILE_MODE_NEW(x) ((x) << 22)
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| 199 | # define SAMPLE_SPLIT(x) ((x) << 25)
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| 200 | # define BANK_WIDTH(x) ((x) << 0)
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| 201 | # define BANK_HEIGHT(x) ((x) << 2)
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| 202 | # define MACRO_TILE_ASPECT(x) ((x) << 4)
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| 203 | # define NUM_BANKS(x) ((x) << 6)
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| 204 |
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| 205 | #define MSG_ENTER_RLC_SAFE_MODE 1
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| 206 | #define MSG_EXIT_RLC_SAFE_MODE 0
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| 207 |
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| 208 | |
| 209 | * PM4
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| 210 |
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| 211 | #define PACKET_TYPE0 0
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| 212 | #define PACKET_TYPE1 1
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| 213 | #define PACKET_TYPE2 2
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| 214 | #define PACKET_TYPE3 3
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| 215 |
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| 216 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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| 217 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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| 218 | #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
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| 219 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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| 220 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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| 221 | ((reg) & 0xFFFF) | \
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| 222 | ((n) & 0x3FFF) << 16)
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| 223 | #define CP_PACKET2 0x80000000
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| 224 | #define PACKET2_PAD_SHIFT 0
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| 225 | #define PACKET2_PAD_MASK (0x3fffffff << 0)
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| 226 |
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| 227 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| 228 |
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| 229 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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| 230 | (((op) & 0xFF) << 8) | \
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| 231 | ((n) & 0x3FFF) << 16)
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| 232 |
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| 233 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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| 234 |
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| 235 |
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| 236 | #define PACKET3_NOP 0x10
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| 237 | #define PACKET3_SET_BASE 0x11
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| 238 | #define PACKET3_BASE_INDEX(x) ((x) << 0)
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| 239 | #define CE_PARTITION_BASE 3
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| 240 | #define PACKET3_CLEAR_STATE 0x12
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| 241 | #define PACKET3_INDEX_BUFFER_SIZE 0x13
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| 242 | #define PACKET3_DISPATCH_DIRECT 0x15
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| 243 | #define PACKET3_DISPATCH_INDIRECT 0x16
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| 244 | #define PACKET3_ATOMIC_GDS 0x1D
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| 245 | #define PACKET3_ATOMIC_MEM 0x1E
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| 246 | #define PACKET3_OCCLUSION_QUERY 0x1F
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| 247 | #define PACKET3_SET_PREDICATION 0x20
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| 248 | #define PACKET3_REG_RMW 0x21
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| 249 | #define PACKET3_COND_EXEC 0x22
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| 250 | #define PACKET3_PRED_EXEC 0x23
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| 251 | #define PACKET3_DRAW_INDIRECT 0x24
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| 252 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25
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| 253 | #define PACKET3_INDEX_BASE 0x26
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| 254 | #define PACKET3_DRAW_INDEX_2 0x27
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| 255 | #define PACKET3_CONTEXT_CONTROL 0x28
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| 256 | #define PACKET3_INDEX_TYPE 0x2A
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| 257 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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| 258 | #define PACKET3_DRAW_INDEX_AUTO 0x2D
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| 259 | #define PACKET3_NUM_INSTANCES 0x2F
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| 260 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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| 261 | #define PACKET3_INDIRECT_BUFFER_CONST 0x33
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| 262 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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| 263 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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| 264 | #define PACKET3_DRAW_PREAMBLE 0x36
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| 265 | #define PACKET3_WRITE_DATA 0x37
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| 266 | #define WRITE_DATA_DST_SEL(x) ((x) << 8)
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| 267 | |
| 268 | * 1 - memory (sync - via GRBM)
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| 269 | * 2 - gl2
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| 270 | * 3 - gds
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| 271 | * 4 - reserved
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| 272 | * 5 - memory (async - direct)
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| 273 |
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| 274 | #define WR_ONE_ADDR (1 << 16)
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| 275 | #define WR_CONFIRM (1 << 20)
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| 276 | #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
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| 277 | |
| 278 | * 1 - Stream
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| 279 |
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| 280 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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| 281 | |
| 282 | * 1 - pfp
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| 283 | * 2 - ce
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| 284 |
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| 285 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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| 286 | #define PACKET3_MEM_SEMAPHORE 0x39
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| 287 | # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
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| 288 | # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20)
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| 289 | # define PACKET3_SEM_CLIENT_CODE ((x) << 24)
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| 290 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
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| 291 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
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| 292 | #define PACKET3_COPY_DW 0x3B
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| 293 | #define PACKET3_WAIT_REG_MEM 0x3C
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| 294 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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| 295 | |
| 296 | * 1 - <
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| 297 | * 2 - <=
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| 298 | * 3 - ==
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| 299 | * 4 - !=
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| 300 | * 5 - >=
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| 301 | * 6 - >
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| 302 |
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| 303 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
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| 304 | |
| 305 | * 1 - mem
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| 306 |
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| 307 | #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
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| 308 | |
| 309 | * 1 - wr_wait_wr_reg
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| 310 |
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| 311 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
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| 312 | |
| 313 | * 1 - pfp
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| 314 |
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| 315 | #define PACKET3_INDIRECT_BUFFER 0x3F
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| 316 | #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
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| 317 | #define INDIRECT_BUFFER_VALID (1 << 23)
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| 318 | #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
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| 319 | |
| 320 | * 1 - Stream
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| 321 | * 2 - Bypass
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| 322 |
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| 323 | #define PACKET3_COPY_DATA 0x40
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| 324 | #define PACKET3_PFP_SYNC_ME 0x42
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| 325 | #define PACKET3_SURFACE_SYNC 0x43
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| 326 | # define PACKET3_DEST_BASE_0_ENA (1 << 0)
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| 327 | # define PACKET3_DEST_BASE_1_ENA (1 << 1)
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| 328 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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| 329 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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| 330 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
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| 331 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
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| 332 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
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| 333 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
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| 334 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
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| 335 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
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| 336 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
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| 337 | # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
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| 338 | # define PACKET3_TC_VOL_ACTION_ENA (1 << 16)
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| 339 | # define PACKET3_TC_WB_ACTION_ENA (1 << 18)
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| 340 | # define PACKET3_DEST_BASE_2_ENA (1 << 19)
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| 341 | # define PACKET3_DEST_BASE_3_ENA (1 << 21)
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| 342 | # define PACKET3_TCL1_ACTION_ENA (1 << 22)
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| 343 | # define PACKET3_TC_ACTION_ENA (1 << 23)
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| 344 | # define PACKET3_CB_ACTION_ENA (1 << 25)
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| 345 | # define PACKET3_DB_ACTION_ENA (1 << 26)
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| 346 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
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| 347 | # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
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| 348 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
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| 349 | #define PACKET3_COND_WRITE 0x45
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| 350 | #define PACKET3_EVENT_WRITE 0x46
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| 351 | #define EVENT_TYPE(x) ((x) << 0)
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| 352 | #define EVENT_INDEX(x) ((x) << 8)
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| 353 | |
| 354 | * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
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| 355 | * 2 - SAMPLE_PIPELINESTAT
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| 356 | * 3 - SAMPLE_STREAMOUTSTAT*
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| 357 | * 4 - *S_PARTIAL_FLUSH
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| 358 | * 5 - EOP events
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| 359 | * 6 - EOS events
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| 360 |
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| 361 | #define PACKET3_EVENT_WRITE_EOP 0x47
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| 362 | #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
|
| 363 | #define EOP_TC_VOL_ACTION_EN (1 << 13)
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| 364 | #define EOP_TC_WB_ACTION_EN (1 << 15)
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| 365 | #define EOP_TCL1_ACTION_EN (1 << 16)
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| 366 | #define EOP_TC_ACTION_EN (1 << 17)
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| 367 | #define EOP_TCL2_VOLATILE (1 << 24)
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| 368 | #define EOP_CACHE_POLICY(x) ((x) << 25)
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| 369 | |
| 370 | * 1 - Stream
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| 371 | * 2 - Bypass
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| 372 |
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| 373 | #define EOP_EXEC (1 << 28)
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| 374 | #define DATA_SEL(x) ((x) << 29)
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| 375 | |
| 376 | * 1 - send low 32bit data
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| 377 | * 2 - send 64bit data
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| 378 | * 3 - send 64bit GPU counter value
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| 379 | * 4 - send 64bit sys counter value
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| 380 |
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| 381 | #define INT_SEL(x) ((x) << 24)
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| 382 | |
| 383 | * 1 - interrupt only (DATA_SEL = 0)
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| 384 | * 2 - interrupt when data write is confirmed
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| 385 |
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| 386 | #define DST_SEL(x) ((x) << 16)
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| 387 | |
| 388 | * 1 - TC/L2
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| 389 |
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| 390 | #define PACKET3_EVENT_WRITE_EOS 0x48
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| 391 | #define PACKET3_RELEASE_MEM 0x49
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| 392 | #define PACKET3_PREAMBLE_CNTL 0x4A
|
| 393 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
|
| 394 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
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| 395 | #define PACKET3_DMA_DATA 0x50
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| 396 | |
| 397 | * 2. CONTROL
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| 398 | * 3. SRC_ADDR_LO or DATA [31:0]
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| 399 | * 4. SRC_ADDR_HI [31:0]
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| 400 | * 5. DST_ADDR_LO [31:0]
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| 401 | * 6. DST_ADDR_HI [7:0]
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| 402 | * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
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| 403 |
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| 404 |
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| 405 | # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
|
| 406 | |
| 407 | * 1 - PFP
|
| 408 |
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| 409 | # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
|
| 410 | |
| 411 | * 1 - Stream
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| 412 | * 2 - Bypass
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| 413 |
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| 414 | # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
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| 415 | # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
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| 416 | |
| 417 | * 1 - GDS
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| 418 | * 3 - DST_ADDR using L2
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| 419 |
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| 420 | # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
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| 421 | |
| 422 | * 1 - Stream
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| 423 | * 2 - Bypass
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| 424 |
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| 425 | # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
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| 426 | # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
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| 427 | |
| 428 | * 1 - GDS
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| 429 | * 2 - DATA
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| 430 | * 3 - SRC_ADDR using L2
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| 431 |
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| 432 | # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
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| 433 |
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| 434 | # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
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| 435 | # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
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| 436 | |
| 437 | * 1 - 8 in 16
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| 438 | * 2 - 8 in 32
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| 439 | * 3 - 8 in 64
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| 440 |
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| 441 | # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
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| 442 | |
| 443 | * 1 - 8 in 16
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| 444 | * 2 - 8 in 32
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| 445 | * 3 - 8 in 64
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| 446 |
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| 447 | # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
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| 448 | |
| 449 | * 1 - register
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| 450 |
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| 451 | # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
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| 452 | |
| 453 | * 1 - register
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| 454 |
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| 455 | # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
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| 456 | # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
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| 457 | # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
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| 458 | #define PACKET3_ACQUIRE_MEM 0x58
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| 459 | #define PACKET3_REWIND 0x59
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| 460 | #define PACKET3_LOAD_UCONFIG_REG 0x5E
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| 461 | #define PACKET3_LOAD_SH_REG 0x5F
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| 462 | #define PACKET3_LOAD_CONFIG_REG 0x60
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| 463 | #define PACKET3_LOAD_CONTEXT_REG 0x61
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| 464 | #define PACKET3_SET_CONFIG_REG 0x68
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| 465 | #define PACKET3_SET_CONFIG_REG_START 0x00002000
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| 466 | #define PACKET3_SET_CONFIG_REG_END 0x00002c00
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| 467 | #define PACKET3_SET_CONTEXT_REG 0x69
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| 468 | #define PACKET3_SET_CONTEXT_REG_START 0x0000a000
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| 469 | #define PACKET3_SET_CONTEXT_REG_END 0x0000a400
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| 470 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
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| 471 | #define PACKET3_SET_SH_REG 0x76
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| 472 | #define PACKET3_SET_SH_REG_START 0x00002c00
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| 473 | #define PACKET3_SET_SH_REG_END 0x00003000
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| 474 | #define PACKET3_SET_SH_REG_OFFSET 0x77
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| 475 | #define PACKET3_SET_QUEUE_REG 0x78
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| 476 | #define PACKET3_SET_UCONFIG_REG 0x79
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| 477 | #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
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| 478 | #define PACKET3_SET_UCONFIG_REG_END 0x0000c400
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| 479 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D
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| 480 | #define PACKET3_SCRATCH_RAM_READ 0x7E
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| 481 | #define PACKET3_LOAD_CONST_RAM 0x80
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| 482 | #define PACKET3_WRITE_CONST_RAM 0x81
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| 483 | #define PACKET3_DUMP_CONST_RAM 0x83
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| 484 | #define PACKET3_INCREMENT_CE_COUNTER 0x84
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| 485 | #define PACKET3_INCREMENT_DE_COUNTER 0x85
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| 486 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86
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| 487 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
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| 488 | #define PACKET3_SWITCH_BUFFER 0x8B
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| 489 |
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| 490 |
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| 491 | #define SDMA0_REGISTER_OFFSET 0x0
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| 492 | #define SDMA1_REGISTER_OFFSET 0x200
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| 493 | #define SDMA_MAX_INSTANCE 2
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| 494 |
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| 495 | #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
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| 496 | (((sub_op) & 0xFF) << 8) | \
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| 497 | (((op) & 0xFF) << 0))
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| 498 |
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| 499 | #define SDMA_OPCODE_NOP 0
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| 500 | # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16)
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| 501 | #define SDMA_OPCODE_COPY 1
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| 502 | # define SDMA_COPY_SUB_OPCODE_LINEAR 0
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| 503 | # define SDMA_COPY_SUB_OPCODE_TILED 1
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| 504 | # define SDMA_COPY_SUB_OPCODE_SOA 3
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| 505 | # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
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| 506 | # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
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| 507 | # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
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| 508 | #define SDMA_OPCODE_WRITE 2
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| 509 | # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
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| 510 | # define SDMA_WRITE_SUB_OPCODE_TILED 1
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| 511 | #define SDMA_OPCODE_INDIRECT_BUFFER 4
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| 512 | #define SDMA_OPCODE_FENCE 5
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| 513 | #define SDMA_OPCODE_TRAP 6
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| 514 | #define SDMA_OPCODE_SEMAPHORE 7
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| 515 | # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
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| 516 | |
| 517 | * 1 - write 1
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| 518 |
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| 519 | # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
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| 520 | |
| 521 | * 1 - signal
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| 522 |
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| 523 | # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
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| 524 |
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| 525 | #define SDMA_OPCODE_POLL_REG_MEM 8
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| 526 | # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
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| 527 | |
| 528 | * 1 - wr_wait_wr_reg
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| 529 |
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| 530 | # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
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| 531 | |
| 532 | * 1 - <
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| 533 | * 2 - <=
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| 534 | * 3 - ==
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| 535 | * 4 - !=
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| 536 | * 5 - >=
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| 537 | * 6 - >
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| 538 |
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| 539 | # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
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| 540 | |
| 541 | * 1 = memory
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| 542 |
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| 543 | #define SDMA_OPCODE_COND_EXEC 9
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| 544 | #define SDMA_OPCODE_CONSTANT_FILL 11
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| 545 | # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
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| 546 | |
| 547 | * 2 = DW fill
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| 548 |
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| 549 | #define SDMA_OPCODE_GENERATE_PTE_PDE 12
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| 550 | #define SDMA_OPCODE_TIMESTAMP 13
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| 551 | # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
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| 552 | # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
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| 553 | # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
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| 554 | #define SDMA_OPCODE_SRBM_WRITE 14
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| 555 | # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
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| 556 |
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| 557 |
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| 558 | #define VCE_CMD_NO_OP 0x00000000
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| 559 | #define VCE_CMD_END 0x00000001
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| 560 | #define VCE_CMD_IB 0x00000002
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| 561 | #define VCE_CMD_FENCE 0x00000003
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| 562 | #define VCE_CMD_TRAP 0x00000004
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| 563 | #define VCE_CMD_IB_AUTO 0x00000005
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| 564 | #define VCE_CMD_SEMAPHORE 0x00000006
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| 565 |
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| 566 |
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| 567 | #define PRIVATE_BASE(x) ((x) << 0)
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| 568 | #define SHARED_BASE(x) ((x) << 16)
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| 569 |
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| 570 | #define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL)
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| 571 |
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| 572 |
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| 573 | enum {
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| 574 | MTYPE_CACHED = 0,
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| 575 | MTYPE_NONCACHED = 3
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| 576 | };
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| 577 |
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| 578 |
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| 579 | #define RB_MAP_PKR0(x) ((x) << 0)
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| 580 | #define RB_MAP_PKR0_MASK (0x3 << 0)
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| 581 | #define RB_MAP_PKR1(x) ((x) << 2)
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| 582 | #define RB_MAP_PKR1_MASK (0x3 << 2)
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| 583 | #define RB_XSEL2(x) ((x) << 4)
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| 584 | #define RB_XSEL2_MASK (0x3 << 4)
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| 585 | #define RB_XSEL (1 << 6)
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| 586 | #define RB_YSEL (1 << 7)
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| 587 | #define PKR_MAP(x) ((x) << 8)
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| 588 | #define PKR_MAP_MASK (0x3 << 8)
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| 589 | #define PKR_XSEL(x) ((x) << 10)
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| 590 | #define PKR_XSEL_MASK (0x3 << 10)
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| 591 | #define PKR_YSEL(x) ((x) << 12)
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| 592 | #define PKR_YSEL_MASK (0x3 << 12)
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| 593 | #define SC_MAP(x) ((x) << 16)
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| 594 | #define SC_MAP_MASK (0x3 << 16)
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| 595 | #define SC_XSEL(x) ((x) << 18)
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| 596 | #define SC_XSEL_MASK (0x3 << 18)
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| 597 | #define SC_YSEL(x) ((x) << 20)
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| 598 | #define SC_YSEL_MASK (0x3 << 20)
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| 599 | #define SE_MAP(x) ((x) << 24)
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| 600 | #define SE_MAP_MASK (0x3 << 24)
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| 601 | #define SE_XSEL(x) ((x) << 26)
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| 602 | #define SE_XSEL_MASK (0x3 << 26)
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| 603 | #define SE_YSEL(x) ((x) << 28)
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| 604 | #define SE_YSEL_MASK (0x3 << 28)
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| 605 |
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| 606 |
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| 607 | #define SE_PAIR_MAP(x) ((x) << 0)
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| 608 | #define SE_PAIR_MAP_MASK (0x3 << 0)
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| 609 | #define SE_PAIR_XSEL(x) ((x) << 2)
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| 610 | #define SE_PAIR_XSEL_MASK (0x3 << 2)
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| 611 | #define SE_PAIR_YSEL(x) ((x) << 4)
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| 612 | #define SE_PAIR_YSEL_MASK (0x3 << 4)
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| 613 |
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| 614 | #endif
|