| 1 | |
| 2 | * Copyright 2011 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 | * Authors: Alex Deucher
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| 23 |
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| 24 | #ifndef SI_H
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| 25 | #define SI_H
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| 26 |
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| 27 | #define SI_MAX_CTLACKS_ASSERTION_WAIT 100
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| 28 |
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| 29 |
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| 30 | #define SMC_CG_IND_START 0xc0030000
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| 31 | #define SMC_CG_IND_END 0xc0040000
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| 32 |
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| 33 |
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| 34 | #define SMC_SYSCON_RESET_CNTL 0x80000000
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| 35 | # define RST_REG (1 << 0)
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| 36 | #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
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| 37 | # define CK_DISABLE (1 << 0)
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| 38 | # define CKEN (1 << 24)
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| 39 |
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| 40 | #define DCCG_DISP_SLOW_SELECT_REG 0x13F
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| 41 | #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
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| 42 | #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
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| 43 | #define DCCG_DISP1_SLOW_SELECT_SHIFT 0
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| 44 | #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
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| 45 | #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
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| 46 | #define DCCG_DISP2_SLOW_SELECT_SHIFT 4
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| 47 |
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| 48 |
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| 49 | #define CG_UPLL_FUNC_CNTL 0x18d
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| 50 | # define UPLL_RESET_MASK 0x00000001
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| 51 | # define UPLL_SLEEP_MASK 0x00000002
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| 52 | # define UPLL_BYPASS_EN_MASK 0x00000004
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| 53 | # define UPLL_CTLREQ_MASK 0x00000008
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| 54 | # define UPLL_VCO_MODE_MASK 0x00000600
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| 55 | # define UPLL_REF_DIV_MASK 0x003F0000
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| 56 | # define UPLL_CTLACK_MASK 0x40000000
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| 57 | # define UPLL_CTLACK2_MASK 0x80000000
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| 58 | #define CG_UPLL_FUNC_CNTL_2 0x18e
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| 59 | # define UPLL_PDIV_A(x) ((x) << 0)
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| 60 | # define UPLL_PDIV_A_MASK 0x0000007F
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| 61 | # define UPLL_PDIV_B(x) ((x) << 8)
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| 62 | # define UPLL_PDIV_B_MASK 0x00007F00
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| 63 | # define VCLK_SRC_SEL(x) ((x) << 20)
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| 64 | # define VCLK_SRC_SEL_MASK 0x01F00000
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| 65 | # define DCLK_SRC_SEL(x) ((x) << 25)
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| 66 | # define DCLK_SRC_SEL_MASK 0x3E000000
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| 67 | #define CG_UPLL_FUNC_CNTL_3 0x18f
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| 68 | # define UPLL_FB_DIV(x) ((x) << 0)
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| 69 | # define UPLL_FB_DIV_MASK 0x01FFFFFF
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| 70 | #define CG_UPLL_FUNC_CNTL_4 0x191
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| 71 | # define UPLL_SPARE_ISPARE9 0x00020000
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| 72 | #define CG_UPLL_FUNC_CNTL_5 0x192
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| 73 | # define RESET_ANTI_MUX_MASK 0x00000200
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| 74 | #define CG_UPLL_SPREAD_SPECTRUM 0x194
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| 75 | # define SSEN_MASK 0x00000001
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| 76 |
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| 77 | #define VM_INVALIDATE_REQUEST 0x51E
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| 78 | #define VM_INVALIDATE_RESPONSE 0x51F
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| 79 |
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| 80 | #define VM_L2_CG 0x570
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| 81 | #define MC_CG_ENABLE (1 << 18)
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| 82 | #define MC_LS_ENABLE (1 << 19)
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| 83 |
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| 84 | #define MC_VM_FB_LOCATION 0x809
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| 85 | #define MC_VM_AGP_TOP 0x80A
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| 86 | #define MC_VM_AGP_BOT 0x80B
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| 87 | #define MC_VM_AGP_BASE 0x80C
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| 88 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D
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| 89 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E
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| 90 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F
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| 91 |
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| 92 | #define MC_VM_MX_L1_TLB_CNTL 0x819
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| 93 | #define ENABLE_L1_TLB (1 << 0)
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| 94 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
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| 95 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
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| 96 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
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| 97 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
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| 98 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
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| 99 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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| 100 | #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
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| 101 |
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| 102 | #define MC_SHARED_BLACKOUT_CNTL 0x82B
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| 103 |
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| 104 | #define MC_HUB_MISC_HUB_CG 0x82E
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| 105 | #define MC_HUB_MISC_VM_CG 0x82F
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| 106 |
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| 107 | #define MC_HUB_MISC_SIP_CG 0x830
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| 108 |
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| 109 | #define MC_XPB_CLK_GAT 0x91E
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| 110 |
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| 111 | #define MC_CITF_MISC_RD_CG 0x992
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| 112 | #define MC_CITF_MISC_WR_CG 0x993
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| 113 | #define MC_CITF_MISC_VM_CG 0x994
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| 114 |
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| 115 | #define MC_ARB_DRAM_TIMING 0x9DD
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| 116 | #define MC_ARB_DRAM_TIMING2 0x9DE
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| 117 |
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| 118 | #define MC_ARB_BURST_TIME 0xA02
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| 119 | #define STATE0(x) ((x) << 0)
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| 120 | #define STATE0_MASK (0x1f << 0)
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| 121 | #define STATE0_SHIFT 0
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| 122 | #define STATE1(x) ((x) << 5)
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| 123 | #define STATE1_MASK (0x1f << 5)
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| 124 | #define STATE1_SHIFT 5
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| 125 | #define STATE2(x) ((x) << 10)
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| 126 | #define STATE2_MASK (0x1f << 10)
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| 127 | #define STATE2_SHIFT 10
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| 128 | #define STATE3(x) ((x) << 15)
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| 129 | #define STATE3_MASK (0x1f << 15)
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| 130 | #define STATE3_SHIFT 15
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| 131 |
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| 132 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A
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| 133 | #define TRAIN_DONE_D0 (1 << 30)
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| 134 | #define TRAIN_DONE_D1 (1 << 31)
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| 135 |
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| 136 | #define MC_SEQ_SUP_CNTL 0xA32
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| 137 | #define RUN_MASK (1 << 0)
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| 138 | #define MC_SEQ_SUP_PGM 0xA33
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| 139 | #define MC_PMG_AUTO_CMD 0xA34
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| 140 |
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| 141 | #define MC_IO_PAD_CNTL_D0 0xA74
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| 142 | #define MEM_FALL_OUT_CMD (1 << 8)
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| 143 |
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| 144 | #define MC_SEQ_RAS_TIMING 0xA28
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| 145 | #define MC_SEQ_CAS_TIMING 0xA29
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| 146 | #define MC_SEQ_MISC_TIMING 0xA2A
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| 147 | #define MC_SEQ_MISC_TIMING2 0xA2B
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| 148 | #define MC_SEQ_PMG_TIMING 0xA2C
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| 149 | #define MC_SEQ_RD_CTL_D0 0xA2D
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| 150 | #define MC_SEQ_RD_CTL_D1 0xA2E
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| 151 | #define MC_SEQ_WR_CTL_D0 0xA2F
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| 152 | #define MC_SEQ_WR_CTL_D1 0xA30
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| 153 |
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| 154 | #define MC_SEQ_MISC0 0xA80
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| 155 | #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
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| 156 | #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
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| 157 | #define MC_SEQ_MISC0_VEN_ID_VALUE 3
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| 158 | #define MC_SEQ_MISC0_REV_ID_SHIFT 12
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| 159 | #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
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| 160 | #define MC_SEQ_MISC0_REV_ID_VALUE 1
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| 161 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28
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| 162 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
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| 163 | #define MC_SEQ_MISC0_GDDR5_VALUE 5
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| 164 | #define MC_SEQ_MISC1 0xA81
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| 165 | #define MC_SEQ_RESERVE_M 0xA82
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| 166 | #define MC_PMG_CMD_EMRS 0xA83
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| 167 |
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| 168 | #define MC_SEQ_IO_DEBUG_INDEX 0xA91
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| 169 | #define MC_SEQ_IO_DEBUG_DATA 0xA92
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| 170 |
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| 171 | #define MC_SEQ_MISC5 0xA95
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| 172 | #define MC_SEQ_MISC6 0xA96
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| 173 |
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| 174 | #define MC_SEQ_MISC7 0xA99
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| 175 |
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| 176 | #define MC_SEQ_RAS_TIMING_LP 0xA9B
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| 177 | #define MC_SEQ_CAS_TIMING_LP 0xA9C
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| 178 | #define MC_SEQ_MISC_TIMING_LP 0xA9D
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| 179 | #define MC_SEQ_MISC_TIMING2_LP 0xA9E
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| 180 | #define MC_SEQ_WR_CTL_D0_LP 0xA9F
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| 181 | #define MC_SEQ_WR_CTL_D1_LP 0xAA0
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| 182 | #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1
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| 183 | #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2
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| 184 |
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| 185 | #define MC_PMG_CMD_MRS 0xAAB
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| 186 |
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| 187 | #define MC_SEQ_RD_CTL_D0_LP 0xAC7
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| 188 | #define MC_SEQ_RD_CTL_D1_LP 0xAC8
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| 189 |
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| 190 | #define MC_PMG_CMD_MRS1 0xAD1
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| 191 | #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2
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| 192 | #define MC_SEQ_PMG_TIMING_LP 0xAD3
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| 193 |
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| 194 | #define MC_SEQ_WR_CTL_2 0xAD5
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| 195 | #define MC_SEQ_WR_CTL_2_LP 0xAD6
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| 196 | #define MC_PMG_CMD_MRS2 0xAD7
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| 197 | #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8
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| 198 |
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| 199 | #define MCLK_PWRMGT_CNTL 0xAE8
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| 200 | # define DLL_SPEED(x) ((x) << 0)
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| 201 | # define DLL_SPEED_MASK (0x1f << 0)
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| 202 | # define DLL_READY (1 << 6)
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| 203 | # define MC_INT_CNTL (1 << 7)
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| 204 | # define MRDCK0_PDNB (1 << 8)
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| 205 | # define MRDCK1_PDNB (1 << 9)
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| 206 | # define MRDCK0_RESET (1 << 16)
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| 207 | # define MRDCK1_RESET (1 << 17)
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| 208 | # define DLL_READY_READ (1 << 24)
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| 209 | #define DLL_CNTL 0xAE9
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| 210 | # define MRDCK0_BYPASS (1 << 24)
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| 211 | # define MRDCK1_BYPASS (1 << 25)
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| 212 |
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| 213 | #define MPLL_CNTL_MODE 0xAEC
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| 214 | # define MPLL_MCLK_SEL (1 << 11)
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| 215 | #define MPLL_FUNC_CNTL 0xAED
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| 216 | #define BWCTRL(x) ((x) << 20)
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| 217 | #define BWCTRL_MASK (0xff << 20)
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| 218 | #define MPLL_FUNC_CNTL_1 0xAEE
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| 219 | #define VCO_MODE(x) ((x) << 0)
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| 220 | #define VCO_MODE_MASK (3 << 0)
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| 221 | #define CLKFRAC(x) ((x) << 4)
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| 222 | #define CLKFRAC_MASK (0xfff << 4)
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| 223 | #define CLKF(x) ((x) << 16)
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| 224 | #define CLKF_MASK (0xfff << 16)
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| 225 | #define MPLL_FUNC_CNTL_2 0xAEF
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| 226 | #define MPLL_AD_FUNC_CNTL 0xAF0
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| 227 | #define YCLK_POST_DIV(x) ((x) << 0)
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| 228 | #define YCLK_POST_DIV_MASK (7 << 0)
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| 229 | #define MPLL_DQ_FUNC_CNTL 0xAF1
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| 230 | #define YCLK_SEL(x) ((x) << 4)
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| 231 | #define YCLK_SEL_MASK (1 << 4)
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| 232 |
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| 233 | #define MPLL_SS1 0xAF3
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| 234 | #define CLKV(x) ((x) << 0)
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| 235 | #define CLKV_MASK (0x3ffffff << 0)
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| 236 | #define MPLL_SS2 0xAF4
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| 237 | #define CLKS(x) ((x) << 0)
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| 238 | #define CLKS_MASK (0xfff << 0)
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| 239 |
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| 240 | #define ATC_MISC_CG 0xCD4
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| 241 |
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| 242 | #define IH_RB_CNTL 0xF80
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| 243 | # define IH_RB_ENABLE (1 << 0)
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| 244 | # define IH_IB_SIZE(x) ((x) << 1)
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| 245 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
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| 246 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
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| 247 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9)
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| 248 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
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| 249 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
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| 250 | #define IH_RB_BASE 0xF81
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| 251 | #define IH_RB_RPTR 0xF82
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| 252 | #define IH_RB_WPTR 0xF83
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| 253 | # define RB_OVERFLOW (1 << 0)
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| 254 | # define WPTR_OFFSET_MASK 0x3fffc
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| 255 | #define IH_RB_WPTR_ADDR_HI 0xF84
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| 256 | #define IH_RB_WPTR_ADDR_LO 0xF85
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| 257 | #define IH_CNTL 0xF86
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| 258 | # define ENABLE_INTR (1 << 0)
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| 259 | # define IH_MC_SWAP(x) ((x) << 1)
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| 260 | # define IH_MC_SWAP_NONE 0
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| 261 | # define IH_MC_SWAP_16BIT 1
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| 262 | # define IH_MC_SWAP_32BIT 2
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| 263 | # define IH_MC_SWAP_64BIT 3
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| 264 | # define RPTR_REARM (1 << 4)
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| 265 | # define MC_WRREQ_CREDIT(x) ((x) << 15)
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| 266 | # define MC_WR_CLEAN_CNT(x) ((x) << 20)
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| 267 | # define MC_VMID(x) ((x) << 25)
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| 268 |
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| 269 | #define INTERRUPT_CNTL 0x151A
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| 270 | # define IH_DUMMY_RD_OVERRIDE (1 << 0)
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| 271 | # define IH_DUMMY_RD_EN (1 << 1)
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| 272 | # define IH_REQ_NONSNOOP_EN (1 << 3)
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| 273 | # define GEN_IH_INT_EN (1 << 8)
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| 274 | #define INTERRUPT_CNTL2 0x151B
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| 275 |
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| 276 | #define VGT_VTX_VECT_EJECT_REG 0x222C
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| 277 | #define VGT_ESGS_RING_SIZE 0x2232
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| 278 | #define VGT_GSVS_RING_SIZE 0x2233
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| 279 | #define VGT_GS_VERTEX_REUSE 0x2235
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| 280 | #define VGT_PRIMITIVE_TYPE 0x2256
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| 281 | #define VGT_INDEX_TYPE 0x2257
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| 282 | #define VGT_NUM_INDICES 0x225C
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| 283 | #define VGT_NUM_INSTANCES 0x225D
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| 284 | #define VGT_TF_RING_SIZE 0x2262
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| 285 | #define VGT_HS_OFFCHIP_PARAM 0x226C
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| 286 | #define VGT_TF_MEMORY_BASE 0x226E
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| 287 |
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| 288 | #define PA_SC_ENHANCE 0x22FC
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| 289 |
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| 290 | #define TA_CNTL_AUX 0x2542
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| 291 |
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| 292 | |
| 293 | # define RB_XSEL2(x) ((x) << 4)
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| 294 | # define RB_XSEL2_MASK (0x3 << 4)
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| 295 | # define RB_XSEL (1 << 6)
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| 296 | # define RB_YSEL (1 << 7)
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| 297 | # define PKR_MAP(x) ((x) << 8)
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| 298 | # define PKR_XSEL(x) ((x) << 10)
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| 299 | # define PKR_XSEL_MASK (0x3 << 10)
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| 300 | # define PKR_YSEL(x) ((x) << 12)
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| 301 | # define PKR_YSEL_MASK (0x3 << 12)
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| 302 | # define SC_MAP(x) ((x) << 16)
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| 303 | # define SC_MAP_MASK (0x3 << 16)
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| 304 | # define SC_XSEL(x) ((x) << 18)
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| 305 | # define SC_XSEL_MASK (0x3 << 18)
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| 306 | # define SC_YSEL(x) ((x) << 20)
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| 307 | # define SC_YSEL_MASK (0x3 << 20)
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| 308 | # define SE_MAP(x) ((x) << 24)
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| 309 | # define SE_XSEL(x) ((x) << 26)
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| 310 | # define SE_XSEL_MASK (0x3 << 26)
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| 311 | # define SE_YSEL(x) ((x) << 28)
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| 312 | # define SE_YSEL_MASK (0x3 << 28)
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| 313 |
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| 314 |
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| 315 | |
| 316 | # define LC_LINK_WIDTH_X0 0
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| 317 | # define LC_LINK_WIDTH_X1 1
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| 318 | # define LC_LINK_WIDTH_X2 2
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| 319 | # define LC_LINK_WIDTH_X4 3
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| 320 | # define LC_LINK_WIDTH_X8 4
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| 321 | # define LC_LINK_WIDTH_X16 6
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| 322 |
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| 323 | |
| 324 | * PM4
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| 325 |
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| 326 | #define PACKET_TYPE0 0
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| 327 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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| 328 | ((reg) & 0xFFFF) | \
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| 329 | ((n) & 0x3FFF) << 16)
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| 330 | #define CP_PACKET2 0x80000000
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| 331 | #define PACKET2_PAD_SHIFT 0
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| 332 | #define PACKET2_PAD_MASK (0x3fffffff << 0)
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| 333 |
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| 334 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| 335 | #define RADEON_PACKET_TYPE3 3
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| 336 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
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| 337 | (((op) & 0xFF) << 8) | \
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| 338 | ((n) & 0x3FFF) << 16)
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| 339 |
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| 340 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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| 341 |
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| 342 |
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| 343 | #define PACKET3_NOP 0x10
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| 344 | #define PACKET3_SET_BASE 0x11
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| 345 | #define PACKET3_BASE_INDEX(x) ((x) << 0)
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| 346 | #define GDS_PARTITION_BASE 2
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| 347 | #define CE_PARTITION_BASE 3
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| 348 | #define PACKET3_CLEAR_STATE 0x12
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| 349 | #define PACKET3_INDEX_BUFFER_SIZE 0x13
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| 350 | #define PACKET3_DISPATCH_DIRECT 0x15
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| 351 | #define PACKET3_DISPATCH_INDIRECT 0x16
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| 352 | #define PACKET3_ALLOC_GDS 0x1B
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| 353 | #define PACKET3_WRITE_GDS_RAM 0x1C
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| 354 | #define PACKET3_ATOMIC_GDS 0x1D
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| 355 | #define PACKET3_ATOMIC 0x1E
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| 356 | #define PACKET3_OCCLUSION_QUERY 0x1F
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| 357 | #define PACKET3_SET_PREDICATION 0x20
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| 358 | #define PACKET3_REG_RMW 0x21
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| 359 | #define PACKET3_COND_EXEC 0x22
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| 360 | #define PACKET3_PRED_EXEC 0x23
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| 361 | #define PACKET3_DRAW_INDIRECT 0x24
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| 362 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25
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| 363 | #define PACKET3_INDEX_BASE 0x26
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| 364 | #define PACKET3_DRAW_INDEX_2 0x27
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| 365 | #define PACKET3_CONTEXT_CONTROL 0x28
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| 366 | #define PACKET3_INDEX_TYPE 0x2A
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| 367 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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| 368 | #define PACKET3_DRAW_INDEX_AUTO 0x2D
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| 369 | #define PACKET3_DRAW_INDEX_IMMD 0x2E
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| 370 | #define PACKET3_NUM_INSTANCES 0x2F
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| 371 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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| 372 | #define PACKET3_INDIRECT_BUFFER_CONST 0x31
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| 373 | #define PACKET3_INDIRECT_BUFFER 0x3F
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| 374 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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| 375 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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| 376 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
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| 377 | #define PACKET3_WRITE_DATA 0x37
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| 378 | #define WRITE_DATA_DST_SEL(x) ((x) << 8)
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| 379 | |
| 380 | * 1 - memory (sync - via GRBM)
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| 381 | * 2 - tc/l2
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| 382 | * 3 - gds
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| 383 | * 4 - reserved
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| 384 | * 5 - memory (async - direct)
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| 385 |
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| 386 | #define WR_ONE_ADDR (1 << 16)
|
| 387 | #define WR_CONFIRM (1 << 20)
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| 388 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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| 389 | |
| 390 | * 1 - pfp
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| 391 | * 2 - ce
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| 392 |
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| 393 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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| 394 | #define PACKET3_MEM_SEMAPHORE 0x39
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| 395 | #define PACKET3_MPEG_INDEX 0x3A
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| 396 | #define PACKET3_COPY_DW 0x3B
|
| 397 | #define PACKET3_WAIT_REG_MEM 0x3C
|
| 398 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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| 399 | |
| 400 | * 1 - <
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| 401 | * 2 - <=
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| 402 | * 3 - ==
|
| 403 | * 4 - !=
|
| 404 | * 5 - >=
|
| 405 | * 6 - >
|
| 406 |
|
| 407 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
|
| 408 | |
| 409 | * 1 - mem
|
| 410 |
|
| 411 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
|
| 412 | |
| 413 | * 1 - pfp
|
| 414 |
|
| 415 | #define PACKET3_MEM_WRITE 0x3D
|
| 416 | #define PACKET3_COPY_DATA 0x40
|
| 417 | #define PACKET3_CP_DMA 0x41
|
| 418 | |
| 419 | * 2. SRC_ADDR_LO or DATA [31:0]
|
| 420 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
|
| 421 | * SRC_ADDR_HI [7:0]
|
| 422 | * 4. DST_ADDR_LO [31:0]
|
| 423 | * 5. DST_ADDR_HI [7:0]
|
| 424 | * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
|
| 425 |
|
| 426 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
|
| 427 | |
| 428 | * 1 - GDS
|
| 429 |
|
| 430 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
|
| 431 | |
| 432 | * 1 - PFP
|
| 433 |
|
| 434 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
|
| 435 | |
| 436 | * 1 - GDS
|
| 437 | * 2 - DATA
|
| 438 |
|
| 439 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
|
| 440 |
|
| 441 | # define PACKET3_CP_DMA_DIS_WC (1 << 21)
|
| 442 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
|
| 443 | |
| 444 | * 1 - 8 in 16
|
| 445 | * 2 - 8 in 32
|
| 446 | * 3 - 8 in 64
|
| 447 |
|
| 448 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
|
| 449 | |
| 450 | * 1 - 8 in 16
|
| 451 | * 2 - 8 in 32
|
| 452 | * 3 - 8 in 64
|
| 453 |
|
| 454 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
|
| 455 | |
| 456 | * 1 - register
|
| 457 |
|
| 458 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
|
| 459 | |
| 460 | * 1 - register
|
| 461 |
|
| 462 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
|
| 463 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
|
| 464 | # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
|
| 465 | #define PACKET3_PFP_SYNC_ME 0x42
|
| 466 | #define PACKET3_SURFACE_SYNC 0x43
|
| 467 | # define PACKET3_DEST_BASE_0_ENA (1 << 0)
|
| 468 | # define PACKET3_DEST_BASE_1_ENA (1 << 1)
|
| 469 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
|
| 470 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
|
| 471 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
|
| 472 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
|
| 473 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
|
| 474 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
|
| 475 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
|
| 476 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
|
| 477 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
|
| 478 | # define PACKET3_DEST_BASE_2_ENA (1 << 19)
|
| 479 | # define PACKET3_DEST_BASE_3_ENA (1 << 21)
|
| 480 | # define PACKET3_TCL1_ACTION_ENA (1 << 22)
|
| 481 | # define PACKET3_TC_ACTION_ENA (1 << 23)
|
| 482 | # define PACKET3_CB_ACTION_ENA (1 << 25)
|
| 483 | # define PACKET3_DB_ACTION_ENA (1 << 26)
|
| 484 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
|
| 485 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
|
| 486 | #define PACKET3_ME_INITIALIZE 0x44
|
| 487 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
|
| 488 | #define PACKET3_COND_WRITE 0x45
|
| 489 | #define PACKET3_EVENT_WRITE 0x46
|
| 490 | #define EVENT_TYPE(x) ((x) << 0)
|
| 491 | #define EVENT_INDEX(x) ((x) << 8)
|
| 492 | |
| 493 | * 1 - ZPASS_DONE
|
| 494 | * 2 - SAMPLE_PIPELINESTAT
|
| 495 | * 3 - SAMPLE_STREAMOUTSTAT*
|
| 496 | * 4 - *S_PARTIAL_FLUSH
|
| 497 | * 5 - EOP events
|
| 498 | * 6 - EOS events
|
| 499 | * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
|
| 500 |
|
| 501 | #define INV_L2 (1 << 20)
|
| 502 |
|
| 503 | #define PACKET3_EVENT_WRITE_EOP 0x47
|
| 504 | #define DATA_SEL(x) ((x) << 29)
|
| 505 | |
| 506 | * 1 - send low 32bit data
|
| 507 | * 2 - send 64bit data
|
| 508 | * 3 - send 64bit counter value
|
| 509 |
|
| 510 | #define INT_SEL(x) ((x) << 24)
|
| 511 | |
| 512 | * 1 - interrupt only (DATA_SEL = 0)
|
| 513 | * 2 - interrupt when data write is confirmed
|
| 514 |
|
| 515 | #define PACKET3_EVENT_WRITE_EOS 0x48
|
| 516 | #define PACKET3_PREAMBLE_CNTL 0x4A
|
| 517 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
|
| 518 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
|
| 519 | #define PACKET3_ONE_REG_WRITE 0x57
|
| 520 | #define PACKET3_LOAD_CONFIG_REG 0x5F
|
| 521 | #define PACKET3_LOAD_CONTEXT_REG 0x60
|
| 522 | #define PACKET3_LOAD_SH_REG 0x61
|
| 523 | #define PACKET3_SET_CONFIG_REG 0x68
|
| 524 | #define PACKET3_SET_CONFIG_REG_START 0x00002000
|
| 525 | #define PACKET3_SET_CONFIG_REG_END 0x00002c00
|
| 526 | #define PACKET3_SET_CONTEXT_REG 0x69
|
| 527 | #define PACKET3_SET_CONTEXT_REG_START 0x000a000
|
| 528 | #define PACKET3_SET_CONTEXT_REG_END 0x000a400
|
| 529 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
|
| 530 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74
|
| 531 | #define PACKET3_SET_SH_REG 0x76
|
| 532 | #define PACKET3_SET_SH_REG_START 0x00002c00
|
| 533 | #define PACKET3_SET_SH_REG_END 0x00003000
|
| 534 | #define PACKET3_SET_SH_REG_OFFSET 0x77
|
| 535 | #define PACKET3_ME_WRITE 0x7A
|
| 536 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D
|
| 537 | #define PACKET3_SCRATCH_RAM_READ 0x7E
|
| 538 | #define PACKET3_CE_WRITE 0x7F
|
| 539 | #define PACKET3_LOAD_CONST_RAM 0x80
|
| 540 | #define PACKET3_WRITE_CONST_RAM 0x81
|
| 541 | #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
|
| 542 | #define PACKET3_DUMP_CONST_RAM 0x83
|
| 543 | #define PACKET3_INCREMENT_CE_COUNTER 0x84
|
| 544 | #define PACKET3_INCREMENT_DE_COUNTER 0x85
|
| 545 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86
|
| 546 | #define PACKET3_WAIT_ON_DE_COUNTER 0x87
|
| 547 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
|
| 548 | #define PACKET3_SET_CE_DE_COUNTERS 0x89
|
| 549 | #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
|
| 550 | #define PACKET3_SWITCH_BUFFER 0x8B
|
| 551 |
|
| 552 |
|
| 553 | #define DMA0_REGISTER_OFFSET 0x0
|
| 554 | #define DMA1_REGISTER_OFFSET 0x200
|
| 555 | #define SDMA_MAX_INSTANCE 2
|
| 556 |
|
| 557 | #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
|
| 558 | (((b) & 0x1) << 26) | \
|
| 559 | (((t) & 0x1) << 23) | \
|
| 560 | (((s) & 0x1) << 22) | \
|
| 561 | (((n) & 0xFFFFF) << 0))
|
| 562 |
|
| 563 | #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
|
| 564 | (((vmid) & 0xF) << 20) | \
|
| 565 | (((n) & 0xFFFFF) << 0))
|
| 566 |
|
| 567 | #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
|
| 568 | (1 << 26) | \
|
| 569 | (1 << 21) | \
|
| 570 | (((n) & 0xFFFFF) << 0))
|
| 571 |
|
| 572 |
|
| 573 | #define DMA_PACKET_WRITE 0x2
|
| 574 | #define DMA_PACKET_COPY 0x3
|
| 575 | #define DMA_PACKET_INDIRECT_BUFFER 0x4
|
| 576 | #define DMA_PACKET_SEMAPHORE 0x5
|
| 577 | #define DMA_PACKET_FENCE 0x6
|
| 578 | #define DMA_PACKET_TRAP 0x7
|
| 579 | #define DMA_PACKET_SRBM_WRITE 0x9
|
| 580 | #define DMA_PACKET_CONSTANT_FILL 0xd
|
| 581 | #define DMA_PACKET_POLL_REG_MEM 0xe
|
| 582 | #define DMA_PACKET_NOP 0xf
|
| 583 |
|
| 584 |
|
| 585 | #define VCE_CMD_NO_OP 0x00000000
|
| 586 | #define VCE_CMD_END 0x00000001
|
| 587 | #define VCE_CMD_IB 0x00000002
|
| 588 | #define VCE_CMD_FENCE 0x00000003
|
| 589 | #define VCE_CMD_TRAP 0x00000004
|
| 590 | #define VCE_CMD_IB_AUTO 0x00000005
|
| 591 | #define VCE_CMD_SEMAPHORE 0x00000006
|
| 592 |
|
| 593 | |
| 594 |
|
| 595 | #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
|
| 596 | #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
|
| 597 | #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c)
|
| 598 | #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c)
|
| 599 | #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c)
|
| 600 | #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c)
|
| 601 |
|
| 602 |
|
| 603 | #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
|
| 604 | #define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
|
| 605 | #define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
|
| 606 | #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
|
| 607 | #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
|
| 608 | #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
|
| 609 |
|
| 610 |
|
| 611 | #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
|
| 612 | #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
|
| 613 | #define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
|
| 614 | #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
|
| 615 | #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
|
| 616 | #define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
|
| 617 | #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
|
| 618 |
|
| 619 | #define CURSOR_WIDTH 64
|
| 620 | #define CURSOR_HEIGHT 64
|
| 621 |
|
| 622 |
|
| 623 | #define R600_ROM_CNTL 0x580
|
| 624 | # define R600_SCK_OVERWRITE (1 << 1)
|
| 625 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
|
| 626 | # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
|
| 627 |
|
| 628 | #define GRPH_ARRAY_LINEAR_GENERAL 0
|
| 629 | #define GRPH_ARRAY_LINEAR_ALIGNED 1
|
| 630 | #define GRPH_ARRAY_1D_TILED_THIN1 2
|
| 631 | #define GRPH_ARRAY_2D_TILED_THIN1 4
|
| 632 |
|
| 633 | #define ES_AND_GS_AUTO 3
|
| 634 | #define BUF_SWAP_32BIT (2 << 16)
|
| 635 |
|
| 636 | #define GRPH_DEPTH_8BPP 0
|
| 637 | #define GRPH_DEPTH_16BPP 1
|
| 638 | #define GRPH_DEPTH_32BPP 2
|
| 639 |
|
| 640 |
|
| 641 | #define GRPH_FORMAT_INDEXED 0
|
| 642 |
|
| 643 |
|
| 644 | #define GRPH_FORMAT_ARGB1555 0
|
| 645 | #define GRPH_FORMAT_ARGB565 1
|
| 646 | #define GRPH_FORMAT_ARGB4444 2
|
| 647 | #define GRPH_FORMAT_AI88 3
|
| 648 | #define GRPH_FORMAT_MONO16 4
|
| 649 | #define GRPH_FORMAT_BGRA5551 5
|
| 650 |
|
| 651 |
|
| 652 | #define GRPH_FORMAT_ARGB8888 0
|
| 653 | #define GRPH_FORMAT_ARGB2101010 1
|
| 654 | #define GRPH_FORMAT_32BPP_DIG 2
|
| 655 | #define GRPH_FORMAT_8B_ARGB2101010 3
|
| 656 | #define GRPH_FORMAT_BGRA1010102 4
|
| 657 | #define GRPH_FORMAT_8B_BGRA1010102 5
|
| 658 | #define GRPH_FORMAT_RGB111110 6
|
| 659 | #define GRPH_FORMAT_BGR101111 7
|
| 660 |
|
| 661 | #define GRPH_ENDIAN_NONE 0
|
| 662 | #define GRPH_ENDIAN_8IN16 1
|
| 663 | #define GRPH_ENDIAN_8IN32 2
|
| 664 | #define GRPH_ENDIAN_8IN64 3
|
| 665 | #define GRPH_RED_SEL_R 0
|
| 666 | #define GRPH_RED_SEL_G 1
|
| 667 | #define GRPH_RED_SEL_B 2
|
| 668 | #define GRPH_RED_SEL_A 3
|
| 669 |
|
| 670 | #define GRPH_GREEN_SEL_G 0
|
| 671 | #define GRPH_GREEN_SEL_B 1
|
| 672 | #define GRPH_GREEN_SEL_A 2
|
| 673 | #define GRPH_GREEN_SEL_R 3
|
| 674 |
|
| 675 | #define GRPH_BLUE_SEL_B 0
|
| 676 | #define GRPH_BLUE_SEL_A 1
|
| 677 | #define GRPH_BLUE_SEL_R 2
|
| 678 | #define GRPH_BLUE_SEL_G 3
|
| 679 |
|
| 680 | #define GRPH_ALPHA_SEL_A 0
|
| 681 | #define GRPH_ALPHA_SEL_R 1
|
| 682 | #define GRPH_ALPHA_SEL_G 2
|
| 683 | #define GRPH_ALPHA_SEL_B 3
|
| 684 |
|
| 685 |
|
| 686 | #define CURSOR_MONO 0
|
| 687 | #define CURSOR_24_1 1
|
| 688 | #define CURSOR_24_8_PRE_MULT 2
|
| 689 | #define CURSOR_24_8_UNPRE_MULT 3
|
| 690 | #define CURSOR_URGENT_ALWAYS 0
|
| 691 | #define CURSOR_URGENT_1_8 1
|
| 692 | #define CURSOR_URGENT_1_4 2
|
| 693 | #define CURSOR_URGENT_3_8 3
|
| 694 | #define CURSOR_URGENT_1_2 4
|
| 695 |
|
| 696 |
|
| 697 | # define INPUT_CSC_BYPASS 0
|
| 698 | # define INPUT_CSC_PROG_COEFF 1
|
| 699 | # define INPUT_CSC_PROG_SHARED_MATRIXA 2
|
| 700 |
|
| 701 |
|
| 702 | # define OUTPUT_CSC_BYPASS 0
|
| 703 | # define OUTPUT_CSC_TV_RGB 1
|
| 704 | # define OUTPUT_CSC_YCBCR_601 2
|
| 705 | # define OUTPUT_CSC_YCBCR_709 3
|
| 706 | # define OUTPUT_CSC_PROG_COEFF 4
|
| 707 | # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5
|
| 708 |
|
| 709 |
|
| 710 | # define DEGAMMA_BYPASS 0
|
| 711 | # define DEGAMMA_SRGB_24 1
|
| 712 | # define DEGAMMA_XVYCC_222 2
|
| 713 |
|
| 714 |
|
| 715 | # define GAMUT_REMAP_BYPASS 0
|
| 716 | # define GAMUT_REMAP_PROG_COEFF 1
|
| 717 | # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2
|
| 718 | # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3
|
| 719 |
|
| 720 |
|
| 721 | # define REGAMMA_BYPASS 0
|
| 722 | # define REGAMMA_SRGB_24 1
|
| 723 | # define REGAMMA_XVYCC_222 2
|
| 724 | # define REGAMMA_PROG_A 3
|
| 725 | # define REGAMMA_PROG_B 4
|
| 726 |
|
| 727 |
|
| 728 |
|
| 729 | # define INPUT_GAMMA_USE_LUT 0
|
| 730 | # define INPUT_GAMMA_BYPASS 1
|
| 731 | # define INPUT_GAMMA_SRGB_24 2
|
| 732 | # define INPUT_GAMMA_XVYCC_222 3
|
| 733 |
|
| 734 | #define MC_SEQ_MISC0__MT__MASK 0xf0000000
|
| 735 | #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
|
| 736 | #define MC_SEQ_MISC0__MT__DDR2 0x20000000
|
| 737 | #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
|
| 738 | #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
|
| 739 | #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
|
| 740 | #define MC_SEQ_MISC0__MT__HBM 0x60000000
|
| 741 | #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
|
| 742 |
|
| 743 | #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
|
| 744 | #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
|
| 745 | #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
|
| 746 | #define PACKET3_SEM_SEL_WAIT (0x7 << 29)
|
| 747 |
|
| 748 | #define AMDGPU_PCIE_INDEX 0xc
|
| 749 | #define AMDGPU_PCIE_DATA 0xd
|
| 750 |
|
| 751 | #define PCIE_BUS_CLK 10000
|
| 752 | #define TCLK (PCIE_BUS_CLK / 10)
|
| 753 | #define PCIE_PORT_INDEX 0xe
|
| 754 | #define PCIE_PORT_DATA 0xf
|
| 755 | #define EVERGREEN_PIF_PHY0_INDEX 0x8
|
| 756 | #define EVERGREEN_PIF_PHY0_DATA 0xc
|
| 757 | #define EVERGREEN_PIF_PHY1_INDEX 0x10
|
| 758 | #define EVERGREEN_PIF_PHY1_DATA 0x14
|
| 759 |
|
| 760 |
|
| 761 | #define CG_VCEPLL_FUNC_CNTL 0xc0030600
|
| 762 | #define VCEPLL_RESET_MASK 0x00000001
|
| 763 | #define VCEPLL_SLEEP_MASK 0x00000002
|
| 764 | #define VCEPLL_BYPASS_EN_MASK 0x00000004
|
| 765 | #define VCEPLL_CTLREQ_MASK 0x00000008
|
| 766 | #define VCEPLL_VCO_MODE_MASK 0x00000600
|
| 767 | #define VCEPLL_REF_DIV_MASK 0x003F0000
|
| 768 | #define VCEPLL_CTLACK_MASK 0x40000000
|
| 769 | #define VCEPLL_CTLACK2_MASK 0x80000000
|
| 770 |
|
| 771 | #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601
|
| 772 | #define VCEPLL_PDIV_A(x) ((x) << 0)
|
| 773 | #define VCEPLL_PDIV_A_MASK 0x0000007F
|
| 774 | #define VCEPLL_PDIV_B(x) ((x) << 8)
|
| 775 | #define VCEPLL_PDIV_B_MASK 0x00007F00
|
| 776 | #define EVCLK_SRC_SEL(x) ((x) << 20)
|
| 777 | #define EVCLK_SRC_SEL_MASK 0x01F00000
|
| 778 | #define ECCLK_SRC_SEL(x) ((x) << 25)
|
| 779 | #define ECCLK_SRC_SEL_MASK 0x3E000000
|
| 780 |
|
| 781 | #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602
|
| 782 | #define VCEPLL_FB_DIV(x) ((x) << 0)
|
| 783 | #define VCEPLL_FB_DIV_MASK 0x01FFFFFF
|
| 784 |
|
| 785 | #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603
|
| 786 |
|
| 787 | #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604
|
| 788 | #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606
|
| 789 | #define VCEPLL_SSEN_MASK 0x00000001
|
| 790 |
|
| 791 |
|
| 792 | #endif
|