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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "amdgpu_smu.h"
35#include "atom.h"
36#include "amd_pcie.h"
37#include "amdgpu_video_codecs.h"
38
39#include "gc/gc_12_0_0_offset.h"
40#include "gc/gc_12_0_0_sh_mask.h"
41#include "mp/mp_14_0_2_offset.h"
42
43#include "soc15.h"
44#include "soc15_common.h"
45#include "soc24.h"
46#include "mxgpu_nv.h"
47
48static const struct amd_ip_funcs soc24_common_ip_funcs;
49
50static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = {
51 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
54};
55
56static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_encode_vcn0 = {
57 .codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_encode_array_vcn0),
58 .codec_array = vcn_5_0_0_video_codecs_encode_array_vcn0,
59};
60
61static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_decode_array_vcn0[] = {
62 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
63 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
64 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
65 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
66 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
67};
68
69static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_decode_vcn0 = {
70 .codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_decode_array_vcn0),
71 .codec_array = vcn_5_0_0_video_codecs_decode_array_vcn0,
72};
73
74static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode,
75 const struct amdgpu_video_codecs **codecs)
76{
77 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
78 return -EINVAL;
79
80 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
81 case IP_VERSION(5, 0, 0):
82 if (encode)
83 *codecs = &vcn_5_0_0_video_codecs_encode_vcn0;
84 else
85 *codecs = &vcn_5_0_0_video_codecs_decode_vcn0;
86 return 0;
87 default:
88 return -EINVAL;
89 }
90}
91
92static u32 soc24_get_config_memsize(struct amdgpu_device *adev)
93{
94 return adev->nbio.funcs->get_memsize(adev);
95}
96
97static u32 soc24_get_xclk(struct amdgpu_device *adev)
98{
99 return adev->clock.spll.reference_freq;
100}
101
102void soc24_grbm_select(struct amdgpu_device *adev,
103 u32 me, u32 pipe, u32 queue, u32 vmid)
104{
105 u32 grbm_gfx_cntl = 0;
106 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
107 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
108 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
109 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
110
111 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
112}
113
114static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {
115 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
116 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
117 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
118 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
119 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
120 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
121 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
122 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
123 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
124 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
125 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
126 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
127 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
128 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
129 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
130 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
131 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
132 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
133 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
134};
135
136static uint32_t soc24_get_register_value(struct amdgpu_device *adev,
137 bool indexed, u32 se_num,
138 u32 sh_num, u32 reg_offset)
139{
140 if (indexed) {
141 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
142 } else {
143 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&
144 adev->gfx.config.gb_addr_config)
145 return adev->gfx.config.gb_addr_config;
146 return RREG32(reg_offset);
147 }
148}
149
150static int soc24_read_register(struct amdgpu_device *adev, u32 se_num,
151 u32 sh_num, u32 reg_offset, u32 *value)
152{
153 uint32_t i;
154 struct soc15_allowed_register_entry *en;
155
156 *value = 0;
157 for (i = 0; i < ARRAY_SIZE(soc24_allowed_read_registers); i++) {
158 en = &soc24_allowed_read_registers[i];
159 if (!adev->reg_offset[en->hwip][en->inst])
160 continue;
161 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
162 + en->reg_offset))
163 continue;
164
165 *value = soc24_get_register_value(adev,
166 soc24_allowed_read_registers[i].grbm_indexed,
167 se_num, sh_num, reg_offset);
168 return 0;
169 }
170 return -EINVAL;
171}
172
173static enum amd_reset_method
174soc24_asic_reset_method(struct amdgpu_device *adev)
175{
176 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
177 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
178 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
179 return amdgpu_reset_method;
180
181 if (amdgpu_reset_method != -1)
182 dev_warn(adev->dev,
183 "Specified reset method:%d isn't supported, using AUTO instead.\n",
184 amdgpu_reset_method);
185
186 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
187 case IP_VERSION(14, 0, 2):
188 case IP_VERSION(14, 0, 3):
189 return AMD_RESET_METHOD_MODE1;
190 default:
191 if (amdgpu_dpm_is_baco_supported(adev))
192 return AMD_RESET_METHOD_BACO;
193 else
194 return AMD_RESET_METHOD_MODE1;
195 }
196}
197
198static int soc24_asic_reset(struct amdgpu_device *adev)
199{
200 int ret = 0;
201
202 switch (soc24_asic_reset_method(adev)) {
203 case AMD_RESET_METHOD_PCI:
204 dev_info(adev->dev, "PCI reset\n");
205 ret = amdgpu_device_pci_reset(adev);
206 break;
207 case AMD_RESET_METHOD_BACO:
208 dev_info(adev->dev, "BACO reset\n");
209 ret = amdgpu_dpm_baco_reset(adev);
210 break;
211 case AMD_RESET_METHOD_MODE2:
212 dev_info(adev->dev, "MODE2 reset\n");
213 ret = amdgpu_dpm_mode2_reset(adev);
214 break;
215 default:
216 dev_info(adev->dev, "MODE1 reset\n");
217 ret = amdgpu_device_mode1_reset(adev);
218 break;
219 }
220
221 return ret;
222}
223
224static void soc24_program_aspm(struct amdgpu_device *adev)
225{
226 if (!amdgpu_device_should_use_aspm(adev))
227 return;
228
229 if (!(adev->flags & AMD_IS_APU) &&
230 (adev->nbio.funcs->program_aspm))
231 adev->nbio.funcs->program_aspm(adev);
232}
233
234const struct amdgpu_ip_block_version soc24_common_ip_block = {
235 .type = AMD_IP_BLOCK_TYPE_COMMON,
236 .major = 1,
237 .minor = 0,
238 .rev = 0,
239 .funcs = &soc24_common_ip_funcs,
240};
241
242static bool soc24_need_reset_on_init(struct amdgpu_device *adev)
243{
244 u32 sol_reg;
245
246 if (adev->flags & AMD_IS_APU)
247 return false;
248
249 /* Check sOS sign of life register to confirm sys driver and sOS
250 * are already been loaded.
251 */
252 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
253 if (sol_reg)
254 return true;
255
256 return false;
257}
258
259static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev)
260{
261 /* TODO
262 * dummy implement for pcie_replay_count sysfs interface
263 * */
264 return 0;
265}
266
267static void soc24_init_doorbell_index(struct amdgpu_device *adev)
268{
269 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
270 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
271 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
272 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
273 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
274 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
275 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
276 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
277 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
278 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
279 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
280 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
281 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
282 adev->doorbell_index.gfx_userqueue_start =
283 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
284 adev->doorbell_index.gfx_userqueue_end =
285 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
286 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
287 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
288 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
289 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
290 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
291 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
292 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
293 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
294 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
295 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
296 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
297
298 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
299 adev->doorbell_index.sdma_doorbell_range = 20;
300}
301
302static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev,
303 bool enter)
304{
305 if (enter)
306 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
307 else
308 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
309
310 if (adev->gfx.funcs->update_perfmon_mgcg)
311 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
312
313 return 0;
314}
315
316static const struct amdgpu_asic_funcs soc24_asic_funcs = {
317 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
318 .read_register = &soc24_read_register,
319 .reset = &soc24_asic_reset,
320 .reset_method = &soc24_asic_reset_method,
321 .get_xclk = &soc24_get_xclk,
322 .get_config_memsize = &soc24_get_config_memsize,
323 .init_doorbell_index = &soc24_init_doorbell_index,
324 .need_reset_on_init = &soc24_need_reset_on_init,
325 .get_pcie_replay_count = &soc24_get_pcie_replay_count,
326 .supports_baco = &amdgpu_dpm_is_baco_supported,
327 .query_video_codecs = &soc24_query_video_codecs,
328 .update_umd_stable_pstate = &soc24_update_umd_stable_pstate,
329};
330
331static int soc24_common_early_init(struct amdgpu_ip_block *ip_block)
332{
333 struct amdgpu_device *adev = ip_block->adev;
334
335 adev->nbio.funcs->set_reg_remap(adev);
336 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg;
337 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg;
338 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64;
339 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64;
340 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg;
341 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg;
342
343 adev->asic_funcs = &soc24_asic_funcs;
344
345 adev->rev_id = amdgpu_device_get_rev_id(adev);
346 adev->external_rev_id = 0xff;
347
348 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
349 case IP_VERSION(12, 0, 0):
350 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
351 AMD_CG_SUPPORT_GFX_CGLS |
352 AMD_CG_SUPPORT_GFX_MGCG |
353 AMD_CG_SUPPORT_GFX_3D_CGCG |
354 AMD_CG_SUPPORT_GFX_3D_CGLS |
355 AMD_CG_SUPPORT_REPEATER_FGCG |
356 AMD_CG_SUPPORT_GFX_FGCG |
357 AMD_CG_SUPPORT_GFX_PERF_CLK |
358 AMD_CG_SUPPORT_ATHUB_MGCG |
359 AMD_CG_SUPPORT_ATHUB_LS |
360 AMD_CG_SUPPORT_MC_MGCG |
361 AMD_CG_SUPPORT_HDP_SD |
362 AMD_CG_SUPPORT_MC_LS;
363 adev->pg_flags = AMD_PG_SUPPORT_VCN |
364 AMD_PG_SUPPORT_JPEG |
365 AMD_PG_SUPPORT_VCN_DPG;
366 adev->external_rev_id = adev->rev_id + 0x40;
367 break;
368 case IP_VERSION(12, 0, 1):
369 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
370 AMD_CG_SUPPORT_GFX_CGLS |
371 AMD_CG_SUPPORT_GFX_MGCG |
372 AMD_CG_SUPPORT_GFX_3D_CGCG |
373 AMD_CG_SUPPORT_GFX_3D_CGLS |
374 AMD_CG_SUPPORT_REPEATER_FGCG |
375 AMD_CG_SUPPORT_GFX_FGCG |
376 AMD_CG_SUPPORT_GFX_PERF_CLK |
377 AMD_CG_SUPPORT_ATHUB_MGCG |
378 AMD_CG_SUPPORT_ATHUB_LS |
379 AMD_CG_SUPPORT_MC_MGCG |
380 AMD_CG_SUPPORT_HDP_SD |
381 AMD_CG_SUPPORT_MC_LS;
382
383 adev->pg_flags = AMD_PG_SUPPORT_VCN |
384 AMD_PG_SUPPORT_JPEG |
385 AMD_PG_SUPPORT_JPEG_DPG |
386 AMD_PG_SUPPORT_VCN_DPG;
387 adev->external_rev_id = adev->rev_id + 0x50;
388 break;
389 default:
390 /* FIXME: not supported yet */
391 return -EINVAL;
392 }
393
394 if (amdgpu_sriov_vf(adev)) {
395 amdgpu_virt_init_setting(adev);
396 xgpu_nv_mailbox_set_irq_funcs(adev);
397 }
398
399 return 0;
400}
401
402static int soc24_common_late_init(struct amdgpu_ip_block *ip_block)
403{
404 struct amdgpu_device *adev = ip_block->adev;
405
406 if (amdgpu_sriov_vf(adev)) {
407 xgpu_nv_mailbox_get_irq(adev);
408 } else {
409 if (adev->nbio.ras &&
410 adev->nbio.ras_err_event_athub_irq.funcs)
411 /* don't need to fail gpu late init
412 * if enabling athub_err_event interrupt failed
413 * nbif v6_3_1 only support fatal error hanlding
414 * just enable the interrupt directly
415 */
416 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
417 }
418
419 /* Enable selfring doorbell aperture late because doorbell BAR
420 * aperture will change if resize BAR successfully in gmc sw_init.
421 */
422 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
423
424 return 0;
425}
426
427static int soc24_common_sw_init(struct amdgpu_ip_block *ip_block)
428{
429 struct amdgpu_device *adev = ip_block->adev;
430
431 if (amdgpu_sriov_vf(adev))
432 xgpu_nv_mailbox_add_irq_id(adev);
433
434 return 0;
435}
436
437static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block)
438{
439 struct amdgpu_device *adev = ip_block->adev;
440
441 /* enable aspm */
442 soc24_program_aspm(adev);
443 /* setup nbio registers */
444 adev->nbio.funcs->init_registers(adev);
445 /* remap HDP registers to a hole in mmio space,
446 * for the purpose of expose those registers
447 * to process space
448 */
449 if (adev->nbio.funcs->remap_hdp_registers)
450 adev->nbio.funcs->remap_hdp_registers(adev);
451
452 if (adev->df.funcs && adev->df.funcs->hw_init)
453 adev->df.funcs->hw_init(adev);
454
455 /* enable the doorbell aperture */
456 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
457
458 return 0;
459}
460
461static int soc24_common_hw_fini(struct amdgpu_ip_block *ip_block)
462{
463 struct amdgpu_device *adev = ip_block->adev;
464
465 /* Disable the doorbell aperture and selfring doorbell aperture
466 * separately in hw_fini because soc21_enable_doorbell_aperture
467 * has been removed and there is no need to delay disabling
468 * selfring doorbell.
469 */
470 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
471 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
472
473 if (amdgpu_sriov_vf(adev)) {
474 xgpu_nv_mailbox_put_irq(adev);
475 } else {
476 if (adev->nbio.ras &&
477 adev->nbio.ras_err_event_athub_irq.funcs)
478 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
479 }
480
481 return 0;
482}
483
484static int soc24_common_suspend(struct amdgpu_ip_block *ip_block)
485{
486 return soc24_common_hw_fini(ip_block);
487}
488
489static bool soc24_need_reset_on_resume(struct amdgpu_device *adev)
490{
491 u32 sol_reg1, sol_reg2;
492
493 /* Will reset for the following suspend abort cases.
494 * 1) Only reset dGPU side.
495 * 2) S3 suspend got aborted and TOS is active.
496 * As for dGPU suspend abort cases the SOL value
497 * will be kept as zero at this resume point.
498 */
499 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) {
500 sol_reg1 = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
501 msleep(100);
502 sol_reg2 = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
503
504 return (sol_reg1 != sol_reg2);
505 }
506
507 return false;
508}
509
510static int soc24_common_resume(struct amdgpu_ip_block *ip_block)
511{
512 struct amdgpu_device *adev = ip_block->adev;
513
514 if (soc24_need_reset_on_resume(adev)) {
515 dev_info(adev->dev, "S3 suspend aborted, resetting...");
516 soc24_asic_reset(adev);
517 }
518
519 return soc24_common_hw_init(ip_block);
520}
521
522static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)
523{
524 return true;
525}
526
527static int soc24_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
528 enum amd_clockgating_state state)
529{
530 struct amdgpu_device *adev = ip_block->adev;
531
532 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
533 case IP_VERSION(6, 3, 1):
534 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
535 state == AMD_CG_STATE_GATE);
536 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
537 state == AMD_CG_STATE_GATE);
538 adev->hdp.funcs->update_clock_gating(adev,
539 state == AMD_CG_STATE_GATE);
540 break;
541 default:
542 break;
543 }
544 return 0;
545}
546
547static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
548 enum amd_powergating_state state)
549{
550 struct amdgpu_device *adev = ip_block->adev;
551
552 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
553 case IP_VERSION(7, 0, 0):
554 case IP_VERSION(7, 0, 1):
555 adev->lsdma.funcs->update_memory_power_gating(adev,
556 state == AMD_PG_STATE_GATE);
557 break;
558 default:
559 break;
560 }
561
562 return 0;
563}
564
565static void soc24_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
566{
567 struct amdgpu_device *adev = ip_block->adev;
568
569 adev->nbio.funcs->get_clockgating_state(adev, flags);
570
571 adev->hdp.funcs->get_clock_gating_state(adev, flags);
572
573 return;
574}
575
576static const struct amd_ip_funcs soc24_common_ip_funcs = {
577 .name = "soc24_common",
578 .early_init = soc24_common_early_init,
579 .late_init = soc24_common_late_init,
580 .sw_init = soc24_common_sw_init,
581 .hw_init = soc24_common_hw_init,
582 .hw_fini = soc24_common_hw_fini,
583 .suspend = soc24_common_suspend,
584 .resume = soc24_common_resume,
585 .is_idle = soc24_common_is_idle,
586 .set_clockgating_state = soc24_common_set_clockgating_state,
587 .set_powergating_state = soc24_common_set_powergating_state,
588 .get_clockgating_state = soc24_common_get_clockgating_state,
589};