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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _DM_PP_INTERFACE_
24#define _DM_PP_INTERFACE_
25
26#include "dm_services_types.h"
27
28#define PP_MAX_CLOCK_LEVELS 16
29
30enum amd_pp_display_config_type {
31 AMD_PP_DisplayConfigType_None = 0,
32 AMD_PP_DisplayConfigType_DP54 ,
33 AMD_PP_DisplayConfigType_DP432 ,
34 AMD_PP_DisplayConfigType_DP324 ,
35 AMD_PP_DisplayConfigType_DP27,
36 AMD_PP_DisplayConfigType_DP243,
37 AMD_PP_DisplayConfigType_DP216,
38 AMD_PP_DisplayConfigType_DP162,
39 AMD_PP_DisplayConfigType_HDMI6G,
40 AMD_PP_DisplayConfigType_HDMI297,
41 AMD_PP_DisplayConfigType_HDMI162,
42 AMD_PP_DisplayConfigType_LVDS,
43 AMD_PP_DisplayConfigType_DVI,
44 AMD_PP_DisplayConfigType_WIRELESS,
45 AMD_PP_DisplayConfigType_VGA
46};
47
48struct single_display_configuration {
49 uint32_t controller_index;
50 uint32_t controller_id;
51 uint32_t signal_type;
52 uint32_t display_state;
53 /* phy id for the primary internal transmitter */
54 uint8_t primary_transmitter_phyi_d;
55 /* bitmap with the active lanes */
56 uint8_t primary_transmitter_active_lanemap;
57 /* phy id for the secondary internal transmitter (for dual-link dvi) */
58 uint8_t secondary_transmitter_phy_id;
59 /* bitmap with the active lanes */
60 uint8_t secondary_transmitter_active_lanemap;
61 /* misc phy settings for SMU. */
62 uint32_t config_flags;
63 uint32_t display_type;
64 uint32_t view_resolution_cx;
65 uint32_t view_resolution_cy;
66 enum amd_pp_display_config_type displayconfigtype;
67 uint32_t vertical_refresh; /* for active display */
68 uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */
69};
70
71#define MAX_NUM_DISPLAY 32
72
73struct amd_pp_display_configuration {
74 bool nb_pstate_switch_disable;/* controls NB PState switch */
75 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
76 bool cpu_pstate_disable;
77 uint32_t cpu_pstate_separation_time;
78
79 uint32_t num_display; /* total number of display*/
80 uint32_t num_path_including_non_display;
81 uint32_t crossfire_display_index;
82 uint32_t min_mem_set_clock;
83 uint32_t min_core_set_clock;
84 /* unit 10KHz x bit*/
85 uint32_t min_bus_bandwidth;
86 /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
87 uint32_t min_core_set_clock_in_sr;
88
89 struct single_display_configuration displays[MAX_NUM_DISPLAY];
90
91 uint32_t vrefresh; /* for active display*/
92
93 uint32_t min_vblank_time; /* for active display*/
94 bool multi_monitor_in_sync;
95 /* Controller Index of primary display - used in MCLK SMC switching hang
96 * SW Workaround*/
97 uint32_t crtc_index;
98 /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
99 uint32_t line_time_in_us;
100 bool invalid_vblank_time;
101
102 uint32_t display_clk;
103 /*
104 * for given display configuration if multimonitormnsync == false then
105 * Memory clock DPMS with this latency or below is allowed, DPMS with
106 * higher latency not allowed.
107 */
108 uint32_t dce_tolerable_mclk_in_active_latency;
109 uint32_t min_dcef_set_clk;
110 uint32_t min_dcef_deep_sleep_set_clk;
111};
112
113struct amd_pp_simple_clock_info {
114 uint32_t engine_max_clock;
115 uint32_t memory_max_clock;
116};
117
118struct amd_pp_clock_info {
119 uint32_t min_engine_clock;
120 uint32_t max_engine_clock;
121 uint32_t min_memory_clock;
122 uint32_t max_memory_clock;
123 uint32_t min_bus_bandwidth;
124 uint32_t max_bus_bandwidth;
125 uint32_t max_engine_clock_in_sr;
126 uint32_t min_engine_clock_in_sr;
127};
128
129enum amd_pp_clock_type {
130 amd_pp_disp_clock = 1,
131 amd_pp_sys_clock,
132 amd_pp_mem_clock,
133 amd_pp_dcef_clock,
134 amd_pp_soc_clock,
135 amd_pp_pixel_clock,
136 amd_pp_phy_clock,
137 amd_pp_dcf_clock,
138 amd_pp_dpp_clock,
139 amd_pp_f_clock = amd_pp_dcef_clock,
140};
141
142#define MAX_NUM_CLOCKS 16
143
144struct amd_pp_clocks {
145 uint32_t count;
146 uint32_t clock[MAX_NUM_CLOCKS];
147 uint32_t latency[MAX_NUM_CLOCKS];
148};
149
150struct pp_clock_with_latency {
151 uint32_t clocks_in_khz;
152 uint32_t latency_in_us;
153};
154
155struct pp_clock_levels_with_latency {
156 uint32_t num_levels;
157 struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS];
158};
159
160struct pp_clock_with_voltage {
161 uint32_t clocks_in_khz;
162 uint32_t voltage_in_mv;
163};
164
165struct pp_clock_levels_with_voltage {
166 uint32_t num_levels;
167 struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
168};
169
170struct pp_display_clock_request {
171 enum amd_pp_clock_type clock_type;
172 uint32_t clock_freq_in_khz;
173};
174
175#endif /* _DM_PP_INTERFACE_ */