| 1 | |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 |
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| 23 |
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| 24 | #ifndef VI_STRUCTS_H_
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| 25 | #define VI_STRUCTS_H_
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| 26 |
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| 27 | struct vi_sdma_mqd {
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| 28 | uint32_t sdmax_rlcx_rb_cntl;
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| 29 | uint32_t sdmax_rlcx_rb_base;
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| 30 | uint32_t sdmax_rlcx_rb_base_hi;
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| 31 | uint32_t sdmax_rlcx_rb_rptr;
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| 32 | uint32_t sdmax_rlcx_rb_wptr;
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| 33 | uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
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| 34 | uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
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| 35 | uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
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| 36 | uint32_t sdmax_rlcx_rb_rptr_addr_hi;
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| 37 | uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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| 38 | uint32_t sdmax_rlcx_ib_cntl;
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| 39 | uint32_t sdmax_rlcx_ib_rptr;
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| 40 | uint32_t sdmax_rlcx_ib_offset;
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| 41 | uint32_t sdmax_rlcx_ib_base_lo;
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| 42 | uint32_t sdmax_rlcx_ib_base_hi;
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| 43 | uint32_t sdmax_rlcx_ib_size;
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| 44 | uint32_t sdmax_rlcx_skip_cntl;
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| 45 | uint32_t sdmax_rlcx_context_status;
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| 46 | uint32_t sdmax_rlcx_doorbell;
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| 47 | uint32_t sdmax_rlcx_virtual_addr;
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| 48 | uint32_t sdmax_rlcx_ape1_cntl;
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| 49 | uint32_t sdmax_rlcx_doorbell_log;
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| 50 | uint32_t reserved_22;
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| 51 | uint32_t reserved_23;
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| 52 | uint32_t reserved_24;
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| 53 | uint32_t reserved_25;
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| 54 | uint32_t reserved_26;
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| 55 | uint32_t reserved_27;
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| 56 | uint32_t reserved_28;
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| 57 | uint32_t reserved_29;
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| 58 | uint32_t reserved_30;
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| 59 | uint32_t reserved_31;
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| 60 | uint32_t reserved_32;
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| 61 | uint32_t reserved_33;
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| 62 | uint32_t reserved_34;
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| 63 | uint32_t reserved_35;
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| 64 | uint32_t reserved_36;
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| 65 | uint32_t reserved_37;
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| 66 | uint32_t reserved_38;
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| 67 | uint32_t reserved_39;
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| 68 | uint32_t reserved_40;
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| 69 | uint32_t reserved_41;
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| 70 | uint32_t reserved_42;
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| 71 | uint32_t reserved_43;
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| 72 | uint32_t reserved_44;
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| 73 | uint32_t reserved_45;
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| 74 | uint32_t reserved_46;
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| 75 | uint32_t reserved_47;
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| 76 | uint32_t reserved_48;
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| 77 | uint32_t reserved_49;
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| 78 | uint32_t reserved_50;
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| 79 | uint32_t reserved_51;
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| 80 | uint32_t reserved_52;
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| 81 | uint32_t reserved_53;
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| 82 | uint32_t reserved_54;
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| 83 | uint32_t reserved_55;
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| 84 | uint32_t reserved_56;
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| 85 | uint32_t reserved_57;
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| 86 | uint32_t reserved_58;
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| 87 | uint32_t reserved_59;
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| 88 | uint32_t reserved_60;
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| 89 | uint32_t reserved_61;
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| 90 | uint32_t reserved_62;
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| 91 | uint32_t reserved_63;
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| 92 | uint32_t reserved_64;
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| 93 | uint32_t reserved_65;
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| 94 | uint32_t reserved_66;
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| 95 | uint32_t reserved_67;
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| 96 | uint32_t reserved_68;
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| 97 | uint32_t reserved_69;
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| 98 | uint32_t reserved_70;
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| 99 | uint32_t reserved_71;
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| 100 | uint32_t reserved_72;
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| 101 | uint32_t reserved_73;
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| 102 | uint32_t reserved_74;
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| 103 | uint32_t reserved_75;
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| 104 | uint32_t reserved_76;
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| 105 | uint32_t reserved_77;
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| 106 | uint32_t reserved_78;
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| 107 | uint32_t reserved_79;
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| 108 | uint32_t reserved_80;
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| 109 | uint32_t reserved_81;
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| 110 | uint32_t reserved_82;
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| 111 | uint32_t reserved_83;
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| 112 | uint32_t reserved_84;
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| 113 | uint32_t reserved_85;
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| 114 | uint32_t reserved_86;
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| 115 | uint32_t reserved_87;
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| 116 | uint32_t reserved_88;
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| 117 | uint32_t reserved_89;
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| 118 | uint32_t reserved_90;
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| 119 | uint32_t reserved_91;
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| 120 | uint32_t reserved_92;
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| 121 | uint32_t reserved_93;
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| 122 | uint32_t reserved_94;
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| 123 | uint32_t reserved_95;
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| 124 | uint32_t reserved_96;
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| 125 | uint32_t reserved_97;
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| 126 | uint32_t reserved_98;
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| 127 | uint32_t reserved_99;
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| 128 | uint32_t reserved_100;
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| 129 | uint32_t reserved_101;
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| 130 | uint32_t reserved_102;
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| 131 | uint32_t reserved_103;
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| 132 | uint32_t reserved_104;
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| 133 | uint32_t reserved_105;
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| 134 | uint32_t reserved_106;
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| 135 | uint32_t reserved_107;
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| 136 | uint32_t reserved_108;
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| 137 | uint32_t reserved_109;
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| 138 | uint32_t reserved_110;
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| 139 | uint32_t reserved_111;
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| 140 | uint32_t reserved_112;
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| 141 | uint32_t reserved_113;
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| 142 | uint32_t reserved_114;
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| 143 | uint32_t reserved_115;
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| 144 | uint32_t reserved_116;
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| 145 | uint32_t reserved_117;
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| 146 | uint32_t reserved_118;
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| 147 | uint32_t reserved_119;
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| 148 | uint32_t reserved_120;
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| 149 | uint32_t reserved_121;
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| 150 | uint32_t reserved_122;
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| 151 | uint32_t reserved_123;
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| 152 | uint32_t reserved_124;
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| 153 | uint32_t reserved_125;
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| 154 |
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| 155 | uint32_t sdma_engine_id;
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| 156 | uint32_t sdma_queue_id;
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| 157 | };
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| 158 |
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| 159 | struct vi_mqd {
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| 160 | uint32_t header;
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| 161 | uint32_t compute_dispatch_initiator;
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| 162 | uint32_t compute_dim_x;
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| 163 | uint32_t compute_dim_y;
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| 164 | uint32_t compute_dim_z;
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| 165 | uint32_t compute_start_x;
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| 166 | uint32_t compute_start_y;
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| 167 | uint32_t compute_start_z;
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| 168 | uint32_t compute_num_thread_x;
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| 169 | uint32_t compute_num_thread_y;
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| 170 | uint32_t compute_num_thread_z;
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| 171 | uint32_t compute_pipelinestat_enable;
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| 172 | uint32_t compute_perfcount_enable;
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| 173 | uint32_t compute_pgm_lo;
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| 174 | uint32_t compute_pgm_hi;
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| 175 | uint32_t compute_tba_lo;
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| 176 | uint32_t compute_tba_hi;
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| 177 | uint32_t compute_tma_lo;
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| 178 | uint32_t compute_tma_hi;
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| 179 | uint32_t compute_pgm_rsrc1;
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| 180 | uint32_t compute_pgm_rsrc2;
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| 181 | uint32_t compute_vmid;
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| 182 | uint32_t compute_resource_limits;
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| 183 | uint32_t compute_static_thread_mgmt_se0;
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| 184 | uint32_t compute_static_thread_mgmt_se1;
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| 185 | uint32_t compute_tmpring_size;
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| 186 | uint32_t compute_static_thread_mgmt_se2;
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| 187 | uint32_t compute_static_thread_mgmt_se3;
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| 188 | uint32_t compute_restart_x;
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| 189 | uint32_t compute_restart_y;
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| 190 | uint32_t compute_restart_z;
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| 191 | uint32_t compute_thread_trace_enable;
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| 192 | uint32_t compute_misc_reserved;
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| 193 | uint32_t compute_dispatch_id;
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| 194 | uint32_t compute_threadgroup_id;
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| 195 | uint32_t compute_relaunch;
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| 196 | uint32_t compute_wave_restore_addr_lo;
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| 197 | uint32_t compute_wave_restore_addr_hi;
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| 198 | uint32_t compute_wave_restore_control;
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| 199 | uint32_t reserved9;
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| 200 | uint32_t reserved10;
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| 201 | uint32_t reserved11;
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| 202 | uint32_t reserved12;
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| 203 | uint32_t reserved13;
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| 204 | uint32_t reserved14;
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| 205 | uint32_t reserved15;
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| 206 | uint32_t reserved16;
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| 207 | uint32_t reserved17;
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| 208 | uint32_t reserved18;
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| 209 | uint32_t reserved19;
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| 210 | uint32_t reserved20;
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| 211 | uint32_t reserved21;
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| 212 | uint32_t reserved22;
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| 213 | uint32_t reserved23;
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| 214 | uint32_t reserved24;
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| 215 | uint32_t reserved25;
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| 216 | uint32_t reserved26;
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| 217 | uint32_t reserved27;
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| 218 | uint32_t reserved28;
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| 219 | uint32_t reserved29;
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| 220 | uint32_t reserved30;
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| 221 | uint32_t reserved31;
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| 222 | uint32_t reserved32;
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| 223 | uint32_t reserved33;
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| 224 | uint32_t reserved34;
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| 225 | uint32_t compute_user_data_0;
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| 226 | uint32_t compute_user_data_1;
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| 227 | uint32_t compute_user_data_2;
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| 228 | uint32_t compute_user_data_3;
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| 229 | uint32_t compute_user_data_4;
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| 230 | uint32_t compute_user_data_5;
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| 231 | uint32_t compute_user_data_6;
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| 232 | uint32_t compute_user_data_7;
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| 233 | uint32_t compute_user_data_8;
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| 234 | uint32_t compute_user_data_9;
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| 235 | uint32_t compute_user_data_10;
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| 236 | uint32_t compute_user_data_11;
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| 237 | uint32_t compute_user_data_12;
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| 238 | uint32_t compute_user_data_13;
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| 239 | uint32_t compute_user_data_14;
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| 240 | uint32_t compute_user_data_15;
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| 241 | uint32_t cp_compute_csinvoc_count_lo;
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| 242 | uint32_t cp_compute_csinvoc_count_hi;
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| 243 | uint32_t reserved35;
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| 244 | uint32_t reserved36;
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| 245 | uint32_t reserved37;
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| 246 | uint32_t cp_mqd_query_time_lo;
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| 247 | uint32_t cp_mqd_query_time_hi;
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| 248 | uint32_t cp_mqd_connect_start_time_lo;
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| 249 | uint32_t cp_mqd_connect_start_time_hi;
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| 250 | uint32_t cp_mqd_connect_end_time_lo;
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| 251 | uint32_t cp_mqd_connect_end_time_hi;
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| 252 | uint32_t cp_mqd_connect_end_wf_count;
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| 253 | uint32_t cp_mqd_connect_end_pq_rptr;
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| 254 | uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;
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| 255 | uint32_t cp_mqd_connect_end_ib_rptr;
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| 256 | uint32_t reserved38;
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| 257 | uint32_t reserved39;
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| 258 | uint32_t cp_mqd_save_start_time_lo;
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| 259 | uint32_t cp_mqd_save_start_time_hi;
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| 260 | uint32_t cp_mqd_save_end_time_lo;
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| 261 | uint32_t cp_mqd_save_end_time_hi;
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| 262 | uint32_t cp_mqd_restore_start_time_lo;
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| 263 | uint32_t cp_mqd_restore_start_time_hi;
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| 264 | uint32_t cp_mqd_restore_end_time_lo;
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| 265 | uint32_t cp_mqd_restore_end_time_hi;
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| 266 | uint32_t disable_queue;
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| 267 | uint32_t reserved41;
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| 268 | uint32_t gds_cs_ctxsw_cnt0;
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| 269 | uint32_t gds_cs_ctxsw_cnt1;
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| 270 | uint32_t gds_cs_ctxsw_cnt2;
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| 271 | uint32_t gds_cs_ctxsw_cnt3;
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| 272 | uint32_t reserved42;
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| 273 | uint32_t reserved43;
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| 274 | uint32_t cp_pq_exe_status_lo;
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| 275 | uint32_t cp_pq_exe_status_hi;
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| 276 | uint32_t cp_packet_id_lo;
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| 277 | uint32_t cp_packet_id_hi;
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| 278 | uint32_t cp_packet_exe_status_lo;
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| 279 | uint32_t cp_packet_exe_status_hi;
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| 280 | uint32_t gds_save_base_addr_lo;
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| 281 | uint32_t gds_save_base_addr_hi;
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| 282 | uint32_t gds_save_mask_lo;
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| 283 | uint32_t gds_save_mask_hi;
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| 284 | uint32_t ctx_save_base_addr_lo;
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| 285 | uint32_t ctx_save_base_addr_hi;
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| 286 | uint32_t dynamic_cu_mask_addr_lo;
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| 287 | uint32_t dynamic_cu_mask_addr_hi;
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| 288 | uint32_t cp_mqd_base_addr_lo;
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| 289 | uint32_t cp_mqd_base_addr_hi;
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| 290 | uint32_t cp_hqd_active;
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| 291 | uint32_t cp_hqd_vmid;
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| 292 | uint32_t cp_hqd_persistent_state;
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| 293 | uint32_t cp_hqd_pipe_priority;
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| 294 | uint32_t cp_hqd_queue_priority;
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| 295 | uint32_t cp_hqd_quantum;
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| 296 | uint32_t cp_hqd_pq_base_lo;
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| 297 | uint32_t cp_hqd_pq_base_hi;
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| 298 | uint32_t cp_hqd_pq_rptr;
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| 299 | uint32_t cp_hqd_pq_rptr_report_addr_lo;
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| 300 | uint32_t cp_hqd_pq_rptr_report_addr_hi;
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| 301 | uint32_t cp_hqd_pq_wptr_poll_addr_lo;
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| 302 | uint32_t cp_hqd_pq_wptr_poll_addr_hi;
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| 303 | uint32_t cp_hqd_pq_doorbell_control;
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| 304 | uint32_t cp_hqd_pq_wptr;
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| 305 | uint32_t cp_hqd_pq_control;
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| 306 | uint32_t cp_hqd_ib_base_addr_lo;
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| 307 | uint32_t cp_hqd_ib_base_addr_hi;
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| 308 | uint32_t cp_hqd_ib_rptr;
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| 309 | uint32_t cp_hqd_ib_control;
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| 310 | uint32_t cp_hqd_iq_timer;
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| 311 | uint32_t cp_hqd_iq_rptr;
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| 312 | uint32_t cp_hqd_dequeue_request;
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| 313 | uint32_t cp_hqd_dma_offload;
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| 314 | uint32_t cp_hqd_sema_cmd;
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| 315 | uint32_t cp_hqd_msg_type;
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| 316 | uint32_t cp_hqd_atomic0_preop_lo;
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| 317 | uint32_t cp_hqd_atomic0_preop_hi;
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| 318 | uint32_t cp_hqd_atomic1_preop_lo;
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| 319 | uint32_t cp_hqd_atomic1_preop_hi;
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| 320 | uint32_t cp_hqd_hq_status0;
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| 321 | uint32_t cp_hqd_hq_control0;
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| 322 | uint32_t cp_mqd_control;
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| 323 | uint32_t cp_hqd_hq_status1;
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| 324 | uint32_t cp_hqd_hq_control1;
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| 325 | uint32_t cp_hqd_eop_base_addr_lo;
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| 326 | uint32_t cp_hqd_eop_base_addr_hi;
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| 327 | uint32_t cp_hqd_eop_control;
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| 328 | uint32_t cp_hqd_eop_rptr;
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| 329 | uint32_t cp_hqd_eop_wptr;
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| 330 | uint32_t cp_hqd_eop_done_events;
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| 331 | uint32_t cp_hqd_ctx_save_base_addr_lo;
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| 332 | uint32_t cp_hqd_ctx_save_base_addr_hi;
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| 333 | uint32_t cp_hqd_ctx_save_control;
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| 334 | uint32_t cp_hqd_cntl_stack_offset;
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| 335 | uint32_t cp_hqd_cntl_stack_size;
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| 336 | uint32_t cp_hqd_wg_state_offset;
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| 337 | uint32_t cp_hqd_ctx_save_size;
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| 338 | uint32_t cp_hqd_gds_resource_state;
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| 339 | uint32_t cp_hqd_error;
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| 340 | uint32_t cp_hqd_eop_wptr_mem;
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| 341 | uint32_t cp_hqd_eop_dones;
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| 342 | uint32_t reserved46;
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| 343 | uint32_t reserved47;
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| 344 | uint32_t reserved48;
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| 345 | uint32_t reserved49;
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| 346 | uint32_t reserved50;
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| 347 | uint32_t reserved51;
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| 348 | uint32_t reserved52;
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| 349 | uint32_t reserved53;
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| 350 | uint32_t reserved54;
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| 351 | uint32_t reserved55;
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| 352 | uint32_t iqtimer_pkt_header;
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| 353 | uint32_t iqtimer_pkt_dw0;
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| 354 | uint32_t iqtimer_pkt_dw1;
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| 355 | uint32_t iqtimer_pkt_dw2;
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| 356 | uint32_t iqtimer_pkt_dw3;
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| 357 | uint32_t iqtimer_pkt_dw4;
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| 358 | uint32_t iqtimer_pkt_dw5;
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| 359 | uint32_t iqtimer_pkt_dw6;
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| 360 | uint32_t iqtimer_pkt_dw7;
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| 361 | uint32_t iqtimer_pkt_dw8;
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| 362 | uint32_t iqtimer_pkt_dw9;
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| 363 | uint32_t iqtimer_pkt_dw10;
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| 364 | uint32_t iqtimer_pkt_dw11;
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| 365 | uint32_t iqtimer_pkt_dw12;
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| 366 | uint32_t iqtimer_pkt_dw13;
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| 367 | uint32_t iqtimer_pkt_dw14;
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| 368 | uint32_t iqtimer_pkt_dw15;
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| 369 | uint32_t iqtimer_pkt_dw16;
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| 370 | uint32_t iqtimer_pkt_dw17;
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| 371 | uint32_t iqtimer_pkt_dw18;
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| 372 | uint32_t iqtimer_pkt_dw19;
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| 373 | uint32_t iqtimer_pkt_dw20;
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| 374 | uint32_t iqtimer_pkt_dw21;
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| 375 | uint32_t iqtimer_pkt_dw22;
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| 376 | uint32_t iqtimer_pkt_dw23;
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| 377 | uint32_t iqtimer_pkt_dw24;
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| 378 | uint32_t iqtimer_pkt_dw25;
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| 379 | uint32_t iqtimer_pkt_dw26;
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| 380 | uint32_t iqtimer_pkt_dw27;
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| 381 | uint32_t iqtimer_pkt_dw28;
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| 382 | uint32_t iqtimer_pkt_dw29;
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| 383 | uint32_t iqtimer_pkt_dw30;
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| 384 | uint32_t iqtimer_pkt_dw31;
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| 385 | uint32_t reserved56;
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| 386 | uint32_t reserved57;
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| 387 | uint32_t reserved58;
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| 388 | uint32_t set_resources_header;
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| 389 | uint32_t set_resources_dw1;
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| 390 | uint32_t set_resources_dw2;
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| 391 | uint32_t set_resources_dw3;
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| 392 | uint32_t set_resources_dw4;
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| 393 | uint32_t set_resources_dw5;
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| 394 | uint32_t set_resources_dw6;
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| 395 | uint32_t set_resources_dw7;
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| 396 | uint32_t reserved59;
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| 397 | uint32_t reserved60;
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| 398 | uint32_t reserved61;
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| 399 | uint32_t reserved62;
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| 400 | uint32_t queue_doorbell_id0;
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| 401 | uint32_t queue_doorbell_id1;
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| 402 | uint32_t queue_doorbell_id2;
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| 403 | uint32_t queue_doorbell_id3;
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| 404 | uint32_t queue_doorbell_id4;
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| 405 | uint32_t queue_doorbell_id5;
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| 406 | uint32_t queue_doorbell_id6;
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| 407 | uint32_t queue_doorbell_id7;
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| 408 | uint32_t queue_doorbell_id8;
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| 409 | uint32_t queue_doorbell_id9;
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| 410 | uint32_t queue_doorbell_id10;
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| 411 | uint32_t queue_doorbell_id11;
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| 412 | uint32_t queue_doorbell_id12;
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| 413 | uint32_t queue_doorbell_id13;
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| 414 | uint32_t queue_doorbell_id14;
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| 415 | uint32_t queue_doorbell_id15;
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| 416 | uint32_t reserved_t[256];
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| 417 | };
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| 418 |
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| 419 | struct vi_mqd_allocation {
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| 420 | struct vi_mqd mqd;
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| 421 | uint32_t wptr_poll_mem;
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| 422 | uint32_t rptr_report_mem;
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| 423 | uint32_t dynamic_cu_mask;
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| 424 | uint32_t dynamic_rb_mask;
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| 425 | };
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| 426 |
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| 427 | struct vi_ce_ib_state {
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| 428 | uint32_t ce_ib_completion_status;
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| 429 | uint32_t ce_constegnine_count;
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| 430 | uint32_t ce_ibOffset_ib1;
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| 431 | uint32_t ce_ibOffset_ib2;
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| 432 | };
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| 433 |
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| 434 | struct vi_de_ib_state {
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| 435 | uint32_t ib_completion_status;
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| 436 | uint32_t de_constEngine_count;
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| 437 | uint32_t ib_offset_ib1;
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| 438 | uint32_t ib_offset_ib2;
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| 439 | uint32_t preamble_begin_ib1;
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| 440 | uint32_t preamble_begin_ib2;
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| 441 | uint32_t preamble_end_ib1;
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| 442 | uint32_t preamble_end_ib2;
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| 443 | uint32_t draw_indirect_baseLo;
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| 444 | uint32_t draw_indirect_baseHi;
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| 445 | uint32_t disp_indirect_baseLo;
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| 446 | uint32_t disp_indirect_baseHi;
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| 447 | uint32_t gds_backup_addrlo;
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| 448 | uint32_t gds_backup_addrhi;
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| 449 | uint32_t index_base_addrlo;
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| 450 | uint32_t index_base_addrhi;
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| 451 | uint32_t sample_cntl;
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| 452 | };
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| 453 |
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| 454 | struct vi_ce_ib_state_chained_ib {
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| 455 |
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| 456 | uint32_t ce_ib_completion_status;
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| 457 | uint32_t ce_constegnine_count;
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| 458 | uint32_t ce_ibOffset_ib1;
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| 459 | uint32_t ce_ibOffset_ib2;
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| 460 |
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| 461 |
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| 462 | uint32_t ce_chainib_addrlo_ib1;
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| 463 | uint32_t ce_chainib_addrlo_ib2;
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| 464 | uint32_t ce_chainib_addrhi_ib1;
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| 465 | uint32_t ce_chainib_addrhi_ib2;
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| 466 | uint32_t ce_chainib_size_ib1;
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| 467 | uint32_t ce_chainib_size_ib2;
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| 468 | };
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| 469 |
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| 470 | struct vi_de_ib_state_chained_ib {
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| 471 |
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| 472 | uint32_t ib_completion_status;
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| 473 | uint32_t de_constEngine_count;
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| 474 | uint32_t ib_offset_ib1;
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| 475 | uint32_t ib_offset_ib2;
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| 476 |
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| 477 |
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| 478 | uint32_t chain_ib_addrlo_ib1;
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| 479 | uint32_t chain_ib_addrlo_ib2;
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| 480 | uint32_t chain_ib_addrhi_ib1;
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| 481 | uint32_t chain_ib_addrhi_ib2;
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| 482 | uint32_t chain_ib_size_ib1;
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| 483 | uint32_t chain_ib_size_ib2;
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| 484 |
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| 485 |
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| 486 | uint32_t preamble_begin_ib1;
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| 487 | uint32_t preamble_begin_ib2;
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| 488 | uint32_t preamble_end_ib1;
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| 489 | uint32_t preamble_end_ib2;
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| 490 |
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| 491 |
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| 492 | uint32_t chain_ib_pream_addrlo_ib1;
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| 493 | uint32_t chain_ib_pream_addrlo_ib2;
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| 494 | uint32_t chain_ib_pream_addrhi_ib1;
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| 495 | uint32_t chain_ib_pream_addrhi_ib2;
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| 496 |
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| 497 |
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| 498 | uint32_t draw_indirect_baseLo;
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| 499 | uint32_t draw_indirect_baseHi;
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| 500 | uint32_t disp_indirect_baseLo;
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| 501 | uint32_t disp_indirect_baseHi;
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| 502 | uint32_t gds_backup_addrlo;
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| 503 | uint32_t gds_backup_addrhi;
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| 504 | uint32_t index_base_addrlo;
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| 505 | uint32_t index_base_addrhi;
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| 506 | uint32_t sample_cntl;
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| 507 | };
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| 508 |
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| 509 | struct vi_gfx_meta_data {
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| 510 |
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| 511 | struct vi_ce_ib_state ce_payload;
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| 512 | uint32_t reserved1[60];
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| 513 |
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| 514 | struct vi_de_ib_state de_payload;
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| 515 |
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| 516 | uint32_t DeIbBaseAddrLo;
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| 517 | uint32_t DeIbBaseAddrHi;
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| 518 | uint32_t reserved2[941];
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| 519 | };
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| 520 |
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| 521 | struct vi_gfx_meta_data_chained_ib {
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| 522 |
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| 523 | struct vi_ce_ib_state_chained_ib ce_payload;
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| 524 | uint32_t reserved1[54];
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| 525 |
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| 526 | struct vi_de_ib_state_chained_ib de_payload;
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| 527 |
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| 528 | uint32_t DeIbBaseAddrLo;
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| 529 | uint32_t DeIbBaseAddrHi;
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| 530 | uint32_t reserved2[931];
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| 531 | };
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| 532 |
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| 533 | #endif
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