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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Linus Walleij <[email protected]>
4 * Parts of this file were based on the MCDE driver by Marcus Lorentzon
5 * (C) ST-Ericsson SA 2013
6 */
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/dma-buf.h>
10#include <linux/regulator/consumer.h>
11#include <linux/media-bus-format.h>
12
13#include <drm/drm_device.h>
14#include <drm/drm_fb_dma_helper.h>
15#include <drm/drm_fourcc.h>
16#include <drm/drm_framebuffer.h>
17#include <drm/drm_gem_atomic_helper.h>
18#include <drm/drm_gem_dma_helper.h>
19#include <drm/drm_mipi_dsi.h>
20#include <drm/drm_print.h>
21#include <drm/drm_simple_kms_helper.h>
22#include <drm/drm_bridge.h>
23#include <drm/drm_vblank.h>
24#include <video/mipi_display.h>
25
26#include "mcde_drm.h"
27#include "mcde_display_regs.h"
28
29enum mcde_fifo {
30 MCDE_FIFO_A,
31 MCDE_FIFO_B,
32 /* TODO: implement FIFO C0 and FIFO C1 */
33};
34
35enum mcde_channel {
36 MCDE_CHANNEL_0 = 0,
37 MCDE_CHANNEL_1,
38 MCDE_CHANNEL_2,
39 MCDE_CHANNEL_3,
40};
41
42enum mcde_extsrc {
43 MCDE_EXTSRC_0 = 0,
44 MCDE_EXTSRC_1,
45 MCDE_EXTSRC_2,
46 MCDE_EXTSRC_3,
47 MCDE_EXTSRC_4,
48 MCDE_EXTSRC_5,
49 MCDE_EXTSRC_6,
50 MCDE_EXTSRC_7,
51 MCDE_EXTSRC_8,
52 MCDE_EXTSRC_9,
53};
54
55enum mcde_overlay {
56 MCDE_OVERLAY_0 = 0,
57 MCDE_OVERLAY_1,
58 MCDE_OVERLAY_2,
59 MCDE_OVERLAY_3,
60 MCDE_OVERLAY_4,
61 MCDE_OVERLAY_5,
62};
63
64enum mcde_formatter {
65 MCDE_DSI_FORMATTER_0 = 0,
66 MCDE_DSI_FORMATTER_1,
67 MCDE_DSI_FORMATTER_2,
68 MCDE_DSI_FORMATTER_3,
69 MCDE_DSI_FORMATTER_4,
70 MCDE_DSI_FORMATTER_5,
71 MCDE_DPI_FORMATTER_0,
72 MCDE_DPI_FORMATTER_1,
73};
74
75void mcde_display_irq(struct mcde *mcde)
76{
77 u32 mispp, misovl, mischnl;
78 bool vblank = false;
79
80 /* Handle display IRQs */
81 mispp = readl(mcde->regs + MCDE_MISPP);
82 misovl = readl(mcde->regs + MCDE_MISOVL);
83 mischnl = readl(mcde->regs + MCDE_MISCHNL);
84
85 /*
86 * Handle IRQs from the DSI link. All IRQs from the DSI links
87 * are just latched onto the MCDE IRQ line, so we need to traverse
88 * any active DSI masters and check if an IRQ is originating from
89 * them.
90 *
91 * TODO: Currently only one DSI link is supported.
92 */
93 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) {
94 u32 val;
95
96 /*
97 * In oneshot mode we do not send continuous updates
98 * to the display, instead we only push out updates when
99 * the update function is called, then we disable the
100 * flow on the channel once we get the TE IRQ.
101 */
102 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
103 spin_lock(&mcde->flow_lock);
104 if (--mcde->flow_active == 0) {
105 dev_dbg(mcde->dev, "TE0 IRQ\n");
106 /* Disable FIFO A flow */
107 val = readl(mcde->regs + MCDE_CRA0);
108 val &= ~MCDE_CRX0_FLOEN;
109 writel(val, mcde->regs + MCDE_CRA0);
110 }
111 spin_unlock(&mcde->flow_lock);
112 }
113 }
114
115 /* Vblank from one of the channels */
116 if (mispp & MCDE_PP_VCMPA) {
117 dev_dbg(mcde->dev, "chnl A vblank IRQ\n");
118 vblank = true;
119 }
120 if (mispp & MCDE_PP_VCMPB) {
121 dev_dbg(mcde->dev, "chnl B vblank IRQ\n");
122 vblank = true;
123 }
124 if (mispp & MCDE_PP_VCMPC0)
125 dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n");
126 if (mispp & MCDE_PP_VCMPC1)
127 dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n");
128 if (mispp & MCDE_PP_VSCC0)
129 dev_dbg(mcde->dev, "chnl C0 TE IRQ\n");
130 if (mispp & MCDE_PP_VSCC1)
131 dev_dbg(mcde->dev, "chnl C1 TE IRQ\n");
132 writel(mispp, mcde->regs + MCDE_RISPP);
133
134 if (vblank)
135 drm_crtc_handle_vblank(&mcde->pipe.crtc);
136
137 if (misovl)
138 dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl);
139 writel(misovl, mcde->regs + MCDE_RISOVL);
140
141 if (mischnl)
142 dev_info(mcde->dev, "some stray channel error IRQ %08x\n",
143 mischnl);
144 writel(mischnl, mcde->regs + MCDE_RISCHNL);
145}
146
147void mcde_display_disable_irqs(struct mcde *mcde)
148{
149 /* Disable all IRQs */
150 writel(0, mcde->regs + MCDE_IMSCPP);
151 writel(0, mcde->regs + MCDE_IMSCOVL);
152 writel(0, mcde->regs + MCDE_IMSCCHNL);
153
154 /* Clear any pending IRQs */
155 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
156 writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);
157 writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);
158}
159
160static int mcde_display_check(struct drm_simple_display_pipe *pipe,
161 struct drm_plane_state *pstate,
162 struct drm_crtc_state *cstate)
163{
164 const struct drm_display_mode *mode = &cstate->mode;
165 struct drm_framebuffer *old_fb = pipe->plane.state->fb;
166 struct drm_framebuffer *fb = pstate->fb;
167
168 if (fb) {
169 u32 offset = drm_fb_dma_get_gem_addr(fb, pstate, 0);
170
171 /* FB base address must be dword aligned. */
172 if (offset & 3) {
173 DRM_DEBUG_KMS("FB not 32-bit aligned\n");
174 return -EINVAL;
175 }
176
177 /*
178 * There's no pitch register, the mode's hdisplay
179 * controls this.
180 */
181 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) {
182 DRM_DEBUG_KMS("can't handle pitches\n");
183 return -EINVAL;
184 }
185
186 /*
187 * We can't change the FB format in a flicker-free
188 * manner (and only update it during CRTC enable).
189 */
190 if (old_fb && old_fb->format != fb->format)
191 cstate->mode_changed = true;
192 }
193
194 return 0;
195}
196
197static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src,
198 u32 format)
199{
200 u32 val;
201 u32 conf;
202 u32 cr;
203
204 switch (src) {
205 case MCDE_EXTSRC_0:
206 conf = MCDE_EXTSRC0CONF;
207 cr = MCDE_EXTSRC0CR;
208 break;
209 case MCDE_EXTSRC_1:
210 conf = MCDE_EXTSRC1CONF;
211 cr = MCDE_EXTSRC1CR;
212 break;
213 case MCDE_EXTSRC_2:
214 conf = MCDE_EXTSRC2CONF;
215 cr = MCDE_EXTSRC2CR;
216 break;
217 case MCDE_EXTSRC_3:
218 conf = MCDE_EXTSRC3CONF;
219 cr = MCDE_EXTSRC3CR;
220 break;
221 case MCDE_EXTSRC_4:
222 conf = MCDE_EXTSRC4CONF;
223 cr = MCDE_EXTSRC4CR;
224 break;
225 case MCDE_EXTSRC_5:
226 conf = MCDE_EXTSRC5CONF;
227 cr = MCDE_EXTSRC5CR;
228 break;
229 case MCDE_EXTSRC_6:
230 conf = MCDE_EXTSRC6CONF;
231 cr = MCDE_EXTSRC6CR;
232 break;
233 case MCDE_EXTSRC_7:
234 conf = MCDE_EXTSRC7CONF;
235 cr = MCDE_EXTSRC7CR;
236 break;
237 case MCDE_EXTSRC_8:
238 conf = MCDE_EXTSRC8CONF;
239 cr = MCDE_EXTSRC8CR;
240 break;
241 case MCDE_EXTSRC_9:
242 conf = MCDE_EXTSRC9CONF;
243 cr = MCDE_EXTSRC9CR;
244 break;
245 }
246
247 /*
248 * Configure external source 0 one buffer (buffer 0)
249 * primary overlay ID 0.
250 * From mcde_hw.c ovly_update_registers() in the vendor tree
251 */
252 val = 0 << MCDE_EXTSRCXCONF_BUF_ID_SHIFT;
253 val |= 1 << MCDE_EXTSRCXCONF_BUF_NB_SHIFT;
254 val |= 0 << MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT;
255
256 switch (format) {
257 case DRM_FORMAT_ARGB8888:
258 val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 <<
259 MCDE_EXTSRCXCONF_BPP_SHIFT;
260 break;
261 case DRM_FORMAT_ABGR8888:
262 val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 <<
263 MCDE_EXTSRCXCONF_BPP_SHIFT;
264 val |= MCDE_EXTSRCXCONF_BGR;
265 break;
266 case DRM_FORMAT_XRGB8888:
267 val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 <<
268 MCDE_EXTSRCXCONF_BPP_SHIFT;
269 break;
270 case DRM_FORMAT_XBGR8888:
271 val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 <<
272 MCDE_EXTSRCXCONF_BPP_SHIFT;
273 val |= MCDE_EXTSRCXCONF_BGR;
274 break;
275 case DRM_FORMAT_RGB888:
276 val |= MCDE_EXTSRCXCONF_BPP_RGB888 <<
277 MCDE_EXTSRCXCONF_BPP_SHIFT;
278 break;
279 case DRM_FORMAT_BGR888:
280 val |= MCDE_EXTSRCXCONF_BPP_RGB888 <<
281 MCDE_EXTSRCXCONF_BPP_SHIFT;
282 val |= MCDE_EXTSRCXCONF_BGR;
283 break;
284 case DRM_FORMAT_ARGB4444:
285 val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 <<
286 MCDE_EXTSRCXCONF_BPP_SHIFT;
287 break;
288 case DRM_FORMAT_ABGR4444:
289 val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 <<
290 MCDE_EXTSRCXCONF_BPP_SHIFT;
291 val |= MCDE_EXTSRCXCONF_BGR;
292 break;
293 case DRM_FORMAT_XRGB4444:
294 val |= MCDE_EXTSRCXCONF_BPP_RGB444 <<
295 MCDE_EXTSRCXCONF_BPP_SHIFT;
296 break;
297 case DRM_FORMAT_XBGR4444:
298 val |= MCDE_EXTSRCXCONF_BPP_RGB444 <<
299 MCDE_EXTSRCXCONF_BPP_SHIFT;
300 val |= MCDE_EXTSRCXCONF_BGR;
301 break;
302 case DRM_FORMAT_XRGB1555:
303 val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 <<
304 MCDE_EXTSRCXCONF_BPP_SHIFT;
305 break;
306 case DRM_FORMAT_XBGR1555:
307 val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 <<
308 MCDE_EXTSRCXCONF_BPP_SHIFT;
309 val |= MCDE_EXTSRCXCONF_BGR;
310 break;
311 case DRM_FORMAT_RGB565:
312 val |= MCDE_EXTSRCXCONF_BPP_RGB565 <<
313 MCDE_EXTSRCXCONF_BPP_SHIFT;
314 break;
315 case DRM_FORMAT_BGR565:
316 val |= MCDE_EXTSRCXCONF_BPP_RGB565 <<
317 MCDE_EXTSRCXCONF_BPP_SHIFT;
318 val |= MCDE_EXTSRCXCONF_BGR;
319 break;
320 case DRM_FORMAT_YUV422:
321 val |= MCDE_EXTSRCXCONF_BPP_YCBCR422 <<
322 MCDE_EXTSRCXCONF_BPP_SHIFT;
323 break;
324 default:
325 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
326 format);
327 return -EINVAL;
328 }
329 writel(val, mcde->regs + conf);
330
331 /* Software select, primary */
332 val = MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL;
333 val |= MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY;
334 writel(val, mcde->regs + cr);
335
336 return 0;
337}
338
339static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl,
340 enum mcde_extsrc src,
341 enum mcde_channel ch,
342 const struct drm_display_mode *mode,
343 u32 format, int cpp)
344{
345 u32 val;
346 u32 conf1;
347 u32 conf2;
348 u32 crop;
349 u32 ljinc;
350 u32 cr;
351 u32 comp;
352 u32 pixel_fetcher_watermark;
353
354 switch (ovl) {
355 case MCDE_OVERLAY_0:
356 conf1 = MCDE_OVL0CONF;
357 conf2 = MCDE_OVL0CONF2;
358 crop = MCDE_OVL0CROP;
359 ljinc = MCDE_OVL0LJINC;
360 cr = MCDE_OVL0CR;
361 comp = MCDE_OVL0COMP;
362 break;
363 case MCDE_OVERLAY_1:
364 conf1 = MCDE_OVL1CONF;
365 conf2 = MCDE_OVL1CONF2;
366 crop = MCDE_OVL1CROP;
367 ljinc = MCDE_OVL1LJINC;
368 cr = MCDE_OVL1CR;
369 comp = MCDE_OVL1COMP;
370 break;
371 case MCDE_OVERLAY_2:
372 conf1 = MCDE_OVL2CONF;
373 conf2 = MCDE_OVL2CONF2;
374 crop = MCDE_OVL2CROP;
375 ljinc = MCDE_OVL2LJINC;
376 cr = MCDE_OVL2CR;
377 comp = MCDE_OVL2COMP;
378 break;
379 case MCDE_OVERLAY_3:
380 conf1 = MCDE_OVL3CONF;
381 conf2 = MCDE_OVL3CONF2;
382 crop = MCDE_OVL3CROP;
383 ljinc = MCDE_OVL3LJINC;
384 cr = MCDE_OVL3CR;
385 comp = MCDE_OVL3COMP;
386 break;
387 case MCDE_OVERLAY_4:
388 conf1 = MCDE_OVL4CONF;
389 conf2 = MCDE_OVL4CONF2;
390 crop = MCDE_OVL4CROP;
391 ljinc = MCDE_OVL4LJINC;
392 cr = MCDE_OVL4CR;
393 comp = MCDE_OVL4COMP;
394 break;
395 case MCDE_OVERLAY_5:
396 conf1 = MCDE_OVL5CONF;
397 conf2 = MCDE_OVL5CONF2;
398 crop = MCDE_OVL5CROP;
399 ljinc = MCDE_OVL5LJINC;
400 cr = MCDE_OVL5CR;
401 comp = MCDE_OVL5COMP;
402 break;
403 }
404
405 val = mode->hdisplay << MCDE_OVLXCONF_PPL_SHIFT;
406 val |= mode->vdisplay << MCDE_OVLXCONF_LPF_SHIFT;
407 /* Use external source 0 that we just configured */
408 val |= src << MCDE_OVLXCONF_EXTSRC_ID_SHIFT;
409 writel(val, mcde->regs + conf1);
410
411 val = MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA;
412 val |= 0xff << MCDE_OVLXCONF2_ALPHAVALUE_SHIFT;
413 /* OPQ: overlay is opaque */
414 switch (format) {
415 case DRM_FORMAT_ARGB8888:
416 case DRM_FORMAT_ABGR8888:
417 case DRM_FORMAT_ARGB4444:
418 case DRM_FORMAT_ABGR4444:
419 case DRM_FORMAT_XRGB1555:
420 case DRM_FORMAT_XBGR1555:
421 /* No OPQ */
422 break;
423 case DRM_FORMAT_XRGB8888:
424 case DRM_FORMAT_XBGR8888:
425 case DRM_FORMAT_RGB888:
426 case DRM_FORMAT_BGR888:
427 case DRM_FORMAT_RGB565:
428 case DRM_FORMAT_BGR565:
429 case DRM_FORMAT_YUV422:
430 val |= MCDE_OVLXCONF2_OPQ;
431 break;
432 default:
433 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
434 format);
435 break;
436 }
437
438 /*
439 * Pixel fetch watermark level is max 0x1FFF pixels.
440 * Two basic rules should be followed:
441 * 1. The value should be at least 256 bits.
442 * 2. The sum of all active overlays pixelfetch watermark level
443 * multiplied with bits per pixel, should be lower than the
444 * size of input_fifo_size in bits.
445 * 3. The value should be a multiple of a line (256 bits).
446 */
447 switch (cpp) {
448 case 2:
449 pixel_fetcher_watermark = 128;
450 break;
451 case 3:
452 pixel_fetcher_watermark = 96;
453 break;
454 case 4:
455 pixel_fetcher_watermark = 48;
456 break;
457 default:
458 pixel_fetcher_watermark = 48;
459 break;
460 }
461 dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n",
462 pixel_fetcher_watermark);
463 val |= pixel_fetcher_watermark << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT;
464 writel(val, mcde->regs + conf2);
465
466 /* Number of bytes to fetch per line */
467 writel(mcde->stride, mcde->regs + ljinc);
468 /* No cropping */
469 writel(0, mcde->regs + crop);
470
471 /* Set up overlay control register */
472 val = MCDE_OVLXCR_OVLEN;
473 val |= MCDE_OVLXCR_COLCCTRL_DISABLED;
474 val |= MCDE_OVLXCR_BURSTSIZE_8W <<
475 MCDE_OVLXCR_BURSTSIZE_SHIFT;
476 val |= MCDE_OVLXCR_MAXOUTSTANDING_8_REQ <<
477 MCDE_OVLXCR_MAXOUTSTANDING_SHIFT;
478 /* Not using rotation but set it up anyways */
479 val |= MCDE_OVLXCR_ROTBURSTSIZE_8W <<
480 MCDE_OVLXCR_ROTBURSTSIZE_SHIFT;
481 writel(val, mcde->regs + cr);
482
483 /*
484 * Set up the overlay compositor to route the overlay out to
485 * the desired channel
486 */
487 val = ch << MCDE_OVLXCOMP_CH_ID_SHIFT;
488 writel(val, mcde->regs + comp);
489}
490
491static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch,
492 enum mcde_fifo fifo,
493 const struct drm_display_mode *mode)
494{
495 u32 val;
496 u32 conf;
497 u32 sync;
498 u32 stat;
499 u32 bgcol;
500 u32 mux;
501
502 switch (ch) {
503 case MCDE_CHANNEL_0:
504 conf = MCDE_CHNL0CONF;
505 sync = MCDE_CHNL0SYNCHMOD;
506 stat = MCDE_CHNL0STAT;
507 bgcol = MCDE_CHNL0BCKGNDCOL;
508 mux = MCDE_CHNL0MUXING;
509 break;
510 case MCDE_CHANNEL_1:
511 conf = MCDE_CHNL1CONF;
512 sync = MCDE_CHNL1SYNCHMOD;
513 stat = MCDE_CHNL1STAT;
514 bgcol = MCDE_CHNL1BCKGNDCOL;
515 mux = MCDE_CHNL1MUXING;
516 break;
517 case MCDE_CHANNEL_2:
518 conf = MCDE_CHNL2CONF;
519 sync = MCDE_CHNL2SYNCHMOD;
520 stat = MCDE_CHNL2STAT;
521 bgcol = MCDE_CHNL2BCKGNDCOL;
522 mux = MCDE_CHNL2MUXING;
523 break;
524 case MCDE_CHANNEL_3:
525 conf = MCDE_CHNL3CONF;
526 sync = MCDE_CHNL3SYNCHMOD;
527 stat = MCDE_CHNL3STAT;
528 bgcol = MCDE_CHNL3BCKGNDCOL;
529 mux = MCDE_CHNL3MUXING;
530 return;
531 }
532
533 /* Set up channel 0 sync (based on chnl_update_registers()) */
534 switch (mcde->flow_mode) {
535 case MCDE_COMMAND_ONESHOT_FLOW:
536 /* Oneshot is achieved with software sync */
537 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE
538 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
539 break;
540 case MCDE_COMMAND_TE_FLOW:
541 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
542 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
543 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
544 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
545 break;
546 case MCDE_COMMAND_BTA_TE_FLOW:
547 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
548 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
549 /*
550 * TODO:
551 * The vendor driver uses the formatter as sync source
552 * for BTA TE mode. Test to use TE if you have a panel
553 * that uses this mode.
554 */
555 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
556 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
557 break;
558 case MCDE_VIDEO_TE_FLOW:
559 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
560 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
561 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
562 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
563 break;
564 case MCDE_VIDEO_FORMATTER_FLOW:
565 case MCDE_DPI_FORMATTER_FLOW:
566 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
567 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT;
568 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
569 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT;
570 break;
571 default:
572 dev_err(mcde->dev, "unknown flow mode %d\n",
573 mcde->flow_mode);
574 return;
575 }
576
577 writel(val, mcde->regs + sync);
578
579 /* Set up pixels per line and lines per frame */
580 val = (mode->hdisplay - 1) << MCDE_CHNLXCONF_PPL_SHIFT;
581 val |= (mode->vdisplay - 1) << MCDE_CHNLXCONF_LPF_SHIFT;
582 writel(val, mcde->regs + conf);
583
584 /*
585 * Normalize color conversion:
586 * black background, OLED conversion disable on channel
587 */
588 val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN |
589 MCDE_CHNLXSTAT_CHNLRD;
590 writel(val, mcde->regs + stat);
591 writel(0, mcde->regs + bgcol);
592
593 /* Set up muxing: connect the channel to the desired FIFO */
594 switch (fifo) {
595 case MCDE_FIFO_A:
596 writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_A,
597 mcde->regs + mux);
598 break;
599 case MCDE_FIFO_B:
600 writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_B,
601 mcde->regs + mux);
602 break;
603 }
604
605 /*
606 * If using DPI configure the sync event.
607 * TODO: this is for LCD only, it does not cover TV out.
608 */
609 if (mcde->dpi_output) {
610 u32 stripwidth;
611
612 stripwidth = 0xF000 / (mode->vdisplay * 4);
613 dev_info(mcde->dev, "stripwidth: %d\n", stripwidth);
614
615 val = MCDE_SYNCHCONF_HWREQVEVENT_ACTIVE_VIDEO |
616 (mode->hdisplay - 1 - stripwidth) << MCDE_SYNCHCONF_HWREQVCNT_SHIFT |
617 MCDE_SYNCHCONF_SWINTVEVENT_ACTIVE_VIDEO |
618 (mode->hdisplay - 1 - stripwidth) << MCDE_SYNCHCONF_SWINTVCNT_SHIFT;
619
620 switch (fifo) {
621 case MCDE_FIFO_A:
622 writel(val, mcde->regs + MCDE_SYNCHCONFA);
623 break;
624 case MCDE_FIFO_B:
625 writel(val, mcde->regs + MCDE_SYNCHCONFB);
626 break;
627 }
628 }
629}
630
631static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo,
632 enum mcde_formatter fmt,
633 int fifo_wtrmrk)
634{
635 u32 val;
636 u32 ctrl;
637 u32 cr0, cr1;
638
639 switch (fifo) {
640 case MCDE_FIFO_A:
641 ctrl = MCDE_CTRLA;
642 cr0 = MCDE_CRA0;
643 cr1 = MCDE_CRA1;
644 break;
645 case MCDE_FIFO_B:
646 ctrl = MCDE_CTRLB;
647 cr0 = MCDE_CRB0;
648 cr1 = MCDE_CRB1;
649 break;
650 }
651
652 val = fifo_wtrmrk << MCDE_CTRLX_FIFOWTRMRK_SHIFT;
653
654 /*
655 * Select the formatter to use for this FIFO
656 *
657 * The register definitions imply that different IDs should be used
658 * by the DSI formatters depending on if they are in VID or CMD
659 * mode, and the manual says they are dedicated but identical.
660 * The vendor code uses them as it seems fit.
661 */
662 switch (fmt) {
663 case MCDE_DSI_FORMATTER_0:
664 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
665 val |= MCDE_CTRLX_FORMID_DSI0VID << MCDE_CTRLX_FORMID_SHIFT;
666 break;
667 case MCDE_DSI_FORMATTER_1:
668 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
669 val |= MCDE_CTRLX_FORMID_DSI0CMD << MCDE_CTRLX_FORMID_SHIFT;
670 break;
671 case MCDE_DSI_FORMATTER_2:
672 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
673 val |= MCDE_CTRLX_FORMID_DSI1VID << MCDE_CTRLX_FORMID_SHIFT;
674 break;
675 case MCDE_DSI_FORMATTER_3:
676 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
677 val |= MCDE_CTRLX_FORMID_DSI1CMD << MCDE_CTRLX_FORMID_SHIFT;
678 break;
679 case MCDE_DSI_FORMATTER_4:
680 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
681 val |= MCDE_CTRLX_FORMID_DSI2VID << MCDE_CTRLX_FORMID_SHIFT;
682 break;
683 case MCDE_DSI_FORMATTER_5:
684 val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
685 val |= MCDE_CTRLX_FORMID_DSI2CMD << MCDE_CTRLX_FORMID_SHIFT;
686 break;
687 case MCDE_DPI_FORMATTER_0:
688 val |= MCDE_CTRLX_FORMTYPE_DPITV << MCDE_CTRLX_FORMTYPE_SHIFT;
689 val |= MCDE_CTRLX_FORMID_DPIA << MCDE_CTRLX_FORMID_SHIFT;
690 break;
691 case MCDE_DPI_FORMATTER_1:
692 val |= MCDE_CTRLX_FORMTYPE_DPITV << MCDE_CTRLX_FORMTYPE_SHIFT;
693 val |= MCDE_CTRLX_FORMID_DPIB << MCDE_CTRLX_FORMID_SHIFT;
694 break;
695 }
696 writel(val, mcde->regs + ctrl);
697
698 /* Blend source with Alpha 0xff on FIFO */
699 val = MCDE_CRX0_BLENDEN |
700 0xff << MCDE_CRX0_ALPHABLEND_SHIFT;
701 writel(val, mcde->regs + cr0);
702
703 spin_lock(&mcde->fifo_crx1_lock);
704 val = readl(mcde->regs + cr1);
705 /*
706 * Set-up from mcde_fmtr_dsi.c, fmtr_dsi_enable_video()
707 * FIXME: a different clock needs to be selected for TV out.
708 */
709 if (mcde->dpi_output) {
710 struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);
711 u32 bus_format;
712
713 /* Assume RGB888 24 bit if we have no further info */
714 if (!connector->display_info.num_bus_formats) {
715 dev_info(mcde->dev, "panel does not specify bus format, assume RGB888\n");
716 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
717 } else {
718 bus_format = connector->display_info.bus_formats[0];
719 }
720
721 /*
722 * Set up the CDWIN and OUTBPP for the LCD
723 *
724 * FIXME: fill this in if you know the correspondance between the MIPI
725 * DPI specification and the media bus formats.
726 */
727 val &= ~MCDE_CRX1_CDWIN_MASK;
728 val &= ~MCDE_CRX1_OUTBPP_MASK;
729 switch (bus_format) {
730 case MEDIA_BUS_FMT_RGB888_1X24:
731 val |= MCDE_CRX1_CDWIN_24BPP << MCDE_CRX1_CDWIN_SHIFT;
732 val |= MCDE_CRX1_OUTBPP_24BPP << MCDE_CRX1_OUTBPP_SHIFT;
733 break;
734 default:
735 dev_err(mcde->dev, "unknown bus format, assume RGB888\n");
736 val |= MCDE_CRX1_CDWIN_24BPP << MCDE_CRX1_CDWIN_SHIFT;
737 val |= MCDE_CRX1_OUTBPP_24BPP << MCDE_CRX1_OUTBPP_SHIFT;
738 break;
739 }
740 } else {
741 /* Use the MCDE clock for DSI */
742 val &= ~MCDE_CRX1_CLKSEL_MASK;
743 val |= MCDE_CRX1_CLKSEL_MCDECLK << MCDE_CRX1_CLKSEL_SHIFT;
744 }
745 writel(val, mcde->regs + cr1);
746 spin_unlock(&mcde->fifo_crx1_lock);
747};
748
749static void mcde_configure_dsi_formatter(struct mcde *mcde,
750 enum mcde_formatter fmt,
751 u32 formatter_frame,
752 int pkt_size)
753{
754 u32 val;
755 u32 conf0;
756 u32 frame;
757 u32 pkt;
758 u32 sync;
759 u32 cmdw;
760 u32 delay0, delay1;
761
762 switch (fmt) {
763 case MCDE_DSI_FORMATTER_0:
764 conf0 = MCDE_DSIVID0CONF0;
765 frame = MCDE_DSIVID0FRAME;
766 pkt = MCDE_DSIVID0PKT;
767 sync = MCDE_DSIVID0SYNC;
768 cmdw = MCDE_DSIVID0CMDW;
769 delay0 = MCDE_DSIVID0DELAY0;
770 delay1 = MCDE_DSIVID0DELAY1;
771 break;
772 case MCDE_DSI_FORMATTER_1:
773 conf0 = MCDE_DSIVID1CONF0;
774 frame = MCDE_DSIVID1FRAME;
775 pkt = MCDE_DSIVID1PKT;
776 sync = MCDE_DSIVID1SYNC;
777 cmdw = MCDE_DSIVID1CMDW;
778 delay0 = MCDE_DSIVID1DELAY0;
779 delay1 = MCDE_DSIVID1DELAY1;
780 break;
781 case MCDE_DSI_FORMATTER_2:
782 conf0 = MCDE_DSIVID2CONF0;
783 frame = MCDE_DSIVID2FRAME;
784 pkt = MCDE_DSIVID2PKT;
785 sync = MCDE_DSIVID2SYNC;
786 cmdw = MCDE_DSIVID2CMDW;
787 delay0 = MCDE_DSIVID2DELAY0;
788 delay1 = MCDE_DSIVID2DELAY1;
789 break;
790 default:
791 dev_err(mcde->dev, "tried to configure a non-DSI formatter as DSI\n");
792 return;
793 }
794
795 /*
796 * Enable formatter
797 * 8 bit commands and DCS commands (notgen = not generic)
798 */
799 val = MCDE_DSICONF0_CMD8 | MCDE_DSICONF0_DCSVID_NOTGEN;
800 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
801 val |= MCDE_DSICONF0_VID_MODE_VID;
802 switch (mcde->mdsi->format) {
803 case MIPI_DSI_FMT_RGB888:
804 val |= MCDE_DSICONF0_PACKING_RGB888 <<
805 MCDE_DSICONF0_PACKING_SHIFT;
806 break;
807 case MIPI_DSI_FMT_RGB666:
808 val |= MCDE_DSICONF0_PACKING_RGB666 <<
809 MCDE_DSICONF0_PACKING_SHIFT;
810 break;
811 case MIPI_DSI_FMT_RGB666_PACKED:
812 dev_err(mcde->dev,
813 "we cannot handle the packed RGB666 format\n");
814 val |= MCDE_DSICONF0_PACKING_RGB666 <<
815 MCDE_DSICONF0_PACKING_SHIFT;
816 break;
817 case MIPI_DSI_FMT_RGB565:
818 val |= MCDE_DSICONF0_PACKING_RGB565 <<
819 MCDE_DSICONF0_PACKING_SHIFT;
820 break;
821 default:
822 dev_err(mcde->dev, "unknown DSI format\n");
823 return;
824 }
825 writel(val, mcde->regs + conf0);
826
827 writel(formatter_frame, mcde->regs + frame);
828 writel(pkt_size, mcde->regs + pkt);
829 writel(0, mcde->regs + sync);
830 /* Define the MIPI command: we want to write into display memory */
831 val = MIPI_DCS_WRITE_MEMORY_CONTINUE <<
832 MCDE_DSIVIDXCMDW_CMDW_CONTINUE_SHIFT;
833 val |= MIPI_DCS_WRITE_MEMORY_START <<
834 MCDE_DSIVIDXCMDW_CMDW_START_SHIFT;
835 writel(val, mcde->regs + cmdw);
836
837 /*
838 * FIXME: the vendor driver has some hack around this value in
839 * CMD mode with autotrig.
840 */
841 writel(0, mcde->regs + delay0);
842 writel(0, mcde->regs + delay1);
843}
844
845static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo)
846{
847 u32 val;
848 u32 cr;
849
850 switch (fifo) {
851 case MCDE_FIFO_A:
852 cr = MCDE_CRA0;
853 break;
854 case MCDE_FIFO_B:
855 cr = MCDE_CRB0;
856 break;
857 default:
858 dev_err(mcde->dev, "cannot enable FIFO %c\n",
859 'A' + fifo);
860 return;
861 }
862
863 spin_lock(&mcde->flow_lock);
864 val = readl(mcde->regs + cr);
865 val |= MCDE_CRX0_FLOEN;
866 writel(val, mcde->regs + cr);
867 mcde->flow_active++;
868 spin_unlock(&mcde->flow_lock);
869}
870
871static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo,
872 bool wait_for_drain)
873{
874 int timeout = 100;
875 u32 val;
876 u32 cr;
877
878 switch (fifo) {
879 case MCDE_FIFO_A:
880 cr = MCDE_CRA0;
881 break;
882 case MCDE_FIFO_B:
883 cr = MCDE_CRB0;
884 break;
885 default:
886 dev_err(mcde->dev, "cannot disable FIFO %c\n",
887 'A' + fifo);
888 return;
889 }
890
891 spin_lock(&mcde->flow_lock);
892 val = readl(mcde->regs + cr);
893 val &= ~MCDE_CRX0_FLOEN;
894 writel(val, mcde->regs + cr);
895 mcde->flow_active = 0;
896 spin_unlock(&mcde->flow_lock);
897
898 if (!wait_for_drain)
899 return;
900
901 /* Check that we really drained and stopped the flow */
902 while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {
903 usleep_range(1000, 1500);
904 if (!--timeout) {
905 dev_err(mcde->dev,
906 "FIFO timeout while clearing FIFO %c\n",
907 'A' + fifo);
908 return;
909 }
910 }
911}
912
913/*
914 * This drains a pipe i.e. a FIFO connected to a certain channel
915 */
916static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo,
917 enum mcde_channel ch)
918{
919 u32 val;
920 u32 ctrl;
921 u32 synsw;
922
923 switch (fifo) {
924 case MCDE_FIFO_A:
925 ctrl = MCDE_CTRLA;
926 break;
927 case MCDE_FIFO_B:
928 ctrl = MCDE_CTRLB;
929 break;
930 }
931
932 switch (ch) {
933 case MCDE_CHANNEL_0:
934 synsw = MCDE_CHNL0SYNCHSW;
935 break;
936 case MCDE_CHANNEL_1:
937 synsw = MCDE_CHNL1SYNCHSW;
938 break;
939 case MCDE_CHANNEL_2:
940 synsw = MCDE_CHNL2SYNCHSW;
941 break;
942 case MCDE_CHANNEL_3:
943 synsw = MCDE_CHNL3SYNCHSW;
944 return;
945 }
946
947 val = readl(mcde->regs + ctrl);
948 if (!(val & MCDE_CTRLX_FIFOEMPTY)) {
949 dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n");
950 /* Attempt to clear the FIFO */
951 mcde_enable_fifo(mcde, fifo);
952 /* Trigger a software sync out on respective channel (0-3) */
953 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);
954 /* Disable FIFO A flow again */
955 mcde_disable_fifo(mcde, fifo, true);
956 }
957}
958
959static int mcde_dsi_get_pkt_div(int ppl, int fifo_size)
960{
961 /*
962 * DSI command mode line packets should be split into an even number of
963 * packets smaller than or equal to the fifo size.
964 */
965 int div;
966 const int max_div = DIV_ROUND_UP(MCDE_MAX_WIDTH, fifo_size);
967
968 for (div = 1; div < max_div; div++)
969 if (ppl % div == 0 && ppl / div <= fifo_size)
970 return div;
971 return 1;
972}
973
974static void mcde_setup_dpi(struct mcde *mcde, const struct drm_display_mode *mode,
975 int *fifo_wtrmrk_lvl)
976{
977 struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);
978 u32 hsw, hfp, hbp;
979 u32 vsw, vfp, vbp;
980 u32 val;
981
982 /* FIXME: we only support LCD, implement TV out */
983 hsw = mode->hsync_end - mode->hsync_start;
984 hfp = mode->hsync_start - mode->hdisplay;
985 hbp = mode->htotal - mode->hsync_end;
986 vsw = mode->vsync_end - mode->vsync_start;
987 vfp = mode->vsync_start - mode->vdisplay;
988 vbp = mode->vtotal - mode->vsync_end;
989
990 dev_info(mcde->dev, "output on DPI LCD from channel A\n");
991 /* Display actual values */
992 dev_info(mcde->dev, "HSW: %d, HFP: %d, HBP: %d, VSW: %d, VFP: %d, VBP: %d\n",
993 hsw, hfp, hbp, vsw, vfp, vbp);
994
995 /*
996 * The pixel fetcher is 128 64-bit words deep = 1024 bytes.
997 * One overlay of 32bpp (4 cpp) assumed, fetch 160 pixels.
998 * 160 * 4 = 640 bytes.
999 */
1000 *fifo_wtrmrk_lvl = 640;
1001
1002 /* Set up the main control, watermark level at 7 */
1003 val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT;
1004
1005 /*
1006 * This sets up the internal silicon muxing of the DPI
1007 * lines. This is how the silicon connects out to the
1008 * external pins, then the pins need to be further
1009 * configured into "alternate functions" using pin control
1010 * to actually get the signals out.
1011 *
1012 * FIXME: this is hardcoded to the only setting found in
1013 * the wild. If we need to use different settings for
1014 * different DPI displays, make this parameterizable from
1015 * the device tree.
1016 */
1017 /* 24 bits DPI: connect Ch A LSB to D[0:7] */
1018 val |= 0 << MCDE_CONF0_OUTMUX0_SHIFT;
1019 /* 24 bits DPI: connect Ch A MID to D[8:15] */
1020 val |= 1 << MCDE_CONF0_OUTMUX1_SHIFT;
1021 /* Don't care about this muxing */
1022 val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT;
1023 /* Don't care about this muxing */
1024 val |= 0 << MCDE_CONF0_OUTMUX3_SHIFT;
1025 /* 24 bits DPI: connect Ch A MSB to D[32:39] */
1026 val |= 2 << MCDE_CONF0_OUTMUX4_SHIFT;
1027 /* Syncmux bits zero: DPI channel A */
1028 writel(val, mcde->regs + MCDE_CONF0);
1029
1030 /* This hammers us into LCD mode */
1031 writel(0, mcde->regs + MCDE_TVCRA);
1032
1033 /* Front porch and sync width */
1034 val = (vsw << MCDE_TVBL1_BEL1_SHIFT);
1035 val |= (vfp << MCDE_TVBL1_BSL1_SHIFT);
1036 writel(val, mcde->regs + MCDE_TVBL1A);
1037 /* The vendor driver sets the same value into TVBL2A */
1038 writel(val, mcde->regs + MCDE_TVBL2A);
1039
1040 /* Vertical back porch */
1041 val = (vbp << MCDE_TVDVO_DVO1_SHIFT);
1042 /* The vendor drivers sets the same value into TVDVOA */
1043 val |= (vbp << MCDE_TVDVO_DVO2_SHIFT);
1044 writel(val, mcde->regs + MCDE_TVDVOA);
1045
1046 /* Horizontal back porch, as 0 = 1 cycle we need to subtract 1 */
1047 writel((hbp - 1), mcde->regs + MCDE_TVTIM1A);
1048
1049 /* Horizongal sync width and horizonal front porch, 0 = 1 cycle */
1050 val = ((hsw - 1) << MCDE_TVLBALW_LBW_SHIFT);
1051 val |= ((hfp - 1) << MCDE_TVLBALW_ALW_SHIFT);
1052 writel(val, mcde->regs + MCDE_TVLBALWA);
1053
1054 /* Blank some TV registers we don't use */
1055 writel(0, mcde->regs + MCDE_TVISLA);
1056 writel(0, mcde->regs + MCDE_TVBLUA);
1057
1058 /* Set up sync inversion etc */
1059 val = 0;
1060 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1061 val |= MCDE_LCDTIM1B_IHS;
1062 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1063 val |= MCDE_LCDTIM1B_IVS;
1064 if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
1065 val |= MCDE_LCDTIM1B_IOE;
1066 if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
1067 val |= MCDE_LCDTIM1B_IPC;
1068 writel(val, mcde->regs + MCDE_LCDTIM1A);
1069}
1070
1071static void mcde_setup_dsi(struct mcde *mcde, const struct drm_display_mode *mode,
1072 int cpp, int *fifo_wtrmrk_lvl, int *dsi_formatter_frame,
1073 int *dsi_pkt_size)
1074{
1075 u32 formatter_ppl = mode->hdisplay; /* pixels per line */
1076 u32 formatter_lpf = mode->vdisplay; /* lines per frame */
1077 int formatter_frame;
1078 int formatter_cpp;
1079 int fifo_wtrmrk;
1080 u32 pkt_div;
1081 int pkt_size;
1082 u32 val;
1083
1084 dev_info(mcde->dev, "output in %s mode, format %dbpp\n",
1085 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ?
1086 "VIDEO" : "CMD",
1087 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format));
1088 formatter_cpp =
1089 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8;
1090 dev_info(mcde->dev, "Overlay CPP: %d bytes, DSI formatter CPP %d bytes\n",
1091 cpp, formatter_cpp);
1092
1093 /* Set up the main control, watermark level at 7 */
1094 val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT;
1095
1096 /*
1097 * This is the internal silicon muxing of the DPI
1098 * (parallell display) lines. Since we are not using
1099 * this at all (we are using DSI) these are just
1100 * dummy values from the vendor tree.
1101 */
1102 val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT;
1103 val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT;
1104 val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT;
1105 val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT;
1106 val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT;
1107 writel(val, mcde->regs + MCDE_CONF0);
1108
1109 /* Calculations from mcde_fmtr_dsi.c, fmtr_dsi_enable_video() */
1110
1111 /*
1112 * Set up FIFO A watermark level:
1113 * 128 for LCD 32bpp video mode
1114 * 48 for LCD 32bpp command mode
1115 * 128 for LCD 16bpp video mode
1116 * 64 for LCD 16bpp command mode
1117 * 128 for HDMI 32bpp
1118 * 192 for HDMI 16bpp
1119 */
1120 fifo_wtrmrk = mode->hdisplay;
1121 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1122 fifo_wtrmrk = min(fifo_wtrmrk, 128);
1123 pkt_div = 1;
1124 } else {
1125 fifo_wtrmrk = min(fifo_wtrmrk, 48);
1126 /* The FIFO is 640 entries deep on this v3 hardware */
1127 pkt_div = mcde_dsi_get_pkt_div(mode->hdisplay, 640);
1128 }
1129 dev_dbg(mcde->dev, "FIFO watermark after flooring: %d bytes\n",
1130 fifo_wtrmrk);
1131 dev_dbg(mcde->dev, "Packet divisor: %d bytes\n", pkt_div);
1132
1133 /* NOTE: pkt_div is 1 for video mode */
1134 pkt_size = (formatter_ppl * formatter_cpp) / pkt_div;
1135 /* Commands CMD8 need one extra byte */
1136 if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO))
1137 pkt_size++;
1138
1139 dev_dbg(mcde->dev, "DSI packet size: %d * %d bytes per line\n",
1140 pkt_size, pkt_div);
1141 dev_dbg(mcde->dev, "Overlay frame size: %u bytes\n",
1142 mode->hdisplay * mode->vdisplay * cpp);
1143 /* NOTE: pkt_div is 1 for video mode */
1144 formatter_frame = pkt_size * pkt_div * formatter_lpf;
1145 dev_dbg(mcde->dev, "Formatter frame size: %u bytes\n", formatter_frame);
1146
1147 *fifo_wtrmrk_lvl = fifo_wtrmrk;
1148 *dsi_pkt_size = pkt_size;
1149 *dsi_formatter_frame = formatter_frame;
1150}
1151
1152static void mcde_display_enable(struct drm_simple_display_pipe *pipe,
1153 struct drm_crtc_state *cstate,
1154 struct drm_plane_state *plane_state)
1155{
1156 struct drm_crtc *crtc = &pipe->crtc;
1157 struct drm_plane *plane = &pipe->plane;
1158 struct drm_device *drm = crtc->dev;
1159 struct mcde *mcde = to_mcde(drm);
1160 const struct drm_display_mode *mode = &cstate->mode;
1161 struct drm_framebuffer *fb = plane->state->fb;
1162 u32 format = fb->format->format;
1163 int dsi_pkt_size;
1164 int fifo_wtrmrk;
1165 int cpp = fb->format->cpp[0];
1166 u32 dsi_formatter_frame;
1167 u32 val;
1168 int ret;
1169
1170 /* This powers up the entire MCDE block and the DSI hardware */
1171 ret = regulator_enable(mcde->epod);
1172 if (ret) {
1173 dev_err(drm->dev, "can't re-enable EPOD regulator\n");
1174 return;
1175 }
1176
1177 dev_info(drm->dev, "enable MCDE, %d x %d format %p4cc\n",
1178 mode->hdisplay, mode->vdisplay, &format);
1179
1180
1181 /* Clear any pending interrupts */
1182 mcde_display_disable_irqs(mcde);
1183 writel(0, mcde->regs + MCDE_IMSCERR);
1184 writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
1185
1186 if (mcde->dpi_output)
1187 mcde_setup_dpi(mcde, mode, &fifo_wtrmrk);
1188 else
1189 mcde_setup_dsi(mcde, mode, cpp, &fifo_wtrmrk,
1190 &dsi_formatter_frame, &dsi_pkt_size);
1191
1192 mcde->stride = mode->hdisplay * cpp;
1193 dev_dbg(drm->dev, "Overlay line stride: %u bytes\n",
1194 mcde->stride);
1195
1196 /* Drain the FIFO A + channel 0 pipe so we have a clean slate */
1197 mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0);
1198
1199 /*
1200 * We set up our display pipeline:
1201 * EXTSRC 0 -> OVERLAY 0 -> CHANNEL 0 -> FIFO A -> DSI FORMATTER 0
1202 *
1203 * First configure the external source (memory) on external source 0
1204 * using the desired bitstream/bitmap format
1205 */
1206 mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format);
1207
1208 /*
1209 * Configure overlay 0 according to format and mode and take input
1210 * from external source 0 and route the output of this overlay to
1211 * channel 0
1212 */
1213 mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0,
1214 MCDE_CHANNEL_0, mode, format, cpp);
1215
1216 /*
1217 * Configure pixel-per-line and line-per-frame for channel 0 and then
1218 * route channel 0 to FIFO A
1219 */
1220 mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode);
1221
1222 if (mcde->dpi_output) {
1223 unsigned long lcd_freq;
1224
1225 /* Configure FIFO A to use DPI formatter 0 */
1226 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DPI_FORMATTER_0,
1227 fifo_wtrmrk);
1228
1229 /* Set up and enable the LCD clock */
1230 lcd_freq = clk_round_rate(mcde->fifoa_clk, mode->clock * 1000);
1231 ret = clk_set_rate(mcde->fifoa_clk, lcd_freq);
1232 if (ret)
1233 dev_err(mcde->dev, "failed to set LCD clock rate %lu Hz\n",
1234 lcd_freq);
1235 ret = clk_prepare_enable(mcde->fifoa_clk);
1236 if (ret) {
1237 dev_err(mcde->dev, "failed to enable FIFO A DPI clock\n");
1238 return;
1239 }
1240 dev_info(mcde->dev, "LCD FIFO A clk rate %lu Hz\n",
1241 clk_get_rate(mcde->fifoa_clk));
1242 } else {
1243 /* Configure FIFO A to use DSI formatter 0 */
1244 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0,
1245 fifo_wtrmrk);
1246
1247 /*
1248 * This brings up the DSI bridge which is tightly connected
1249 * to the MCDE DSI formatter.
1250 */
1251 mcde_dsi_enable(mcde->bridge);
1252
1253 /* Configure the DSI formatter 0 for the DSI panel output */
1254 mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0,
1255 dsi_formatter_frame, dsi_pkt_size);
1256 }
1257
1258 switch (mcde->flow_mode) {
1259 case MCDE_COMMAND_TE_FLOW:
1260 case MCDE_COMMAND_BTA_TE_FLOW:
1261 case MCDE_VIDEO_TE_FLOW:
1262 /* We are using TE in some combination */
1263 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1264 val = MCDE_VSCRC_VSPOL;
1265 else
1266 val = 0;
1267 writel(val, mcde->regs + MCDE_VSCRC0);
1268 /* Enable VSYNC capture on TE0 */
1269 val = readl(mcde->regs + MCDE_CRC);
1270 val |= MCDE_CRC_SYCEN0;
1271 writel(val, mcde->regs + MCDE_CRC);
1272 break;
1273 default:
1274 /* No TE capture */
1275 break;
1276 }
1277
1278 drm_crtc_vblank_on(crtc);
1279
1280 /*
1281 * If we're using oneshot mode we don't start the flow
1282 * until each time the display is given an update, and
1283 * then we disable it immediately after. For all other
1284 * modes (command or video) we start the FIFO flow
1285 * right here. This is necessary for the hardware to
1286 * behave right.
1287 */
1288 if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) {
1289 mcde_enable_fifo(mcde, MCDE_FIFO_A);
1290 dev_dbg(mcde->dev, "started MCDE video FIFO flow\n");
1291 }
1292
1293 /* Enable MCDE with automatic clock gating */
1294 val = readl(mcde->regs + MCDE_CR);
1295 val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN;
1296 writel(val, mcde->regs + MCDE_CR);
1297
1298 dev_info(drm->dev, "MCDE display is enabled\n");
1299}
1300
1301static void mcde_display_disable(struct drm_simple_display_pipe *pipe)
1302{
1303 struct drm_crtc *crtc = &pipe->crtc;
1304 struct drm_device *drm = crtc->dev;
1305 struct mcde *mcde = to_mcde(drm);
1306 struct drm_pending_vblank_event *event;
1307 int ret;
1308
1309 drm_crtc_vblank_off(crtc);
1310
1311 /* Disable FIFO A flow */
1312 mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
1313
1314 if (mcde->dpi_output) {
1315 clk_disable_unprepare(mcde->fifoa_clk);
1316 } else {
1317 /* This disables the DSI bridge */
1318 mcde_dsi_disable(mcde->bridge);
1319 }
1320
1321 event = crtc->state->event;
1322 if (event) {
1323 crtc->state->event = NULL;
1324
1325 spin_lock_irq(&crtc->dev->event_lock);
1326 drm_crtc_send_vblank_event(crtc, event);
1327 spin_unlock_irq(&crtc->dev->event_lock);
1328 }
1329
1330 ret = regulator_disable(mcde->epod);
1331 if (ret)
1332 dev_err(drm->dev, "can't disable EPOD regulator\n");
1333 /* Make sure we are powered down (before we may power up again) */
1334 usleep_range(50000, 70000);
1335
1336 dev_info(drm->dev, "MCDE display is disabled\n");
1337}
1338
1339static void mcde_start_flow(struct mcde *mcde)
1340{
1341 /* Request a TE ACK only in TE+BTA mode */
1342 if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW)
1343 mcde_dsi_te_request(mcde->mdsi);
1344
1345 /* Enable FIFO A flow */
1346 mcde_enable_fifo(mcde, MCDE_FIFO_A);
1347
1348 /*
1349 * If oneshot mode is enabled, the flow will be disabled
1350 * when the TE0 IRQ arrives in the interrupt handler. Otherwise
1351 * updates are continuously streamed to the display after this
1352 * point.
1353 */
1354
1355 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
1356 /* Trigger a software sync out on channel 0 */
1357 writel(MCDE_CHNLXSYNCHSW_SW_TRIG,
1358 mcde->regs + MCDE_CHNL0SYNCHSW);
1359
1360 /*
1361 * Disable FIFO A flow again: since we are using TE sync we
1362 * need to wait for the FIFO to drain before we continue
1363 * so repeated calls to this function will not cause a mess
1364 * in the hardware by pushing updates will updates are going
1365 * on already.
1366 */
1367 mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
1368 }
1369
1370 dev_dbg(mcde->dev, "started MCDE FIFO flow\n");
1371}
1372
1373static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address)
1374{
1375 /* Write bitmap base address to register */
1376 writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);
1377 /*
1378 * Base address for next line this is probably only used
1379 * in interlace modes.
1380 */
1381 writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);
1382}
1383
1384static void mcde_display_update(struct drm_simple_display_pipe *pipe,
1385 struct drm_plane_state *old_pstate)
1386{
1387 struct drm_crtc *crtc = &pipe->crtc;
1388 struct drm_device *drm = crtc->dev;
1389 struct mcde *mcde = to_mcde(drm);
1390 struct drm_pending_vblank_event *event = crtc->state->event;
1391 struct drm_plane *plane = &pipe->plane;
1392 struct drm_plane_state *pstate = plane->state;
1393 struct drm_framebuffer *fb = pstate->fb;
1394
1395 /*
1396 * Handle any pending event first, we need to arm the vblank
1397 * interrupt before sending any update to the display so we don't
1398 * miss the interrupt.
1399 */
1400 if (event) {
1401 crtc->state->event = NULL;
1402
1403 spin_lock_irq(&crtc->dev->event_lock);
1404 /*
1405 * Hardware must be on before we can arm any vblank event,
1406 * this is not a scanout controller where there is always
1407 * some periodic update going on, it is completely frozen
1408 * until we get an update. If MCDE output isn't yet enabled,
1409 * we just send a vblank dummy event back.
1410 */
1411 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) {
1412 dev_dbg(mcde->dev, "arm vblank event\n");
1413 drm_crtc_arm_vblank_event(crtc, event);
1414 } else {
1415 dev_dbg(mcde->dev, "insert fake vblank event\n");
1416 drm_crtc_send_vblank_event(crtc, event);
1417 }
1418
1419 spin_unlock_irq(&crtc->dev->event_lock);
1420 }
1421
1422 /*
1423 * We do not start sending framebuffer updates before the
1424 * display is enabled. Update events will however be dispatched
1425 * from the DRM core before the display is enabled.
1426 */
1427 if (fb) {
1428 mcde_set_extsrc(mcde, drm_fb_dma_get_gem_addr(fb, pstate, 0));
1429 dev_info_once(mcde->dev, "first update of display contents\n");
1430 /*
1431 * Usually the flow is already active, unless we are in
1432 * oneshot mode, then we need to kick the flow right here.
1433 */
1434 if (mcde->flow_active == 0)
1435 mcde_start_flow(mcde);
1436 } else {
1437 /*
1438 * If an update is receieved before the MCDE is enabled
1439 * (before mcde_display_enable() is called) we can't really
1440 * do much with that buffer.
1441 */
1442 dev_info(mcde->dev, "ignored a display update\n");
1443 }
1444}
1445
1446static int mcde_display_enable_vblank(struct drm_simple_display_pipe *pipe)
1447{
1448 struct drm_crtc *crtc = &pipe->crtc;
1449 struct drm_device *drm = crtc->dev;
1450 struct mcde *mcde = to_mcde(drm);
1451 u32 val;
1452
1453 /* Enable all VBLANK IRQs */
1454 val = MCDE_PP_VCMPA |
1455 MCDE_PP_VCMPB |
1456 MCDE_PP_VSCC0 |
1457 MCDE_PP_VSCC1 |
1458 MCDE_PP_VCMPC0 |
1459 MCDE_PP_VCMPC1;
1460 writel(val, mcde->regs + MCDE_IMSCPP);
1461
1462 return 0;
1463}
1464
1465static void mcde_display_disable_vblank(struct drm_simple_display_pipe *pipe)
1466{
1467 struct drm_crtc *crtc = &pipe->crtc;
1468 struct drm_device *drm = crtc->dev;
1469 struct mcde *mcde = to_mcde(drm);
1470
1471 /* Disable all VBLANK IRQs */
1472 writel(0, mcde->regs + MCDE_IMSCPP);
1473 /* Clear any pending IRQs */
1474 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
1475}
1476
1477static struct drm_simple_display_pipe_funcs mcde_display_funcs = {
1478 .check = mcde_display_check,
1479 .enable = mcde_display_enable,
1480 .disable = mcde_display_disable,
1481 .update = mcde_display_update,
1482 .enable_vblank = mcde_display_enable_vblank,
1483 .disable_vblank = mcde_display_disable_vblank,
1484};
1485
1486int mcde_display_init(struct drm_device *drm)
1487{
1488 struct mcde *mcde = to_mcde(drm);
1489 int ret;
1490 static const u32 formats[] = {
1491 DRM_FORMAT_ARGB8888,
1492 DRM_FORMAT_ABGR8888,
1493 DRM_FORMAT_XRGB8888,
1494 DRM_FORMAT_XBGR8888,
1495 DRM_FORMAT_RGB888,
1496 DRM_FORMAT_BGR888,
1497 DRM_FORMAT_ARGB4444,
1498 DRM_FORMAT_ABGR4444,
1499 DRM_FORMAT_XRGB4444,
1500 DRM_FORMAT_XBGR4444,
1501 /* These are actually IRGB1555 so intensity bit is lost */
1502 DRM_FORMAT_XRGB1555,
1503 DRM_FORMAT_XBGR1555,
1504 DRM_FORMAT_RGB565,
1505 DRM_FORMAT_BGR565,
1506 DRM_FORMAT_YUV422,
1507 };
1508
1509 ret = mcde_init_clock_divider(mcde);
1510 if (ret)
1511 return ret;
1512
1513 ret = drm_simple_display_pipe_init(drm, &mcde->pipe,
1514 &mcde_display_funcs,
1515 formats, ARRAY_SIZE(formats),
1516 NULL,
1517 mcde->connector);
1518 if (ret)
1519 return ret;
1520
1521 return 0;
1522}
1523EXPORT_SYMBOL_GPL(mcde_display_init);