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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <[email protected]>
5 */
6
7#ifndef __MSM_GPU_H__
8#define __MSM_GPU_H__
9
10#include <linux/adreno-smmu-priv.h>
11#include <linux/clk.h>
12#include <linux/devfreq.h>
13#include <linux/interconnect.h>
14#include <linux/pm_opp.h>
15#include <linux/regulator/consumer.h>
16
17#include "msm_drv.h"
18#include "msm_fence.h"
19#include "msm_gpu_trace.h"
20#include "msm_ringbuffer.h"
21#include "msm_gem.h"
22
23struct msm_gem_submit;
24struct msm_gem_vm_log_entry;
25struct msm_gpu_state;
26struct msm_context;
27struct msm_perfcntr_group;
28struct msm_perfcntr_stream;
29
30struct msm_gpu_config {
31 const char *ioname;
32 unsigned int nr_rings;
33};
34
35/* So far, with hardware that I've seen to date, we can have:
36 * + zero, one, or two z180 2d cores
37 * + a3xx or a2xx 3d core, which share a common CP (the firmware
38 * for the CP seems to implement some different PM4 packet types
39 * but the basics of cmdstream submission are the same)
40 *
41 * Which means that the eventual complete "class" hierarchy, once
42 * support for all past and present hw is in place, becomes:
43 * + msm_gpu
44 * + adreno_gpu
45 * + a3xx_gpu
46 * + a2xx_gpu
47 * + z180_gpu
48 */
49struct msm_gpu_funcs {
50 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
51 uint32_t param, uint64_t *value, uint32_t *len);
52 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
53 uint32_t param, uint64_t value, uint32_t len);
54 int (*hw_init)(struct msm_gpu *gpu);
55
56 /**
57 * @ucode_load: Optional hook to upload fw to GEM objs
58 */
59 int (*ucode_load)(struct msm_gpu *gpu);
60
61 int (*pm_suspend)(struct msm_gpu *gpu);
62 int (*pm_resume)(struct msm_gpu *gpu);
63 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
64 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
65 irqreturn_t (*irq)(struct msm_gpu *irq);
66 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
67 void (*recover)(struct msm_gpu *gpu);
68 void (*destroy)(struct msm_gpu *gpu);
69#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
70 /* show GPU status in debugfs: */
71 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
72 struct drm_printer *p);
73 /* for generation specific debugfs: */
74 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
75#endif
76 /* note: gpu_busy() can assume that we have been pm_resumed */
77 u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
78 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
79 int (*gpu_state_put)(struct msm_gpu_state *state);
80 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
81 /* note: gpu_set_freq() can assume that we have been pm_resumed */
82 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
83 bool suspended);
84 struct drm_gpuvm *(*create_vm)(struct msm_gpu *gpu, struct platform_device *pdev);
85 struct drm_gpuvm *(*create_private_vm)(struct msm_gpu *gpu, bool kernel_managed);
86 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
87
88 /**
89 * progress: Has the GPU made progress?
90 *
91 * Return true if GPU position in cmdstream has advanced (or changed)
92 * since the last call. To avoid false negatives, this should account
93 * for cmdstream that is buffered in this FIFO upstream of the CP fw.
94 */
95 bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
96 void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on);
97
98 /* Configure perfcntr SELect regs: */
99 void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
100 const struct msm_perfcntr_stream *stream);
101
102 /* Flush perfcntrs before reading (optional): */
103 void (*perfcntr_flush)(struct msm_gpu *gpu);
104};
105
106/* Additional state for iommu faults: */
107struct msm_gpu_fault_info {
108 u64 ttbr0;
109 unsigned long iova;
110 int flags;
111 const char *type;
112 const char *block;
113
114 /* Information about what we think/expect is the current SMMU state,
115 * for example expected_ttbr0 should match smmu_info.ttbr0 which
116 * was read back from SMMU registers.
117 */
118 phys_addr_t pgtbl_ttbr0;
119 u64 ptes[4];
120 int asid;
121};
122
123/**
124 * struct msm_gpu_devfreq - devfreq related state
125 */
126struct msm_gpu_devfreq {
127 /** @devfreq: devfreq instance */
128 struct devfreq *devfreq;
129 /** @lock: lock for "suspended", "busy_cycles", and "time" */
130 struct mutex lock;
131 /**
132 * @idle_freq:
133 * Shadow frequency used while the GPU is idle. From the PoV of
134 * the devfreq governor, we are continuing to sample busyness and
135 * adjust frequency while the GPU is idle, but we use this shadow
136 * value as the GPU is actually clamped to minimum frequency while
137 * it is inactive.
138 */
139 unsigned long idle_freq;
140 /**
141 * @boost_freq:
142 * A PM QoS constraint to boost min freq for a period of time
143 * until the boost expires.
144 */
145 struct dev_pm_qos_request boost_freq;
146 /**
147 * @busy_cycles: Last busy counter value, for calculating elapsed busy
148 * cycles since last sampling period.
149 */
150 u64 busy_cycles;
151 /** @time: Time of last sampling period. */
152 ktime_t time;
153 /** @idle_time: Time of last transition to idle. */
154 ktime_t idle_time;
155 /**
156 * @idle_work:
157 * Used to delay clamping to idle freq on active->idle transition.
158 */
159 struct msm_hrtimer_work idle_work;
160 /**
161 * @boost_work:
162 * Used to reset the boost_constraint after the boost period has
163 * elapsed
164 */
165 struct msm_hrtimer_work boost_work;
166
167 /** @suspended: tracks if we're suspended */
168 bool suspended;
169};
170
171struct msm_gpu {
172 const char *name;
173 struct drm_device *dev;
174 struct platform_device *pdev;
175 const struct msm_gpu_funcs *funcs;
176
177 struct adreno_smmu_priv adreno_smmu;
178
179 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
180 int nr_rings;
181
182 /**
183 * sysprof_active:
184 *
185 * The count of contexts that have enabled system profiling.
186 */
187 refcount_t sysprof_active;
188
189 /**
190 * lock:
191 *
192 * General lock for serializing all the gpu things.
193 *
194 * TODO move to per-ring locking where feasible (ie. submit/retire
195 * path, etc)
196 */
197 struct mutex lock;
198
199 /**
200 * active_submits:
201 *
202 * The number of submitted but not yet retired submits, used to
203 * determine transitions between active and idle.
204 *
205 * Protected by active_lock
206 */
207 int active_submits;
208
209 /** lock: protects active_submits and idle/active transitions */
210 struct mutex active_lock;
211
212 /* does gpu need hw_init? */
213 bool needs_hw_init;
214
215 /**
216 * global_faults: number of GPU hangs not attributed to a particular
217 * address space
218 */
219 int global_faults;
220
221 void __iomem *mmio;
222 int irq;
223
224 struct drm_gpuvm *vm;
225
226 /* Power Control: */
227 struct regulator *gpu_reg, *gpu_cx;
228 struct clk_bulk_data *grp_clks;
229 int nr_clocks;
230 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
231 uint32_t fast_rate;
232
233 /* Hang and Inactivity Detection:
234 */
235#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
236
237#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
238#define DRM_MSM_HANGCHECK_PROGRESS_RETRIES 3
239 struct timer_list hangcheck_timer;
240
241 /* work for handling GPU recovery: */
242 struct kthread_work recover_work;
243
244 /** retire_event: notified when submits are retired: */
245 wait_queue_head_t retire_event;
246
247 /* work for handling active-list retiring: */
248 struct kthread_work retire_work;
249
250 /* worker for retire/recover: */
251 struct kthread_worker *worker;
252
253 struct drm_gem_object *memptrs_bo;
254
255 struct msm_gpu_devfreq devfreq;
256
257 uint32_t suspend_count;
258
259 struct msm_gpu_state *crashstate;
260
261 /* True if the hardware supports expanded apriv (a650 and newer) */
262 bool hw_apriv;
263
264 /**
265 * @allow_relocs: allow relocs in SUBMIT ioctl
266 *
267 * Mesa won't use relocs for driver version 1.4.0 and later. This
268 * switch-over happened early enough in mesa a6xx bringup that we
269 * can disallow relocs for a6xx and newer.
270 */
271 bool allow_relocs;
272
273 struct thermal_cooling_device *cooling;
274
275 const struct msm_perfcntr_group *perfcntr_groups;
276 unsigned num_perfcntr_groups;
277
278 struct msm_perfcntr_state *perfcntrs;
279
280 /** @perfcntr_lock: protects perfcntr related state */
281 struct mutex perfcntr_lock;
282};
283
284static inline struct msm_gpu *dev_to_gpu(struct device *dev)
285{
286 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
287
288 if (!adreno_smmu)
289 return NULL;
290
291 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
292}
293
294static inline bool
295adreno_smmu_has_prr(struct msm_gpu *gpu)
296{
297 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
298
299 if (!adreno_smmu)
300 return false;
301
302 return adreno_smmu && adreno_smmu->set_prr_addr;
303}
304
305/* It turns out that all targets use the same ringbuffer size */
306#define MSM_GPU_RINGBUFFER_SZ SZ_32K
307#define MSM_GPU_RINGBUFFER_BLKSIZE 32
308
309#define MSM_GPU_RB_CNTL_DEFAULT \
310 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
311 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
312
313static inline bool msm_gpu_active(struct msm_gpu *gpu)
314{
315 int i;
316
317 for (i = 0; i < gpu->nr_rings; i++) {
318 struct msm_ringbuffer *ring = gpu->rb[i];
319
320 if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))
321 return true;
322 }
323
324 return false;
325}
326
327/**
328 * struct msm_perfcntr_group_state - Tracking for the currently allocated counter state
329 */
330struct msm_perfcntr_group_state {
331 /**
332 * @allocated_counters:
333 *
334 * allocated counters for global counter collection. The
335 * corresponding counters are allocated from highest to
336 * lowest, to minimize chance of conflict with old userspace
337 * allocating from lowest to highest.
338 */
339 unsigned allocated_counters;
340
341 /**
342 * @countables:
343 *
344 * The corresponding SELect reg values for the allocated counters
345 */
346 uint32_t countables[];
347};
348
349/**
350 * struct msm_perfcntr_state - overall global perfcntr state
351 */
352struct msm_perfcntr_state {
353 /** @stream: current global counter stream if active */
354 struct msm_perfcntr_stream *stream;
355
356 /** @sel_seqno: counter for sel_fence */
357 uint32_t sel_seqno;
358
359 /**
360 * @groups: Global perfcntr stream group state.
361 *
362 * Conceptually this is part of msm_perfcntr_stream state, but is
363 * statically pre-allocated when the gpu is initialized to simplify
364 * error path cleanup in PERFCNTR_CONFIG ioctl. (__free(kfree)
365 * doesn't really help with variable length arrays of allocated
366 * pointers.)
367 */
368 struct msm_perfcntr_group_state *groups[];
369};
370
371static inline bool
372msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu)
373{
374 return (refcount_read(&gpu->sysprof_active) > 1) ||
375 (gpu->perfcntrs && READ_ONCE(gpu->perfcntrs->stream));
376}
377
378static inline bool
379msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu)
380{
381 return refcount_read(&gpu->sysprof_active) > 1;
382}
383
384/*
385 * The number of priority levels provided by drm gpu scheduler. The
386 * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some
387 * cases, so we don't use it (no need for kernel generated jobs).
388 */
389#define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_LOW - DRM_SCHED_PRIORITY_HIGH)
390
391/**
392 * struct msm_context - per-drm_file context
393 */
394struct msm_context {
395 /** @ctxlock: synchronizes access to submitqueues list, etc */
396 struct rw_semaphore ctxlock;
397 /** @submitqueues: list of &msm_gpu_submitqueue created by userspace */
398 struct list_head submitqueues;
399 /**
400 * @queueid:
401 * Counter incremented each time a submitqueue is created, used to
402 * assign &msm_gpu_submitqueue.id
403 */
404 int queueid;
405 /**
406 * @closed: The device file associated with this context has been closed.
407 * Once the device is closed, any submits that have not been written
408 * to the ring buffer are no-op'd.
409 */
410 bool closed;
411 /**
412 * @userspace_managed_vm:
413 * Has userspace opted-in to userspace managed VM (ie. VM_BIND) via
414 * MSM_PARAM_EN_VM_BIND?
415 */
416 bool userspace_managed_vm;
417 /**
418 * @vm:
419 * The per-process GPU address-space. Do not access directly, use
420 * msm_context_vm().
421 */
422 struct drm_gpuvm *vm;
423 /** @ref: the reference count */
424 struct kref ref;
425 /**
426 * @seqno:
427 * A unique per-process sequence number. Used to detect context
428 * switches, without relying on keeping a, potentially dangling,
429 * pointer to the previous context.
430 */
431 int seqno;
432 /**
433 * @sysprof:
434 * The value of MSM_PARAM_SYSPROF set by userspace. This is
435 * intended to be used by system profiling tools like Mesa's
436 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
437 *
438 * Setting a value of 1 will preserve performance counters across
439 * context switches. Setting a value of 2 will in addition
440 * suppress suspend. (Performance counters lose state across
441 * power collapse, which is undesirable for profiling in some
442 * cases.)
443 *
444 * The value automatically reverts to zero when the drm device
445 * file is closed.
446 */
447 int sysprof;
448 /**
449 * @comm: Overridden task comm, see MSM_PARAM_COMM
450 *
451 * Accessed under msm_gpu::lock
452 */
453 char *comm;
454 /**
455 * @cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE
456 *
457 * Accessed under msm_gpu::lock
458 */
459 char *cmdline;
460 /**
461 * @elapsed_ns:
462 * The total (cumulative) elapsed time GPU was busy with rendering
463 * from this context in ns.
464 */
465 uint64_t elapsed_ns;
466 /**
467 * @cycles:
468 * The total (cumulative) GPU cycles elapsed attributed to this
469 * context.
470 */
471 uint64_t cycles;
472 /**
473 * @entities:
474 * Table of per-priority-level sched entities used by submitqueues
475 * associated with this &drm_file. Because some userspace apps
476 * make assumptions about rendering from multiple gl contexts
477 * (of the same priority) within the process happening in FIFO
478 * order without requiring any fencing beyond MakeCurrent(), we
479 * create at most one &drm_sched_entity per-process per-priority-
480 * level.
481 */
482 struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS];
483 /**
484 * @ctx_mem:
485 * Total amount of memory of GEM buffers with handles attached for
486 * this context.
487 */
488 atomic64_t ctx_mem;
489
490 /**
491 * @perfcntrs: Per-context reserved perfcntrs state
492 */
493 struct msm_perfcntr_context_state *perfctx;
494};
495
496struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx);
497
498/**
499 * msm_context_is_vmbind() - has userspace opted in to VM_BIND?
500 *
501 * @ctx: the drm_file context
502 *
503 * See MSM_PARAM_EN_VM_BIND. If userspace is managing the VM, it can
504 * do sparse binding including having multiple, potentially partial,
505 * mappings in the VM. Therefore certain legacy uabi (ie. GET_IOVA,
506 * SET_IOVA) are rejected because they don't have a sensible meaning.
507 *
508 * Returns: %true if userspace is managing the VM, %false otherwise.
509 */
510static inline bool
511msm_context_is_vmbind(struct msm_context *ctx)
512{
513 return ctx->userspace_managed_vm;
514}
515
516/**
517 * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
518 *
519 * @gpu: the gpu instance
520 * @prio: the userspace priority level
521 * @ring_nr: [out] the ringbuffer the userspace priority maps to
522 * @sched_prio: [out] the gpu scheduler priority level which the userspace
523 * priority maps to
524 *
525 * With drm/scheduler providing it's own level of prioritization, our total
526 * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES).
527 * Each ring is associated with it's own scheduler instance. However, our
528 * UABI is that lower numerical values are higher priority. So mapping the
529 * single userspace priority level into ring_nr and sched_prio takes some
530 * care. The userspace provided priority (when a submitqueue is created)
531 * is mapped to ring nr and scheduler priority as such:
532 *
533 * ring_nr = userspace_prio / NR_SCHED_PRIORITIES
534 * sched_prio = NR_SCHED_PRIORITIES -
535 * (userspace_prio % NR_SCHED_PRIORITIES) - 1
536 *
537 * This allows generations without preemption (nr_rings==1) to have some
538 * amount of prioritization, and provides more priority levels for gens
539 * that do have preemption.
540 *
541 * Returns: %0 on success, %-errno on error.
542 */
543static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,
544 unsigned *ring_nr, enum drm_sched_priority *sched_prio)
545{
546 unsigned rn, sp;
547
548 rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp);
549
550 /* invert sched priority to map to higher-numeric-is-higher-
551 * priority convention
552 */
553 sp = NR_SCHED_PRIORITIES - sp - 1;
554
555 if (rn >= gpu->nr_rings)
556 return -EINVAL;
557
558 *ring_nr = rn;
559 *sched_prio = sp;
560
561 return 0;
562}
563
564/**
565 * struct msm_gpu_submitqueue - Userspace created context.
566 *
567 * A submitqueue is associated with a gl context or vk queue (or equiv)
568 * in userspace.
569 *
570 * @id: userspace id for the submitqueue, unique within the drm_file
571 * @flags: userspace flags for the submitqueue, specified at creation
572 * (currently unusued)
573 * @ring_nr: the ringbuffer used by this submitqueue, which is determined
574 * by the submitqueue's priority
575 * @faults: the number of GPU hangs associated with this submitqueue
576 * @last_fence: the sequence number of the last allocated fence (for error
577 * checking)
578 * @ctx: the per-drm_file context associated with the submitqueue (ie.
579 * which set of pgtables do submits jobs associated with the
580 * submitqueue use)
581 * @node: node in the context's list of submitqueues
582 * @fence_idr: maps fence-id to dma_fence for userspace visible fence
583 * seqno, protected by submitqueue lock
584 * @idr_lock: for serializing access to fence_idr
585 * @lock: submitqueue lock for serializing submits on a queue
586 * @ref: reference count
587 * @entity: the submit job-queue
588 */
589struct msm_gpu_submitqueue {
590 int id;
591 u32 flags;
592 u32 ring_nr;
593 int faults;
594 uint32_t last_fence;
595 struct msm_context *ctx;
596 struct list_head node;
597 struct idr fence_idr;
598 struct spinlock idr_lock;
599 struct mutex lock;
600 struct kref ref;
601 struct drm_sched_entity *entity;
602
603 /** @_vm_bind_entity: used for @entity pointer for VM_BIND queues */
604 struct drm_sched_entity _vm_bind_entity[0];
605};
606
607struct msm_gpu_state_bo {
608 u64 iova;
609 size_t size;
610 u32 flags;
611 void *data;
612 bool encoded;
613 char name[32];
614};
615
616struct msm_gpu_state {
617 struct kref ref;
618 struct timespec64 time;
619
620 struct {
621 u64 iova;
622 u32 fence;
623 u32 seqno;
624 u32 rptr;
625 u32 wptr;
626 void *data;
627 int data_size;
628 bool encoded;
629 } ring[MSM_GPU_MAX_RINGS];
630
631 int nr_registers;
632 u32 *registers;
633
634 u32 rbbm_status;
635
636 char *comm;
637 char *cmd;
638
639 struct msm_gpu_fault_info fault_info;
640
641 int nr_vm_logs;
642 struct msm_gem_vm_log_entry *vm_logs;
643
644 int nr_bos;
645 struct msm_gpu_state_bo *bos;
646};
647
648static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
649{
650 trace_msm_gpu_regaccess(reg);
651 writel(data, gpu->mmio + (reg << 2));
652}
653
654static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
655{
656 trace_msm_gpu_regaccess(reg);
657 return readl(gpu->mmio + (reg << 2));
658}
659
660static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
661{
662 trace_msm_gpu_regaccess(reg);
663 msm_rmw(gpu->mmio + (reg << 2), mask, or);
664}
665
666static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
667{
668 u64 val;
669
670 /*
671 * Why not a readq here? Two reasons: 1) many of the LO registers are
672 * not quad word aligned and 2) the GPU hardware designers have a bit
673 * of a history of putting registers where they fit, especially in
674 * spins. The longer a GPU family goes the higher the chance that
675 * we'll get burned. We could do a series of validity checks if we
676 * wanted to, but really is a readq() that much better? Nah.
677 */
678
679 /*
680 * For some lo/hi registers (like perfcounters), the hi value is latched
681 * when the lo is read, so make sure to read the lo first to trigger
682 * that
683 */
684 trace_msm_gpu_regaccess(reg);
685 val = (u64) readl(gpu->mmio + (reg << 2));
686 trace_msm_gpu_regaccess(reg+1);
687 val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);
688
689 return val;
690}
691
692static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
693{
694 trace_msm_gpu_regaccess(reg);
695 /* Why not a writeq here? Read the screed above */
696 writel(lower_32_bits(val), gpu->mmio + (reg << 2));
697 trace_msm_gpu_regaccess(reg+1);
698 writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
699}
700
701int msm_gpu_pm_suspend(struct msm_gpu *gpu);
702int msm_gpu_pm_resume(struct msm_gpu *gpu);
703
704void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx,
705 struct drm_printer *p);
706
707int msm_submitqueue_init(struct drm_device *drm, struct msm_context *ctx);
708struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_context *ctx,
709 u32 id);
710int msm_submitqueue_create(struct drm_device *drm,
711 struct msm_context *ctx,
712 u32 prio, u32 flags, u32 *id);
713int msm_submitqueue_query(struct drm_device *drm, struct msm_context *ctx,
714 struct drm_msm_submitqueue_query *args);
715int msm_submitqueue_remove(struct msm_context *ctx, u32 id);
716void msm_submitqueue_close(struct msm_context *ctx);
717
718void msm_submitqueue_destroy(struct kref *kref);
719
720int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sysprof);
721void __msm_context_destroy(struct kref *kref);
722
723static inline void msm_context_put(struct msm_context *ctx)
724{
725 kref_put(&ctx->ref, __msm_context_destroy);
726}
727
728static inline struct msm_context *msm_context_get(
729 struct msm_context *ctx)
730{
731 kref_get(&ctx->ref);
732 return ctx;
733}
734
735void msm_devfreq_init(struct msm_gpu *gpu);
736void msm_devfreq_cleanup(struct msm_gpu *gpu);
737void msm_devfreq_resume(struct msm_gpu *gpu);
738void msm_devfreq_suspend(struct msm_gpu *gpu);
739void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
740void msm_devfreq_active(struct msm_gpu *gpu);
741void msm_devfreq_idle(struct msm_gpu *gpu);
742
743int msm_gpu_hw_init(struct msm_gpu *gpu);
744
745void msm_gpu_retire(struct msm_gpu *gpu);
746void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
747
748int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
749 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
750 const char *name, struct msm_gpu_config *config);
751
752struct drm_gpuvm *
753msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task,
754 bool kernel_managed);
755
756void msm_gpu_cleanup(struct msm_gpu *gpu);
757
758struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
759bool adreno_has_gpu(struct device_node *node);
760void __init adreno_register(void);
761void __exit adreno_unregister(void);
762
763static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
764{
765 if (queue)
766 kref_put(&queue->ref, msm_submitqueue_destroy);
767}
768
769static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
770{
771 struct msm_gpu_state *state = NULL;
772
773 mutex_lock(&gpu->lock);
774
775 if (gpu->crashstate) {
776 kref_get(&gpu->crashstate->ref);
777 state = gpu->crashstate;
778 }
779
780 mutex_unlock(&gpu->lock);
781
782 return state;
783}
784
785static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
786{
787 mutex_lock(&gpu->lock);
788
789 if (gpu->crashstate) {
790 if (gpu->funcs->gpu_state_put(gpu->crashstate))
791 gpu->crashstate = NULL;
792 }
793
794 mutex_unlock(&gpu->lock);
795}
796
797void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info);
798
799/*
800 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
801 * support expanded privileges
802 */
803#define check_apriv(gpu, flags) \
804 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
805
806
807#endif /* __MSM_GPU_H__ */