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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/aperture.h>
8#include <linux/bitops.h>
9#include <linux/host1x.h>
10#include <linux/idr.h>
11#include <linux/iommu.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15
16#include <drm/clients/drm_client_setup.h>
17#include <drm/drm_atomic.h>
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_debugfs.h>
20#include <drm/drm_drv.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_framebuffer.h>
23#include <drm/drm_ioctl.h>
24#include <drm/drm_prime.h>
25#include <drm/drm_print.h>
26#include <drm/drm_vblank.h>
27
28#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
29#include <asm/dma-iommu.h>
30#endif
31
32#include "dc.h"
33#include "drm.h"
34#include "gem.h"
35#include "uapi.h"
36
37#define DRIVER_NAME "tegra"
38#define DRIVER_DESC "NVIDIA Tegra graphics"
39#define DRIVER_MAJOR 1
40#define DRIVER_MINOR 0
41#define DRIVER_PATCHLEVEL 0
42
43#define CARVEOUT_SZ SZ_64M
44#define CDMA_GATHER_FETCHES_MAX_NB 16383
45
46static int tegra_atomic_check(struct drm_device *drm,
47 struct drm_atomic_commit *state)
48{
49 int err;
50
51 err = drm_atomic_helper_check(drm, state);
52 if (err < 0)
53 return err;
54
55 return tegra_display_hub_atomic_check(drm, state);
56}
57
58static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
59 .fb_create = tegra_fb_create,
60 .atomic_check = tegra_atomic_check,
61 .atomic_commit = drm_atomic_helper_commit,
62};
63
64static void tegra_atomic_post_commit(struct drm_device *drm,
65 struct drm_atomic_commit *old_state)
66{
67 struct drm_crtc_state *old_crtc_state __maybe_unused;
68 struct drm_crtc *crtc;
69 unsigned int i;
70
71 for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
72 tegra_crtc_atomic_post_commit(crtc, old_state);
73}
74
75static void tegra_atomic_commit_tail(struct drm_atomic_commit *old_state)
76{
77 struct drm_device *drm = old_state->dev;
78 struct tegra_drm *tegra = drm->dev_private;
79
80 if (tegra->hub) {
81 bool fence_cookie = dma_fence_begin_signalling();
82
83 drm_atomic_helper_commit_modeset_disables(drm, old_state);
84 tegra_display_hub_atomic_commit(drm, old_state);
85 drm_atomic_helper_commit_planes(drm, old_state, 0);
86 drm_atomic_helper_commit_modeset_enables(drm, old_state);
87 drm_atomic_helper_commit_hw_done(old_state);
88 dma_fence_end_signalling(fence_cookie);
89 drm_atomic_helper_wait_for_vblanks(drm, old_state);
90 drm_atomic_helper_cleanup_planes(drm, old_state);
91 } else {
92 drm_atomic_helper_commit_tail_rpm(old_state);
93 }
94
95 tegra_atomic_post_commit(drm, old_state);
96}
97
98static const struct drm_mode_config_helper_funcs
99tegra_drm_mode_config_helpers = {
100 .atomic_commit_tail = tegra_atomic_commit_tail,
101};
102
103static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
104{
105 struct tegra_drm_file *fpriv;
106
107 fpriv = kzalloc_obj(*fpriv);
108 if (!fpriv)
109 return -ENOMEM;
110
111 idr_init_base(&fpriv->legacy_contexts, 1);
112 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
113 xa_init(&fpriv->syncpoints);
114 mutex_init(&fpriv->lock);
115 filp->driver_priv = fpriv;
116
117 return 0;
118}
119
120static void tegra_drm_context_free(struct tegra_drm_context *context)
121{
122 context->client->ops->close_channel(context);
123 pm_runtime_put(context->client->base.dev);
124 kfree(context);
125}
126
127static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
128 struct drm_tegra_reloc __user *src,
129 struct drm_device *drm,
130 struct drm_file *file)
131{
132 u32 cmdbuf, target;
133 int err;
134
135 err = get_user(cmdbuf, &src->cmdbuf.handle);
136 if (err < 0)
137 return err;
138
139 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
140 if (err < 0)
141 return err;
142
143 err = get_user(target, &src->target.handle);
144 if (err < 0)
145 return err;
146
147 err = get_user(dest->target.offset, &src->target.offset);
148 if (err < 0)
149 return err;
150
151 err = get_user(dest->shift, &src->shift);
152 if (err < 0)
153 return err;
154
155 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
156
157 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
158 if (!dest->cmdbuf.bo)
159 return -ENOENT;
160
161 dest->target.bo = tegra_gem_lookup(file, target);
162 if (!dest->target.bo)
163 return -ENOENT;
164
165 return 0;
166}
167
168int tegra_drm_submit(struct tegra_drm_context *context,
169 struct drm_tegra_submit *args, struct drm_device *drm,
170 struct drm_file *file)
171{
172 struct host1x_client *client = &context->client->base;
173 unsigned int num_cmdbufs = args->num_cmdbufs;
174 unsigned int num_relocs = args->num_relocs;
175 struct drm_tegra_cmdbuf __user *user_cmdbufs;
176 struct drm_tegra_reloc __user *user_relocs;
177 struct drm_tegra_syncpt __user *user_syncpt;
178 struct drm_tegra_syncpt syncpt;
179 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
180 struct drm_gem_object **refs;
181 struct host1x_syncpt *sp = NULL;
182 struct host1x_job *job;
183 unsigned int num_refs;
184 int err;
185
186 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
187 user_relocs = u64_to_user_ptr(args->relocs);
188 user_syncpt = u64_to_user_ptr(args->syncpts);
189
190 /* We don't yet support other than one syncpt_incr struct per submit */
191 if (args->num_syncpts != 1)
192 return -EINVAL;
193
194 /* We don't yet support waitchks */
195 if (args->num_waitchks != 0)
196 return -EINVAL;
197
198 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
199 args->num_relocs, false);
200 if (!job)
201 return -ENOMEM;
202
203 job->num_relocs = args->num_relocs;
204 job->client = client;
205 job->class = client->class;
206 job->serialize = true;
207 job->syncpt_recovery = true;
208
209 /*
210 * Track referenced BOs so that they can be unreferenced after the
211 * submission is complete.
212 */
213 num_refs = num_cmdbufs + num_relocs * 2;
214
215 refs = kmalloc_objs(*refs, num_refs);
216 if (!refs) {
217 err = -ENOMEM;
218 goto put;
219 }
220
221 /* reuse as an iterator later */
222 num_refs = 0;
223
224 while (num_cmdbufs) {
225 struct drm_tegra_cmdbuf cmdbuf;
226 struct host1x_bo *bo;
227 struct tegra_bo *obj;
228 u64 offset;
229
230 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
231 err = -EFAULT;
232 goto fail;
233 }
234
235 /*
236 * The maximum number of CDMA gather fetches is 16383, a higher
237 * value means the words count is malformed.
238 */
239 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
240 err = -EINVAL;
241 goto fail;
242 }
243
244 bo = tegra_gem_lookup(file, cmdbuf.handle);
245 if (!bo) {
246 err = -ENOENT;
247 goto fail;
248 }
249
250 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
251 obj = host1x_to_tegra_bo(bo);
252 refs[num_refs++] = &obj->gem;
253
254 /*
255 * Gather buffer base address must be 4-bytes aligned,
256 * unaligned offset is malformed and cause commands stream
257 * corruption on the buffer address relocation.
258 */
259 if (offset & 3 || offset > obj->gem.size) {
260 err = -EINVAL;
261 goto fail;
262 }
263
264 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
265 num_cmdbufs--;
266 user_cmdbufs++;
267 }
268
269 /* copy and resolve relocations from submit */
270 while (num_relocs--) {
271 struct host1x_reloc *reloc;
272 struct tegra_bo *obj;
273
274 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
275 &user_relocs[num_relocs], drm,
276 file);
277 if (err < 0)
278 goto fail;
279
280 reloc = &job->relocs[num_relocs];
281 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
282 refs[num_refs++] = &obj->gem;
283
284 /*
285 * The unaligned cmdbuf offset will cause an unaligned write
286 * during of the relocations patching, corrupting the commands
287 * stream.
288 */
289 if (reloc->cmdbuf.offset & 3 ||
290 reloc->cmdbuf.offset >= obj->gem.size) {
291 err = -EINVAL;
292 goto fail;
293 }
294
295 obj = host1x_to_tegra_bo(reloc->target.bo);
296 refs[num_refs++] = &obj->gem;
297
298 if (reloc->target.offset >= obj->gem.size) {
299 err = -EINVAL;
300 goto fail;
301 }
302 }
303
304 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
305 err = -EFAULT;
306 goto fail;
307 }
308
309 /* Syncpoint ref will be dropped on job release. */
310 sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
311 if (!sp) {
312 err = -ENOENT;
313 goto fail;
314 }
315
316 job->is_addr_reg = context->client->ops->is_addr_reg;
317 job->is_valid_class = context->client->ops->is_valid_class;
318 job->syncpt_incrs = syncpt.incrs;
319 job->syncpt = sp;
320 job->timeout = 10000;
321
322 if (args->timeout && args->timeout < 10000)
323 job->timeout = args->timeout;
324
325 err = host1x_job_pin(job, context->client->base.dev);
326 if (err)
327 goto fail;
328
329 err = host1x_job_submit(job);
330 if (err) {
331 host1x_job_unpin(job);
332 goto fail;
333 }
334
335 args->fence = job->syncpt_end;
336
337fail:
338 while (num_refs--)
339 drm_gem_object_put(refs[num_refs]);
340
341 kfree(refs);
342
343put:
344 host1x_job_put(job);
345 return err;
346}
347
348
349#ifdef CONFIG_DRM_TEGRA_STAGING
350static int tegra_gem_create(struct drm_device *drm, void *data,
351 struct drm_file *file)
352{
353 struct drm_tegra_gem_create *args = data;
354 struct tegra_bo *bo;
355
356 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
357 &args->handle);
358 if (IS_ERR(bo))
359 return PTR_ERR(bo);
360
361 return 0;
362}
363
364static int tegra_gem_mmap(struct drm_device *drm, void *data,
365 struct drm_file *file)
366{
367 struct drm_tegra_gem_mmap *args = data;
368 struct drm_gem_object *gem;
369 struct tegra_bo *bo;
370
371 gem = drm_gem_object_lookup(file, args->handle);
372 if (!gem)
373 return -EINVAL;
374
375 bo = to_tegra_bo(gem);
376
377 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
378
379 drm_gem_object_put(gem);
380
381 return 0;
382}
383
384static int tegra_syncpt_read(struct drm_device *drm, void *data,
385 struct drm_file *file)
386{
387 struct host1x *host = dev_get_drvdata(drm->dev->parent);
388 struct drm_tegra_syncpt_read *args = data;
389 struct host1x_syncpt *sp;
390
391 sp = host1x_syncpt_get_by_id_noref(host, args->id);
392 if (!sp)
393 return -EINVAL;
394
395 args->value = host1x_syncpt_read_min(sp);
396 return 0;
397}
398
399static int tegra_syncpt_incr(struct drm_device *drm, void *data,
400 struct drm_file *file)
401{
402 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
403 struct drm_tegra_syncpt_incr *args = data;
404 struct host1x_syncpt *sp;
405
406 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
407 if (!sp)
408 return -EINVAL;
409
410 return host1x_syncpt_incr(sp);
411}
412
413static int tegra_syncpt_wait(struct drm_device *drm, void *data,
414 struct drm_file *file)
415{
416 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
417 struct drm_tegra_syncpt_wait *args = data;
418 struct host1x_syncpt *sp;
419
420 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
421 if (!sp)
422 return -EINVAL;
423
424 return host1x_syncpt_wait(sp, args->thresh,
425 msecs_to_jiffies(args->timeout),
426 &args->value);
427}
428
429static int tegra_client_open(struct tegra_drm_file *fpriv,
430 struct tegra_drm_client *client,
431 struct tegra_drm_context *context)
432{
433 int err;
434
435 err = pm_runtime_resume_and_get(client->base.dev);
436 if (err)
437 return err;
438
439 err = client->ops->open_channel(client, context);
440 if (err < 0) {
441 pm_runtime_put(client->base.dev);
442 return err;
443 }
444
445 err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
446 if (err < 0) {
447 client->ops->close_channel(context);
448 pm_runtime_put(client->base.dev);
449 return err;
450 }
451
452 context->client = client;
453 context->id = err;
454
455 return 0;
456}
457
458static int tegra_open_channel(struct drm_device *drm, void *data,
459 struct drm_file *file)
460{
461 struct tegra_drm_file *fpriv = file->driver_priv;
462 struct tegra_drm *tegra = drm->dev_private;
463 struct drm_tegra_open_channel *args = data;
464 struct tegra_drm_context *context;
465 struct tegra_drm_client *client;
466 int err = -ENODEV;
467
468 context = kzalloc_obj(*context);
469 if (!context)
470 return -ENOMEM;
471
472 mutex_lock(&fpriv->lock);
473
474 list_for_each_entry(client, &tegra->clients, list)
475 if (client->base.class == args->client) {
476 err = tegra_client_open(fpriv, client, context);
477 if (err < 0)
478 break;
479
480 args->context = context->id;
481 break;
482 }
483
484 if (err < 0)
485 kfree(context);
486
487 mutex_unlock(&fpriv->lock);
488 return err;
489}
490
491static int tegra_close_channel(struct drm_device *drm, void *data,
492 struct drm_file *file)
493{
494 struct tegra_drm_file *fpriv = file->driver_priv;
495 struct drm_tegra_close_channel *args = data;
496 struct tegra_drm_context *context;
497 int err = 0;
498
499 mutex_lock(&fpriv->lock);
500
501 context = idr_find(&fpriv->legacy_contexts, args->context);
502 if (!context) {
503 err = -EINVAL;
504 goto unlock;
505 }
506
507 idr_remove(&fpriv->legacy_contexts, context->id);
508 tegra_drm_context_free(context);
509
510unlock:
511 mutex_unlock(&fpriv->lock);
512 return err;
513}
514
515static int tegra_get_syncpt(struct drm_device *drm, void *data,
516 struct drm_file *file)
517{
518 struct tegra_drm_file *fpriv = file->driver_priv;
519 struct drm_tegra_get_syncpt *args = data;
520 struct tegra_drm_context *context;
521 struct host1x_syncpt *syncpt;
522 int err = 0;
523
524 mutex_lock(&fpriv->lock);
525
526 context = idr_find(&fpriv->legacy_contexts, args->context);
527 if (!context) {
528 err = -ENODEV;
529 goto unlock;
530 }
531
532 if (args->index >= context->client->base.num_syncpts) {
533 err = -EINVAL;
534 goto unlock;
535 }
536
537 syncpt = context->client->base.syncpts[args->index];
538 args->id = host1x_syncpt_id(syncpt);
539
540unlock:
541 mutex_unlock(&fpriv->lock);
542 return err;
543}
544
545static int tegra_submit(struct drm_device *drm, void *data,
546 struct drm_file *file)
547{
548 struct tegra_drm_file *fpriv = file->driver_priv;
549 struct drm_tegra_submit *args = data;
550 struct tegra_drm_context *context;
551 int err;
552
553 mutex_lock(&fpriv->lock);
554
555 context = idr_find(&fpriv->legacy_contexts, args->context);
556 if (!context) {
557 err = -ENODEV;
558 goto unlock;
559 }
560
561 err = context->client->ops->submit(context, args, drm, file);
562
563unlock:
564 mutex_unlock(&fpriv->lock);
565 return err;
566}
567
568static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
569 struct drm_file *file)
570{
571 struct tegra_drm_file *fpriv = file->driver_priv;
572 struct drm_tegra_get_syncpt_base *args = data;
573 struct tegra_drm_context *context;
574 struct host1x_syncpt_base *base;
575 struct host1x_syncpt *syncpt;
576 int err = 0;
577
578 mutex_lock(&fpriv->lock);
579
580 context = idr_find(&fpriv->legacy_contexts, args->context);
581 if (!context) {
582 err = -ENODEV;
583 goto unlock;
584 }
585
586 if (args->syncpt >= context->client->base.num_syncpts) {
587 err = -EINVAL;
588 goto unlock;
589 }
590
591 syncpt = context->client->base.syncpts[args->syncpt];
592
593 base = host1x_syncpt_get_base(syncpt);
594 if (!base) {
595 err = -ENXIO;
596 goto unlock;
597 }
598
599 args->id = host1x_syncpt_base_id(base);
600
601unlock:
602 mutex_unlock(&fpriv->lock);
603 return err;
604}
605
606static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
607 struct drm_file *file)
608{
609 struct drm_tegra_gem_set_tiling *args = data;
610 enum tegra_bo_tiling_mode mode;
611 struct drm_gem_object *gem;
612 unsigned long value = 0;
613 struct tegra_bo *bo;
614
615 switch (args->mode) {
616 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
617 mode = TEGRA_BO_TILING_MODE_PITCH;
618
619 if (args->value != 0)
620 return -EINVAL;
621
622 break;
623
624 case DRM_TEGRA_GEM_TILING_MODE_TILED:
625 mode = TEGRA_BO_TILING_MODE_TILED;
626
627 if (args->value != 0)
628 return -EINVAL;
629
630 break;
631
632 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
633 mode = TEGRA_BO_TILING_MODE_BLOCK;
634
635 if (args->value > 5)
636 return -EINVAL;
637
638 value = args->value;
639 break;
640
641 default:
642 return -EINVAL;
643 }
644
645 gem = drm_gem_object_lookup(file, args->handle);
646 if (!gem)
647 return -ENOENT;
648
649 bo = to_tegra_bo(gem);
650
651 bo->tiling.mode = mode;
652 bo->tiling.value = value;
653
654 drm_gem_object_put(gem);
655
656 return 0;
657}
658
659static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
660 struct drm_file *file)
661{
662 struct drm_tegra_gem_get_tiling *args = data;
663 struct drm_gem_object *gem;
664 struct tegra_bo *bo;
665 int err = 0;
666
667 gem = drm_gem_object_lookup(file, args->handle);
668 if (!gem)
669 return -ENOENT;
670
671 bo = to_tegra_bo(gem);
672
673 switch (bo->tiling.mode) {
674 case TEGRA_BO_TILING_MODE_PITCH:
675 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
676 args->value = 0;
677 break;
678
679 case TEGRA_BO_TILING_MODE_TILED:
680 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
681 args->value = 0;
682 break;
683
684 case TEGRA_BO_TILING_MODE_BLOCK:
685 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
686 args->value = bo->tiling.value;
687 break;
688
689 default:
690 err = -EINVAL;
691 break;
692 }
693
694 drm_gem_object_put(gem);
695
696 return err;
697}
698
699static int tegra_gem_set_flags(struct drm_device *drm, void *data,
700 struct drm_file *file)
701{
702 struct drm_tegra_gem_set_flags *args = data;
703 struct drm_gem_object *gem;
704 struct tegra_bo *bo;
705
706 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
707 return -EINVAL;
708
709 gem = drm_gem_object_lookup(file, args->handle);
710 if (!gem)
711 return -ENOENT;
712
713 bo = to_tegra_bo(gem);
714 bo->flags = 0;
715
716 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
717 bo->flags |= TEGRA_BO_BOTTOM_UP;
718
719 drm_gem_object_put(gem);
720
721 return 0;
722}
723
724static int tegra_gem_get_flags(struct drm_device *drm, void *data,
725 struct drm_file *file)
726{
727 struct drm_tegra_gem_get_flags *args = data;
728 struct drm_gem_object *gem;
729 struct tegra_bo *bo;
730
731 gem = drm_gem_object_lookup(file, args->handle);
732 if (!gem)
733 return -ENOENT;
734
735 bo = to_tegra_bo(gem);
736 args->flags = 0;
737
738 if (bo->flags & TEGRA_BO_BOTTOM_UP)
739 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
740
741 drm_gem_object_put(gem);
742
743 return 0;
744}
745#endif
746
747static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
748#ifdef CONFIG_DRM_TEGRA_STAGING
749 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open,
750 DRM_RENDER_ALLOW),
751 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close,
752 DRM_RENDER_ALLOW),
753 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map,
754 DRM_RENDER_ALLOW),
755 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap,
756 DRM_RENDER_ALLOW),
757 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_SUBMIT, tegra_drm_ioctl_channel_submit,
758 DRM_RENDER_ALLOW),
759 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_ALLOCATE, tegra_drm_ioctl_syncpoint_allocate,
760 DRM_RENDER_ALLOW),
761 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_FREE, tegra_drm_ioctl_syncpoint_free,
762 DRM_RENDER_ALLOW),
763 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_WAIT, tegra_drm_ioctl_syncpoint_wait,
764 DRM_RENDER_ALLOW),
765
766 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_RENDER_ALLOW),
767 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_RENDER_ALLOW),
768 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
769 DRM_RENDER_ALLOW),
770 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
771 DRM_RENDER_ALLOW),
772 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
773 DRM_RENDER_ALLOW),
774 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
775 DRM_RENDER_ALLOW),
776 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
777 DRM_RENDER_ALLOW),
778 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
779 DRM_RENDER_ALLOW),
780 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
781 DRM_RENDER_ALLOW),
782 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
783 DRM_RENDER_ALLOW),
784 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
785 DRM_RENDER_ALLOW),
786 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
787 DRM_RENDER_ALLOW),
788 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
789 DRM_RENDER_ALLOW),
790 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
791 DRM_RENDER_ALLOW),
792#endif
793};
794
795static const struct file_operations tegra_drm_fops = {
796 .owner = THIS_MODULE,
797 .open = drm_open,
798 .release = drm_release,
799 .unlocked_ioctl = drm_ioctl,
800 .mmap = tegra_drm_mmap,
801 .poll = drm_poll,
802 .read = drm_read,
803 .compat_ioctl = drm_compat_ioctl,
804 .llseek = noop_llseek,
805 .fop_flags = FOP_UNSIGNED_OFFSET,
806};
807
808static int tegra_drm_context_cleanup(int id, void *p, void *data)
809{
810 struct tegra_drm_context *context = p;
811
812 tegra_drm_context_free(context);
813
814 return 0;
815}
816
817static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
818{
819 struct tegra_drm_file *fpriv = file->driver_priv;
820
821 mutex_lock(&fpriv->lock);
822 idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
823 tegra_drm_uapi_close_file(fpriv);
824 mutex_unlock(&fpriv->lock);
825
826 idr_destroy(&fpriv->legacy_contexts);
827 mutex_destroy(&fpriv->lock);
828 kfree(fpriv);
829}
830
831#ifdef CONFIG_DEBUG_FS
832static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
833{
834 struct drm_info_node *node = (struct drm_info_node *)s->private;
835 struct drm_device *drm = node->minor->dev;
836 struct drm_framebuffer *fb;
837
838 mutex_lock(&drm->mode_config.fb_lock);
839
840 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
841 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
842 fb->base.id, fb->width, fb->height,
843 fb->format->depth,
844 fb->format->cpp[0] * 8,
845 drm_framebuffer_read_refcount(fb));
846 }
847
848 mutex_unlock(&drm->mode_config.fb_lock);
849
850 return 0;
851}
852
853static int tegra_debugfs_iova(struct seq_file *s, void *data)
854{
855 struct drm_info_node *node = (struct drm_info_node *)s->private;
856 struct drm_device *drm = node->minor->dev;
857 struct tegra_drm *tegra = drm->dev_private;
858 struct drm_printer p = drm_seq_file_printer(s);
859
860 if (tegra->domain) {
861 mutex_lock(&tegra->mm_lock);
862 drm_mm_print(&tegra->mm, &p);
863 mutex_unlock(&tegra->mm_lock);
864 }
865
866 return 0;
867}
868
869static struct drm_info_list tegra_debugfs_list[] = {
870 { "framebuffers", tegra_debugfs_framebuffers, 0 },
871 { "iova", tegra_debugfs_iova, 0 },
872};
873
874static void tegra_debugfs_init(struct drm_minor *minor)
875{
876 drm_debugfs_create_files(tegra_debugfs_list,
877 ARRAY_SIZE(tegra_debugfs_list),
878 minor->debugfs_root, minor);
879}
880#endif
881
882static const struct drm_driver tegra_drm_driver = {
883 .driver_features = DRIVER_MODESET | DRIVER_GEM |
884 DRIVER_ATOMIC | DRIVER_RENDER | DRIVER_SYNCOBJ,
885 .open = tegra_drm_open,
886 .postclose = tegra_drm_postclose,
887
888#if defined(CONFIG_DEBUG_FS)
889 .debugfs_init = tegra_debugfs_init,
890#endif
891
892 .gem_prime_import = tegra_gem_prime_import,
893
894 .dumb_create = tegra_bo_dumb_create,
895
896 TEGRA_FBDEV_DRIVER_OPS,
897
898 .ioctls = tegra_drm_ioctls,
899 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
900 .fops = &tegra_drm_fops,
901
902 .name = DRIVER_NAME,
903 .desc = DRIVER_DESC,
904 .major = DRIVER_MAJOR,
905 .minor = DRIVER_MINOR,
906 .patchlevel = DRIVER_PATCHLEVEL,
907};
908
909int tegra_drm_register_client(struct tegra_drm *tegra,
910 struct tegra_drm_client *client)
911{
912 /*
913 * When MLOCKs are implemented, change to allocate a shared channel
914 * only when MLOCKs are disabled.
915 */
916 client->shared_channel = host1x_channel_request(&client->base);
917 if (!client->shared_channel)
918 return -EBUSY;
919
920 mutex_lock(&tegra->clients_lock);
921 list_add_tail(&client->list, &tegra->clients);
922 client->drm = tegra;
923 mutex_unlock(&tegra->clients_lock);
924
925 return 0;
926}
927
928int tegra_drm_unregister_client(struct tegra_drm *tegra,
929 struct tegra_drm_client *client)
930{
931 mutex_lock(&tegra->clients_lock);
932 list_del_init(&client->list);
933 client->drm = NULL;
934 mutex_unlock(&tegra->clients_lock);
935
936 if (client->shared_channel)
937 host1x_channel_put(client->shared_channel);
938
939 return 0;
940}
941
942int host1x_client_iommu_attach(struct host1x_client *client)
943{
944 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
945 struct drm_device *drm = dev_get_drvdata(client->host);
946 struct tegra_drm *tegra = drm->dev_private;
947 struct iommu_group *group = NULL;
948 int err;
949
950#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
951 if (client->dev->archdata.mapping) {
952 struct dma_iommu_mapping *mapping =
953 to_dma_iommu_mapping(client->dev);
954 arm_iommu_detach_device(client->dev);
955 arm_iommu_release_mapping(mapping);
956
957 domain = iommu_get_domain_for_dev(client->dev);
958 }
959#endif
960
961 /*
962 * If the host1x client is already attached to an IOMMU domain that is
963 * not the shared IOMMU domain, don't try to attach it to a different
964 * domain. This allows using the IOMMU-backed DMA API.
965 */
966 if (domain && domain->type != IOMMU_DOMAIN_IDENTITY &&
967 domain != tegra->domain)
968 return 0;
969
970 if (tegra->domain) {
971 group = iommu_group_get(client->dev);
972 if (!group)
973 return -ENODEV;
974
975 if (domain != tegra->domain) {
976 err = iommu_attach_group(tegra->domain, group);
977 if (err < 0) {
978 iommu_group_put(group);
979 return err;
980 }
981 }
982
983 tegra->use_explicit_iommu = true;
984 }
985
986 client->group = group;
987
988 return 0;
989}
990
991void host1x_client_iommu_detach(struct host1x_client *client)
992{
993 struct drm_device *drm = dev_get_drvdata(client->host);
994 struct tegra_drm *tegra = drm->dev_private;
995 struct iommu_domain *domain;
996
997 if (client->group) {
998 /*
999 * Devices that are part of the same group may no longer be
1000 * attached to a domain at this point because their group may
1001 * have been detached by an earlier client.
1002 */
1003 domain = iommu_get_domain_for_dev(client->dev);
1004 if (domain)
1005 iommu_detach_group(tegra->domain, client->group);
1006
1007 iommu_group_put(client->group);
1008 client->group = NULL;
1009 }
1010}
1011
1012void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
1013{
1014 struct iova *alloc;
1015 void *virt;
1016 gfp_t gfp;
1017 int err;
1018
1019 if (tegra->domain)
1020 size = iova_align(&tegra->carveout.domain, size);
1021 else
1022 size = PAGE_ALIGN(size);
1023
1024 gfp = GFP_KERNEL | __GFP_ZERO;
1025 if (!tegra->domain) {
1026 /*
1027 * Many units only support 32-bit addresses, even on 64-bit
1028 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1029 * virtual address space, force allocations to be in the
1030 * lower 32-bit range.
1031 */
1032 gfp |= GFP_DMA;
1033 }
1034
1035 virt = (void *)__get_free_pages(gfp, get_order(size));
1036 if (!virt)
1037 return ERR_PTR(-ENOMEM);
1038
1039 if (!tegra->domain) {
1040 /*
1041 * If IOMMU is disabled, devices address physical memory
1042 * directly.
1043 */
1044 *dma = virt_to_phys(virt);
1045 return virt;
1046 }
1047
1048 alloc = alloc_iova(&tegra->carveout.domain,
1049 size >> tegra->carveout.shift,
1050 tegra->carveout.limit, true);
1051 if (!alloc) {
1052 err = -EBUSY;
1053 goto free_pages;
1054 }
1055
1056 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1057 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1058 size, IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
1059 if (err < 0)
1060 goto free_iova;
1061
1062 return virt;
1063
1064free_iova:
1065 __free_iova(&tegra->carveout.domain, alloc);
1066free_pages:
1067 free_pages((unsigned long)virt, get_order(size));
1068
1069 return ERR_PTR(err);
1070}
1071
1072void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1073 dma_addr_t dma)
1074{
1075 if (tegra->domain)
1076 size = iova_align(&tegra->carveout.domain, size);
1077 else
1078 size = PAGE_ALIGN(size);
1079
1080 if (tegra->domain) {
1081 iommu_unmap(tegra->domain, dma, size);
1082 free_iova(&tegra->carveout.domain,
1083 iova_pfn(&tegra->carveout.domain, dma));
1084 }
1085
1086 free_pages((unsigned long)virt, get_order(size));
1087}
1088
1089static bool host1x_drm_wants_iommu(struct host1x_device *dev)
1090{
1091 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1092 struct iommu_domain *domain;
1093
1094 /* Our IOMMU usage policy doesn't currently play well with GART */
1095 if (of_machine_is_compatible("nvidia,tegra20"))
1096 return false;
1097
1098 /*
1099 * If the Tegra DRM clients are backed by an IOMMU, push buffers are
1100 * likely to be allocated beyond the 32-bit boundary if sufficient
1101 * system memory is available. This is problematic on earlier Tegra
1102 * generations where host1x supports a maximum of 32 address bits in
1103 * the GATHER opcode. In this case, unless host1x is behind an IOMMU
1104 * as well it won't be able to process buffers allocated beyond the
1105 * 32-bit boundary.
1106 *
1107 * The DMA API will use bounce buffers in this case, so that could
1108 * perhaps still be made to work, even if less efficient, but there
1109 * is another catch: in order to perform cache maintenance on pages
1110 * allocated for discontiguous buffers we need to map and unmap the
1111 * SG table representing these buffers. This is fine for something
1112 * small like a push buffer, but it exhausts the bounce buffer pool
1113 * (typically on the order of a few MiB) for framebuffers (many MiB
1114 * for any modern resolution).
1115 *
1116 * Work around this by making sure that Tegra DRM clients only use
1117 * an IOMMU if the parent host1x also uses an IOMMU.
1118 *
1119 * Note that there's still a small gap here that we don't cover: if
1120 * the DMA API is backed by an IOMMU there's no way to control which
1121 * device is attached to an IOMMU and which isn't, except via wiring
1122 * up the device tree appropriately. This is considered an problem
1123 * of integration, so care must be taken for the DT to be consistent.
1124 */
1125 domain = iommu_get_domain_for_dev(dev->dev.parent);
1126
1127 /*
1128 * Tegra20 and Tegra30 don't support addressing memory beyond the
1129 * 32-bit boundary, so the regular GATHER opcodes will always be
1130 * sufficient and whether or not the host1x is attached to an IOMMU
1131 * doesn't matter.
1132 */
1133 if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
1134 return true;
1135
1136 return domain != NULL;
1137}
1138
1139static int host1x_drm_probe(struct host1x_device *dev)
1140{
1141 struct device *dma_dev = dev->dev.parent;
1142 struct tegra_drm *tegra;
1143 struct drm_device *drm;
1144 int err;
1145
1146 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1147 if (IS_ERR(drm))
1148 return PTR_ERR(drm);
1149
1150 tegra = kzalloc_obj(*tegra);
1151 if (!tegra) {
1152 err = -ENOMEM;
1153 goto put;
1154 }
1155
1156 if (host1x_drm_wants_iommu(dev) && device_iommu_mapped(dma_dev)) {
1157 tegra->domain = iommu_paging_domain_alloc(dma_dev);
1158 if (IS_ERR(tegra->domain)) {
1159 err = PTR_ERR(tegra->domain);
1160 goto free;
1161 }
1162
1163 err = iova_cache_get();
1164 if (err < 0)
1165 goto domain;
1166 }
1167
1168 mutex_init(&tegra->clients_lock);
1169 INIT_LIST_HEAD(&tegra->clients);
1170
1171 dev_set_drvdata(&dev->dev, drm);
1172 drm->dev_private = tegra;
1173 tegra->drm = drm;
1174
1175 drm_mode_config_init(drm);
1176
1177 drm->mode_config.min_width = 0;
1178 drm->mode_config.min_height = 0;
1179 drm->mode_config.max_width = 0;
1180 drm->mode_config.max_height = 0;
1181
1182 drm->mode_config.normalize_zpos = true;
1183
1184 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1185 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1186
1187 drm_kms_helper_poll_init(drm);
1188
1189 err = host1x_device_init(dev);
1190 if (err < 0)
1191 goto poll;
1192
1193 /*
1194 * Now that all display controller have been initialized, the maximum
1195 * supported resolution is known and the bitmask for horizontal and
1196 * vertical bitfields can be computed.
1197 */
1198 tegra->hmask = drm->mode_config.max_width - 1;
1199 tegra->vmask = drm->mode_config.max_height - 1;
1200
1201 if (tegra->use_explicit_iommu) {
1202 u64 carveout_start, carveout_end, gem_start, gem_end;
1203 u64 dma_mask = dma_get_mask(&dev->dev);
1204 dma_addr_t start, end;
1205 unsigned long order;
1206
1207 start = tegra->domain->geometry.aperture_start & dma_mask;
1208 end = tegra->domain->geometry.aperture_end & dma_mask;
1209
1210 gem_start = start;
1211 gem_end = end - CARVEOUT_SZ;
1212 carveout_start = gem_end + 1;
1213 carveout_end = end;
1214
1215 order = __ffs(tegra->domain->pgsize_bitmap);
1216 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1217 carveout_start >> order);
1218
1219 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1220 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1221
1222 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1223 mutex_init(&tegra->mm_lock);
1224
1225 DRM_DEBUG_DRIVER("IOMMU apertures:\n");
1226 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1227 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1228 carveout_end);
1229 } else if (tegra->domain) {
1230 iommu_domain_free(tegra->domain);
1231 tegra->domain = NULL;
1232 iova_cache_put();
1233 }
1234
1235 if (tegra->hub) {
1236 err = tegra_display_hub_prepare(tegra->hub);
1237 if (err < 0)
1238 goto device;
1239 }
1240
1241 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1242 drm->max_vblank_count = 0xffffffff;
1243
1244 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1245 if (err < 0)
1246 goto hub;
1247
1248 drm_mode_config_reset(drm);
1249
1250 /*
1251 * Only take over from a potential firmware framebuffer if any CRTCs
1252 * have been registered. This must not be a fatal error because there
1253 * are other accelerators that are exposed via this driver.
1254 *
1255 * Another case where this happens is on Tegra234 where the display
1256 * hardware is no longer part of the host1x complex, so this driver
1257 * will not expose any modesetting features.
1258 */
1259 if (drm->mode_config.num_crtc > 0) {
1260 err = aperture_remove_all_conflicting_devices(tegra_drm_driver.name);
1261 if (err < 0)
1262 goto hub;
1263 } else {
1264 /*
1265 * Indicate to userspace that this doesn't expose any display
1266 * capabilities.
1267 */
1268 drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1269 }
1270
1271 err = drm_dev_register(drm, 0);
1272 if (err < 0)
1273 goto hub;
1274
1275 drm_client_setup(drm, NULL);
1276
1277 return 0;
1278
1279hub:
1280 if (tegra->hub)
1281 tegra_display_hub_cleanup(tegra->hub);
1282device:
1283 if (tegra->domain) {
1284 mutex_destroy(&tegra->mm_lock);
1285 drm_mm_takedown(&tegra->mm);
1286 put_iova_domain(&tegra->carveout.domain);
1287 iova_cache_put();
1288 }
1289
1290 host1x_device_exit(dev);
1291poll:
1292 drm_kms_helper_poll_fini(drm);
1293 drm_mode_config_cleanup(drm);
1294domain:
1295 if (tegra->domain)
1296 iommu_domain_free(tegra->domain);
1297free:
1298 kfree(tegra);
1299put:
1300 drm_dev_put(drm);
1301 return err;
1302}
1303
1304static void host1x_drm_remove(struct host1x_device *dev)
1305{
1306 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1307 struct tegra_drm *tegra = drm->dev_private;
1308 int err;
1309
1310 drm_dev_unregister(drm);
1311
1312 drm_kms_helper_poll_fini(drm);
1313 drm_atomic_helper_shutdown(drm);
1314 drm_mode_config_cleanup(drm);
1315
1316 if (tegra->hub)
1317 tegra_display_hub_cleanup(tegra->hub);
1318
1319 err = host1x_device_exit(dev);
1320 if (err < 0)
1321 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1322
1323 if (tegra->domain) {
1324 mutex_destroy(&tegra->mm_lock);
1325 drm_mm_takedown(&tegra->mm);
1326 put_iova_domain(&tegra->carveout.domain);
1327 iova_cache_put();
1328 iommu_domain_free(tegra->domain);
1329 }
1330
1331 kfree(tegra);
1332 drm_dev_put(drm);
1333}
1334
1335static void host1x_drm_shutdown(struct host1x_device *dev)
1336{
1337 drm_atomic_helper_shutdown(dev_get_drvdata(&dev->dev));
1338}
1339
1340#ifdef CONFIG_PM_SLEEP
1341static int host1x_drm_suspend(struct device *dev)
1342{
1343 struct drm_device *drm = dev_get_drvdata(dev);
1344
1345 return drm_mode_config_helper_suspend(drm);
1346}
1347
1348static int host1x_drm_resume(struct device *dev)
1349{
1350 struct drm_device *drm = dev_get_drvdata(dev);
1351
1352 return drm_mode_config_helper_resume(drm);
1353}
1354#endif
1355
1356static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1357 host1x_drm_resume);
1358
1359static const struct of_device_id host1x_drm_subdevs[] = {
1360 { .compatible = "nvidia,tegra20-dc", },
1361 { .compatible = "nvidia,tegra20-dsi", },
1362 { .compatible = "nvidia,tegra20-hdmi", },
1363 { .compatible = "nvidia,tegra20-gr2d", },
1364 { .compatible = "nvidia,tegra20-gr3d", },
1365 { .compatible = "nvidia,tegra30-dc", },
1366 { .compatible = "nvidia,tegra30-dsi", },
1367 { .compatible = "nvidia,tegra30-hdmi", },
1368 { .compatible = "nvidia,tegra30-gr2d", },
1369 { .compatible = "nvidia,tegra30-gr3d", },
1370 { .compatible = "nvidia,tegra114-dc", },
1371 { .compatible = "nvidia,tegra114-dsi", },
1372 { .compatible = "nvidia,tegra114-hdmi", },
1373 { .compatible = "nvidia,tegra114-gr2d", },
1374 { .compatible = "nvidia,tegra114-gr3d", },
1375 { .compatible = "nvidia,tegra124-dc", },
1376 { .compatible = "nvidia,tegra124-sor", },
1377 { .compatible = "nvidia,tegra124-hdmi", },
1378 { .compatible = "nvidia,tegra124-dsi", },
1379 { .compatible = "nvidia,tegra124-vic", },
1380 { .compatible = "nvidia,tegra132-dsi", },
1381 { .compatible = "nvidia,tegra210-dc", },
1382 { .compatible = "nvidia,tegra210-dsi", },
1383 { .compatible = "nvidia,tegra210-sor", },
1384 { .compatible = "nvidia,tegra210-sor1", },
1385 { .compatible = "nvidia,tegra210-vic", },
1386 { .compatible = "nvidia,tegra210-nvdec", },
1387 { .compatible = "nvidia,tegra210-nvjpg", },
1388 { .compatible = "nvidia,tegra186-display", },
1389 { .compatible = "nvidia,tegra186-dc", },
1390 { .compatible = "nvidia,tegra186-sor", },
1391 { .compatible = "nvidia,tegra186-sor1", },
1392 { .compatible = "nvidia,tegra186-vic", },
1393 { .compatible = "nvidia,tegra186-nvdec", },
1394 { .compatible = "nvidia,tegra194-display", },
1395 { .compatible = "nvidia,tegra194-dc", },
1396 { .compatible = "nvidia,tegra194-sor", },
1397 { .compatible = "nvidia,tegra194-vic", },
1398 { .compatible = "nvidia,tegra194-nvdec", },
1399 { .compatible = "nvidia,tegra234-vic", },
1400 { .compatible = "nvidia,tegra234-nvdec", },
1401 { .compatible = "nvidia,tegra264-vic", },
1402 { /* sentinel */ }
1403};
1404
1405static struct host1x_driver host1x_drm_driver = {
1406 .driver = {
1407 .name = "drm",
1408 .pm = &host1x_drm_pm_ops,
1409 },
1410 .probe = host1x_drm_probe,
1411 .remove = host1x_drm_remove,
1412 .shutdown = host1x_drm_shutdown,
1413 .subdevs = host1x_drm_subdevs,
1414};
1415
1416static struct platform_driver * const drivers[] = {
1417 &tegra_display_hub_driver,
1418 &tegra_dc_driver,
1419 &tegra_hdmi_driver,
1420 &tegra_dsi_driver,
1421 &tegra_dpaux_driver,
1422 &tegra_sor_driver,
1423 &tegra_gr2d_driver,
1424 &tegra_gr3d_driver,
1425 &tegra_vic_driver,
1426 &tegra_nvdec_driver,
1427 &tegra_nvjpg_driver,
1428};
1429
1430static int __init host1x_drm_init(void)
1431{
1432 int err;
1433
1434 if (drm_firmware_drivers_only())
1435 return -ENODEV;
1436
1437 err = host1x_driver_register(&host1x_drm_driver);
1438 if (err < 0)
1439 return err;
1440
1441 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1442 if (err < 0)
1443 goto unregister_host1x;
1444
1445 return 0;
1446
1447unregister_host1x:
1448 host1x_driver_unregister(&host1x_drm_driver);
1449 return err;
1450}
1451module_init(host1x_drm_init);
1452
1453static void __exit host1x_drm_exit(void)
1454{
1455 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1456 host1x_driver_unregister(&host1x_drm_driver);
1457}
1458module_exit(host1x_drm_exit);
1459
1460MODULE_AUTHOR("Thierry Reding <[email protected]>");
1461MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1462MODULE_LICENSE("GPL v2");