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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2013, NVIDIA Corporation.
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/iommu.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/pm_runtime.h>
13#include <linux/reset.h>
14
15#include <soc/tegra/common.h>
16
17#include "drm.h"
18#include "gem.h"
19#include "gr2d.h"
20
21enum {
22 RST_MC,
23 RST_GR2D,
24 RST_GR2D_MAX,
25};
26
27struct gr2d_soc {
28 unsigned int version;
29};
30
31struct gr2d {
32 struct tegra_drm_client client;
33 struct host1x_channel *channel;
34 struct clk *clk;
35
36 struct reset_control_bulk_data resets[RST_GR2D_MAX];
37 unsigned int nresets;
38
39 const struct gr2d_soc *soc;
40
41 DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS);
42};
43
44static inline struct gr2d *to_gr2d(struct tegra_drm_client *client)
45{
46 return container_of(client, struct gr2d, client);
47}
48
49static int gr2d_init(struct host1x_client *client)
50{
51 struct tegra_drm_client *drm = host1x_to_drm_client(client);
52 struct drm_device *dev = dev_get_drvdata(client->host);
53 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
54 struct gr2d *gr2d = to_gr2d(drm);
55 int err;
56
57 gr2d->channel = host1x_channel_request(client);
58 if (!gr2d->channel)
59 return -ENOMEM;
60
61 client->syncpts[0] = host1x_syncpt_request(client, flags);
62 if (!client->syncpts[0]) {
63 err = -ENOMEM;
64 dev_err(client->dev, "failed to request syncpoint: %d\n", err);
65 goto put;
66 }
67
68 err = host1x_client_iommu_attach(client);
69 if (err < 0) {
70 dev_err(client->dev, "failed to attach to domain: %d\n", err);
71 goto free;
72 }
73
74 err = tegra_drm_register_client(dev->dev_private, drm);
75 if (err < 0) {
76 dev_err(client->dev, "failed to register client: %d\n", err);
77 goto detach_iommu;
78 }
79
80 return 0;
81
82detach_iommu:
83 host1x_client_iommu_detach(client);
84free:
85 host1x_syncpt_put(client->syncpts[0]);
86put:
87 host1x_channel_put(gr2d->channel);
88 return err;
89}
90
91static int gr2d_exit(struct host1x_client *client)
92{
93 struct tegra_drm_client *drm = host1x_to_drm_client(client);
94 struct drm_device *dev = dev_get_drvdata(client->host);
95 struct tegra_drm *tegra = dev->dev_private;
96 struct gr2d *gr2d = to_gr2d(drm);
97 int err;
98
99 err = tegra_drm_unregister_client(tegra, drm);
100 if (err < 0)
101 return err;
102
103 host1x_client_iommu_detach(client);
104 host1x_syncpt_put(client->syncpts[0]);
105 host1x_channel_put(gr2d->channel);
106
107 gr2d->channel = NULL;
108
109 return 0;
110}
111
112static const struct host1x_client_ops gr2d_client_ops = {
113 .init = gr2d_init,
114 .exit = gr2d_exit,
115};
116
117static int gr2d_open_channel(struct tegra_drm_client *client,
118 struct tegra_drm_context *context)
119{
120 struct gr2d *gr2d = to_gr2d(client);
121
122 context->channel = host1x_channel_get(gr2d->channel);
123 if (!context->channel)
124 return -ENOMEM;
125
126 return 0;
127}
128
129static void gr2d_close_channel(struct tegra_drm_context *context)
130{
131 host1x_channel_put(context->channel);
132}
133
134static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset)
135{
136 struct gr2d *gr2d = dev_get_drvdata(dev);
137
138 switch (class) {
139 case HOST1X_CLASS_HOST1X:
140 if (offset == 0x2b)
141 return 1;
142
143 break;
144
145 case HOST1X_CLASS_GR2D:
146 case HOST1X_CLASS_GR2D_SB:
147 if (offset >= GR2D_NUM_REGS)
148 break;
149
150 if (test_bit(offset, gr2d->addr_regs))
151 return 1;
152
153 break;
154 }
155
156 return 0;
157}
158
159static int gr2d_is_valid_class(u32 class)
160{
161 return (class == HOST1X_CLASS_GR2D ||
162 class == HOST1X_CLASS_GR2D_SB);
163}
164
165static const struct tegra_drm_client_ops gr2d_ops = {
166 .open_channel = gr2d_open_channel,
167 .close_channel = gr2d_close_channel,
168 .is_addr_reg = gr2d_is_addr_reg,
169 .is_valid_class = gr2d_is_valid_class,
170 .submit = tegra_drm_submit,
171};
172
173static const struct gr2d_soc tegra20_gr2d_soc = {
174 .version = 0x20,
175};
176
177static const struct gr2d_soc tegra30_gr2d_soc = {
178 .version = 0x30,
179};
180
181static const struct gr2d_soc tegra114_gr2d_soc = {
182 .version = 0x35,
183};
184
185static const struct of_device_id gr2d_match[] = {
186 { .compatible = "nvidia,tegra114-gr2d", .data = &tegra114_gr2d_soc },
187 { .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc },
188 { .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc },
189 { },
190};
191MODULE_DEVICE_TABLE(of, gr2d_match);
192
193static const u32 gr2d_addr_regs[] = {
194 GR2D_UA_BASE_ADDR,
195 GR2D_VA_BASE_ADDR,
196 GR2D_PAT_BASE_ADDR,
197 GR2D_DSTA_BASE_ADDR,
198 GR2D_DSTB_BASE_ADDR,
199 GR2D_DSTC_BASE_ADDR,
200 GR2D_SRCA_BASE_ADDR,
201 GR2D_SRCB_BASE_ADDR,
202 GR2D_PATBASE_ADDR,
203 GR2D_SRC_BASE_ADDR_SB,
204 GR2D_DSTA_BASE_ADDR_SB,
205 GR2D_DSTB_BASE_ADDR_SB,
206 GR2D_UA_BASE_ADDR_SB,
207 GR2D_VA_BASE_ADDR_SB,
208};
209
210static int gr2d_get_resets(struct device *dev, struct gr2d *gr2d)
211{
212 int err;
213
214 gr2d->resets[RST_MC].id = "mc";
215 gr2d->resets[RST_GR2D].id = "2d";
216 gr2d->nresets = RST_GR2D_MAX;
217
218 err = devm_reset_control_bulk_get_optional_exclusive_released(
219 dev, gr2d->nresets, gr2d->resets);
220 if (err) {
221 dev_err(dev, "failed to get reset: %d\n", err);
222 return err;
223 }
224
225 if (WARN_ON(!gr2d->resets[RST_GR2D].rstc))
226 return -ENOENT;
227
228 return 0;
229}
230
231static int gr2d_probe(struct platform_device *pdev)
232{
233 struct device *dev = &pdev->dev;
234 struct host1x_syncpt **syncpts;
235 struct gr2d *gr2d;
236 unsigned int i;
237 int err;
238
239 gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL);
240 if (!gr2d)
241 return -ENOMEM;
242
243 platform_set_drvdata(pdev, gr2d);
244
245 gr2d->soc = of_device_get_match_data(dev);
246
247 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
248 if (!syncpts)
249 return -ENOMEM;
250
251 gr2d->clk = devm_clk_get(dev, NULL);
252 if (IS_ERR(gr2d->clk)) {
253 dev_err(dev, "cannot get clock\n");
254 return PTR_ERR(gr2d->clk);
255 }
256
257 err = gr2d_get_resets(dev, gr2d);
258 if (err)
259 return err;
260
261 INIT_LIST_HEAD(&gr2d->client.base.list);
262 gr2d->client.base.ops = &gr2d_client_ops;
263 gr2d->client.base.dev = dev;
264 gr2d->client.base.class = HOST1X_CLASS_GR2D;
265 gr2d->client.base.syncpts = syncpts;
266 gr2d->client.base.num_syncpts = 1;
267
268 INIT_LIST_HEAD(&gr2d->client.list);
269 gr2d->client.version = gr2d->soc->version;
270 gr2d->client.ops = &gr2d_ops;
271
272 err = devm_tegra_core_dev_init_opp_table_common(dev);
273 if (err)
274 return err;
275
276 /* initialize address register map */
277 for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++)
278 set_bit(gr2d_addr_regs[i], gr2d->addr_regs);
279
280 pm_runtime_enable(dev);
281
282 err = host1x_client_register(&gr2d->client.base);
283 if (err < 0) {
284 pm_runtime_disable(dev);
285 dev_err(dev, "failed to register host1x client: %d\n", err);
286 return err;
287 }
288
289 pm_runtime_use_autosuspend(dev);
290 pm_runtime_set_autosuspend_delay(dev, 500);
291
292 return 0;
293}
294
295static void gr2d_remove(struct platform_device *pdev)
296{
297 struct gr2d *gr2d = platform_get_drvdata(pdev);
298
299 pm_runtime_disable(&pdev->dev);
300 host1x_client_unregister(&gr2d->client.base);
301}
302
303static int __maybe_unused gr2d_runtime_suspend(struct device *dev)
304{
305 struct gr2d *gr2d = dev_get_drvdata(dev);
306 int err;
307
308 host1x_channel_stop(gr2d->channel);
309 reset_control_bulk_release(gr2d->nresets, gr2d->resets);
310
311 /*
312 * GR2D module shouldn't be reset while hardware is idling, otherwise
313 * host1x's cmdproc will stuck on trying to access any G2 register
314 * after reset. GR2D module could be either hot-reset or reset after
315 * power-gating of the HEG partition. Hence we will put in reset only
316 * the memory client part of the module, the HEG GENPD will take care
317 * of resetting GR2D module across power-gating.
318 *
319 * On Tegra20 there is no HEG partition, but it's okay to have
320 * undetermined h/w state since userspace is expected to reprogram
321 * the state on each job submission anyways.
322 */
323 err = reset_control_acquire(gr2d->resets[RST_MC].rstc);
324 if (err) {
325 dev_err(dev, "failed to acquire MC reset: %d\n", err);
326 goto acquire_reset;
327 }
328
329 err = reset_control_assert(gr2d->resets[RST_MC].rstc);
330 reset_control_release(gr2d->resets[RST_MC].rstc);
331 if (err) {
332 dev_err(dev, "failed to assert MC reset: %d\n", err);
333 goto acquire_reset;
334 }
335
336 clk_disable_unprepare(gr2d->clk);
337
338 return 0;
339
340acquire_reset:
341 reset_control_bulk_acquire(gr2d->nresets, gr2d->resets);
342 reset_control_bulk_deassert(gr2d->nresets, gr2d->resets);
343
344 return err;
345}
346
347static int __maybe_unused gr2d_runtime_resume(struct device *dev)
348{
349 struct gr2d *gr2d = dev_get_drvdata(dev);
350 int err;
351
352 err = reset_control_bulk_acquire(gr2d->nresets, gr2d->resets);
353 if (err) {
354 dev_err(dev, "failed to acquire reset: %d\n", err);
355 return err;
356 }
357
358 err = clk_prepare_enable(gr2d->clk);
359 if (err) {
360 dev_err(dev, "failed to enable clock: %d\n", err);
361 goto release_reset;
362 }
363
364 usleep_range(2000, 4000);
365
366 /* this is a reset array which deasserts both 2D MC and 2D itself */
367 err = reset_control_bulk_deassert(gr2d->nresets, gr2d->resets);
368 if (err) {
369 dev_err(dev, "failed to deassert reset: %d\n", err);
370 goto disable_clk;
371 }
372
373 return 0;
374
375disable_clk:
376 clk_disable_unprepare(gr2d->clk);
377release_reset:
378 reset_control_bulk_release(gr2d->nresets, gr2d->resets);
379
380 return err;
381}
382
383static const struct dev_pm_ops tegra_gr2d_pm = {
384 SET_RUNTIME_PM_OPS(gr2d_runtime_suspend, gr2d_runtime_resume, NULL)
385 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
386 pm_runtime_force_resume)
387};
388
389struct platform_driver tegra_gr2d_driver = {
390 .driver = {
391 .name = "tegra-gr2d",
392 .of_match_table = gr2d_match,
393 .pm = &tegra_gr2d_pm,
394 },
395 .probe = gr2d_probe,
396 .remove = gr2d_remove,
397};