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1926 lines · 56.2 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/hdmi.h>
11#include <linux/math64.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pm_opp.h>
16#include <linux/pm_runtime.h>
17#include <linux/regulator/consumer.h>
18#include <linux/reset.h>
19
20#include <soc/tegra/common.h>
21#include <sound/hdmi-codec.h>
22
23#include <drm/drm_bridge_connector.h>
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_edid.h>
28#include <drm/drm_encoder.h>
29#include <drm/drm_eld.h>
30#include <drm/drm_file.h>
31#include <drm/drm_fourcc.h>
32#include <drm/drm_print.h>
33#include <drm/drm_probe_helper.h>
34
35#include "hda.h"
36#include "hdmi.h"
37#include "drm.h"
38#include "dc.h"
39#include "trace.h"
40
41#define HDMI_ELD_BUFFER_SIZE 96
42
43struct tmds_config {
44 unsigned int pclk;
45 u32 pll0;
46 u32 pll1;
47 u32 pe_current;
48 u32 drive_current;
49 u32 peak_current;
50};
51
52struct tegra_hdmi_config {
53 const struct tmds_config *tmds;
54 unsigned int num_tmds;
55
56 unsigned long fuse_override_offset;
57 u32 fuse_override_value;
58
59 bool has_sor_io_peak_current;
60 bool has_hda;
61 bool has_hbr;
62};
63
64struct tegra_hdmi {
65 struct host1x_client client;
66 struct tegra_output output;
67 struct device *dev;
68
69 struct regulator *hdmi;
70 struct regulator *pll;
71 struct regulator *vdd;
72
73 void __iomem *regs;
74 unsigned int irq;
75
76 struct clk *clk_parent;
77 struct clk *clk;
78 struct reset_control *rst;
79
80 const struct tegra_hdmi_config *config;
81
82 unsigned int audio_source;
83 struct tegra_hda_format format;
84
85 unsigned int pixel_clock;
86 bool stereo;
87 bool dvi;
88
89 struct drm_info_list *debugfs_files;
90
91 struct platform_device *audio_pdev;
92 struct mutex audio_lock;
93};
94
95static inline struct tegra_hdmi *
96host1x_client_to_hdmi(struct host1x_client *client)
97{
98 return container_of(client, struct tegra_hdmi, client);
99}
100
101static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
102{
103 return container_of(output, struct tegra_hdmi, output);
104}
105
106#define HDMI_AUDIOCLK_FREQ 216000000
107#define HDMI_REKEY_DEFAULT 56
108
109enum {
110 AUTO = 0,
111 SPDIF,
112 HDA,
113};
114
115static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
116 unsigned int offset)
117{
118 u32 value = readl(hdmi->regs + (offset << 2));
119
120 trace_hdmi_readl(hdmi->dev, offset, value);
121
122 return value;
123}
124
125static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
126 unsigned int offset)
127{
128 trace_hdmi_writel(hdmi->dev, offset, value);
129 writel(value, hdmi->regs + (offset << 2));
130}
131
132struct tegra_hdmi_audio_config {
133 unsigned int n;
134 unsigned int cts;
135 unsigned int aval;
136};
137
138static const struct tmds_config tegra20_tmds_config[] = {
139 { /* slow pixel clock modes */
140 .pclk = 27000000,
141 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
142 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
143 SOR_PLL_TX_REG_LOAD(3),
144 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
145 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
146 PE_CURRENT1(PE_CURRENT_0_0_mA) |
147 PE_CURRENT2(PE_CURRENT_0_0_mA) |
148 PE_CURRENT3(PE_CURRENT_0_0_mA),
149 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
150 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
151 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
152 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
153 },
154 { /* high pixel clock modes */
155 .pclk = UINT_MAX,
156 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
157 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
158 SOR_PLL_TX_REG_LOAD(3),
159 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
160 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
161 PE_CURRENT1(PE_CURRENT_6_0_mA) |
162 PE_CURRENT2(PE_CURRENT_6_0_mA) |
163 PE_CURRENT3(PE_CURRENT_6_0_mA),
164 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
165 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
166 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
167 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
168 },
169};
170
171static const struct tmds_config tegra30_tmds_config[] = {
172 { /* 480p modes */
173 .pclk = 27000000,
174 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
175 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
176 SOR_PLL_TX_REG_LOAD(0),
177 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
178 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
179 PE_CURRENT1(PE_CURRENT_0_0_mA) |
180 PE_CURRENT2(PE_CURRENT_0_0_mA) |
181 PE_CURRENT3(PE_CURRENT_0_0_mA),
182 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
183 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
184 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
185 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
186 }, { /* 720p modes */
187 .pclk = 74250000,
188 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
189 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
190 SOR_PLL_TX_REG_LOAD(0),
191 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
192 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
193 PE_CURRENT1(PE_CURRENT_5_0_mA) |
194 PE_CURRENT2(PE_CURRENT_5_0_mA) |
195 PE_CURRENT3(PE_CURRENT_5_0_mA),
196 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
197 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
198 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
199 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
200 }, { /* 1080p modes */
201 .pclk = UINT_MAX,
202 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
203 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
204 SOR_PLL_TX_REG_LOAD(0),
205 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
206 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
207 PE_CURRENT1(PE_CURRENT_5_0_mA) |
208 PE_CURRENT2(PE_CURRENT_5_0_mA) |
209 PE_CURRENT3(PE_CURRENT_5_0_mA),
210 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
211 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
212 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
213 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
214 },
215};
216
217static const struct tmds_config tegra114_tmds_config[] = {
218 { /* 480p/576p / 25.2MHz/27MHz modes */
219 .pclk = 27000000,
220 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
221 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
222 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
223 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
224 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
225 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
226 PE_CURRENT3(PE_CURRENT_0_mA_T114),
227 .drive_current =
228 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
229 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
230 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
231 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
232 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
233 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
234 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
235 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
236 }, { /* 720p / 74.25MHz modes */
237 .pclk = 74250000,
238 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
239 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
240 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
241 SOR_PLL_TMDS_TERMADJ(0),
242 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
243 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
244 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
245 PE_CURRENT3(PE_CURRENT_15_mA_T114),
246 .drive_current =
247 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
248 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
249 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
250 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
251 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
252 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
253 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
254 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
255 }, { /* 1080p / 148.5MHz modes */
256 .pclk = 148500000,
257 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
258 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
259 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
260 SOR_PLL_TMDS_TERMADJ(0),
261 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
262 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
263 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
264 PE_CURRENT3(PE_CURRENT_10_mA_T114),
265 .drive_current =
266 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
267 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
268 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
269 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
270 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
271 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
272 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
273 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
274 }, { /* 225/297MHz modes */
275 .pclk = UINT_MAX,
276 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
277 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
278 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
279 | SOR_PLL_TMDS_TERM_ENABLE,
280 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
281 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
282 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
283 PE_CURRENT3(PE_CURRENT_0_mA_T114),
284 .drive_current =
285 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
286 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
287 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
288 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
289 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
290 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
291 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
292 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
293 },
294};
295
296static const struct tmds_config tegra124_tmds_config[] = {
297 { /* 480p/576p / 25.2MHz/27MHz modes */
298 .pclk = 27000000,
299 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
300 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
301 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
302 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
303 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
304 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
305 PE_CURRENT3(PE_CURRENT_0_mA_T114),
306 .drive_current =
307 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
308 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
309 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
310 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
311 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
312 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
313 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
314 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
315 }, { /* 720p / 74.25MHz modes */
316 .pclk = 74250000,
317 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
318 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
319 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
320 SOR_PLL_TMDS_TERMADJ(0),
321 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
322 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
323 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
324 PE_CURRENT3(PE_CURRENT_15_mA_T114),
325 .drive_current =
326 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
327 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
328 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
329 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
330 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
331 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
332 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
333 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
334 }, { /* 1080p / 148.5MHz modes */
335 .pclk = 148500000,
336 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
337 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
338 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
339 SOR_PLL_TMDS_TERMADJ(0),
340 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
341 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
342 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
343 PE_CURRENT3(PE_CURRENT_10_mA_T114),
344 .drive_current =
345 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
346 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
347 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
348 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
349 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
350 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
351 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
352 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
353 }, { /* 225/297MHz modes */
354 .pclk = UINT_MAX,
355 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
356 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
357 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
358 | SOR_PLL_TMDS_TERM_ENABLE,
359 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
360 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
361 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
362 PE_CURRENT3(PE_CURRENT_0_mA_T114),
363 .drive_current =
364 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
365 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
366 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
367 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
368 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
369 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
370 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
371 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
372 },
373};
374
375static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
376 .destroy = drm_encoder_cleanup,
377};
378
379static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
380{
381 mutex_lock(&hdmi->audio_lock);
382 disable_irq(hdmi->irq);
383}
384
385static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
386{
387 enable_irq(hdmi->irq);
388 mutex_unlock(&hdmi->audio_lock);
389}
390
391static int
392tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
393 struct tegra_hdmi_audio_config *config)
394{
395 const unsigned int afreq = 128 * audio_freq;
396 const unsigned int min_n = afreq / 1500;
397 const unsigned int max_n = afreq / 300;
398 const unsigned int ideal_n = afreq / 1000;
399 int64_t min_err = (uint64_t)-1 >> 1;
400 unsigned int min_delta = -1;
401 int n;
402
403 memset(config, 0, sizeof(*config));
404 config->n = -1;
405
406 for (n = min_n; n <= max_n; n++) {
407 uint64_t cts_f, aval_f;
408 unsigned int delta;
409 int64_t cts, err;
410
411 /* compute aval in 48.16 fixed point */
412 aval_f = ((int64_t)24000000 << 16) * n;
413 do_div(aval_f, afreq);
414 /* It should round without any rest */
415 if (aval_f & 0xFFFF)
416 continue;
417
418 /* Compute cts in 48.16 fixed point */
419 cts_f = ((int64_t)pix_clock << 16) * n;
420 do_div(cts_f, afreq);
421 /* Round it to the nearest integer */
422 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
423
424 delta = abs(n - ideal_n);
425
426 /* Compute the absolute error */
427 err = abs((int64_t)cts_f - cts);
428 if (err < min_err || (err == min_err && delta < min_delta)) {
429 config->n = n;
430 config->cts = cts >> 16;
431 config->aval = aval_f >> 16;
432 min_delta = delta;
433 min_err = err;
434 }
435 }
436
437 return config->n != -1 ? 0 : -EINVAL;
438}
439
440static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
441{
442 static const unsigned int freqs[] = {
443 32000, 44100, 48000, 88200, 96000, 176400, 192000
444 };
445 unsigned int i;
446
447 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
448 unsigned int f = freqs[i];
449 unsigned int eight_half;
450 unsigned int delta;
451 u32 value;
452
453 if (f > 96000)
454 delta = 2;
455 else if (f > 48000)
456 delta = 6;
457 else
458 delta = 9;
459
460 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
461 value = AUDIO_FS_LOW(eight_half - delta) |
462 AUDIO_FS_HIGH(eight_half + delta);
463 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
464 }
465}
466
467static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
468{
469 static const struct {
470 unsigned int sample_rate;
471 unsigned int offset;
472 } regs[] = {
473 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
474 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
475 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
476 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
477 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
478 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
479 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
480 };
481 unsigned int i;
482
483 for (i = 0; i < ARRAY_SIZE(regs); i++) {
484 if (regs[i].sample_rate == hdmi->format.sample_rate) {
485 tegra_hdmi_writel(hdmi, value, regs[i].offset);
486 break;
487 }
488 }
489}
490
491static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
492{
493 struct tegra_hdmi_audio_config config;
494 u32 source, value;
495 int err;
496
497 switch (hdmi->audio_source) {
498 case HDA:
499 if (hdmi->config->has_hda)
500 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
501 else
502 return -EINVAL;
503
504 break;
505
506 case SPDIF:
507 if (hdmi->config->has_hda)
508 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
509 else
510 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
511 break;
512
513 default:
514 if (hdmi->config->has_hda)
515 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
516 else
517 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
518 break;
519 }
520
521 /*
522 * Tegra30 and later use a slightly modified version of the register
523 * layout to accomodate for changes related to supporting HDA as the
524 * audio input source for HDMI. The source select field has moved to
525 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
526 * per block fields remain in the AUDIO_CNTRL0 register.
527 */
528 if (hdmi->config->has_hda) {
529 /*
530 * Inject null samples into the audio FIFO for every frame in
531 * which the codec did not receive any samples. This applies
532 * to stereo LPCM only.
533 *
534 * XXX: This seems to be a remnant of MCP days when this was
535 * used to work around issues with monitors not being able to
536 * play back system startup sounds early. It is possibly not
537 * needed on Linux at all.
538 */
539 if (hdmi->format.channels == 2)
540 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
541 else
542 value = 0;
543
544 value |= source;
545
546 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
547 }
548
549 /*
550 * On Tegra20, HDA is not a supported audio source and the source
551 * select field is part of the AUDIO_CNTRL0 register.
552 */
553 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
554 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
555
556 if (!hdmi->config->has_hda)
557 value |= source;
558
559 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
560
561 /*
562 * Advertise support for High Bit-Rate on Tegra114 and later.
563 */
564 if (hdmi->config->has_hbr) {
565 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
566 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
567 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
568 }
569
570 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
571 hdmi->pixel_clock, &config);
572 if (err < 0) {
573 dev_err(hdmi->dev,
574 "cannot set audio to %u Hz at %u Hz pixel clock\n",
575 hdmi->format.sample_rate, hdmi->pixel_clock);
576 return err;
577 }
578
579 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
580 hdmi->pixel_clock, config.n, config.cts, config.aval);
581
582 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
583
584 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
585 AUDIO_N_VALUE(config.n - 1);
586 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
587
588 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
589 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
590
591 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
592 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
593
594 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
595 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
596
597 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
598 value &= ~AUDIO_N_RESETF;
599 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
600
601 if (hdmi->config->has_hda)
602 tegra_hdmi_write_aval(hdmi, config.aval);
603
604 tegra_hdmi_setup_audio_fs_tables(hdmi);
605
606 return 0;
607}
608
609static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
610{
611 u32 value;
612
613 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
614 value &= ~GENERIC_CTRL_AUDIO;
615 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
616}
617
618static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
619{
620 u32 value;
621
622 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
623 value |= GENERIC_CTRL_AUDIO;
624 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
625}
626
627static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
628{
629 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
630 u32 value;
631
632 for (i = 0; i < length; i++)
633 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
634 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
635
636 /*
637 * The HDA codec will always report an ELD buffer size of 96 bytes and
638 * the HDA codec driver will check that each byte read from the buffer
639 * is valid. Therefore every byte must be written, even if no 96 bytes
640 * were parsed from EDID.
641 */
642 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
643 tegra_hdmi_writel(hdmi, i << 8 | 0,
644 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
645
646 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
647 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
648}
649
650static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
651{
652 u32 value = 0;
653 size_t i;
654
655 for (i = size; i > 0; i--)
656 value = (value << 8) | ptr[i - 1];
657
658 return value;
659}
660
661static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
662 size_t size)
663{
664 const u8 *ptr = data;
665 unsigned long offset;
666 size_t i;
667 u32 value;
668
669 switch (ptr[0]) {
670 case HDMI_INFOFRAME_TYPE_AVI:
671 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
672 break;
673
674 case HDMI_INFOFRAME_TYPE_AUDIO:
675 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
676 break;
677
678 case HDMI_INFOFRAME_TYPE_VENDOR:
679 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
680 break;
681
682 default:
683 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
684 ptr[0]);
685 return;
686 }
687
688 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
689 INFOFRAME_HEADER_VERSION(ptr[1]) |
690 INFOFRAME_HEADER_LEN(ptr[2]);
691 tegra_hdmi_writel(hdmi, value, offset);
692 offset++;
693
694 /*
695 * Each subpack contains 7 bytes, divided into:
696 * - subpack_low: bytes 0 - 3
697 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
698 */
699 for (i = 3; i < size; i += 7) {
700 size_t rem = size - i, num = min_t(size_t, rem, 4);
701
702 value = tegra_hdmi_subpack(&ptr[i], num);
703 tegra_hdmi_writel(hdmi, value, offset++);
704
705 num = min_t(size_t, rem - num, 3);
706
707 value = tegra_hdmi_subpack(&ptr[i + 4], num);
708 tegra_hdmi_writel(hdmi, value, offset++);
709 }
710}
711
712static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
713 struct drm_display_mode *mode)
714{
715 struct hdmi_avi_infoframe frame;
716 u8 buffer[17];
717 ssize_t err;
718
719 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
720 &hdmi->output.connector, mode);
721 if (err < 0) {
722 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
723 return;
724 }
725
726 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
727 if (err < 0) {
728 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
729 return;
730 }
731
732 tegra_hdmi_write_infopack(hdmi, buffer, err);
733}
734
735static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
736{
737 u32 value;
738
739 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
740 value &= ~INFOFRAME_CTRL_ENABLE;
741 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
742}
743
744static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
745{
746 u32 value;
747
748 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
749 value |= INFOFRAME_CTRL_ENABLE;
750 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
751}
752
753static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
754{
755 struct hdmi_audio_infoframe frame;
756 u8 buffer[14];
757 ssize_t err;
758
759 err = hdmi_audio_infoframe_init(&frame);
760 if (err < 0) {
761 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
762 err);
763 return;
764 }
765
766 frame.channels = hdmi->format.channels;
767
768 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
769 if (err < 0) {
770 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
771 err);
772 return;
773 }
774
775 /*
776 * The audio infoframe has only one set of subpack registers, so the
777 * infoframe needs to be truncated. One set of subpack registers can
778 * contain 7 bytes. Including the 3 byte header only the first 10
779 * bytes can be programmed.
780 */
781 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
782}
783
784static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
785{
786 u32 value;
787
788 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
789 value &= ~INFOFRAME_CTRL_ENABLE;
790 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
791}
792
793static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
794{
795 u32 value;
796
797 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
798 value |= INFOFRAME_CTRL_ENABLE;
799 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
800}
801
802static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
803{
804 struct hdmi_vendor_infoframe frame;
805 u8 buffer[10];
806 ssize_t err;
807
808 hdmi_vendor_infoframe_init(&frame);
809 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
810
811 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
812 if (err < 0) {
813 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
814 err);
815 return;
816 }
817
818 tegra_hdmi_write_infopack(hdmi, buffer, err);
819}
820
821static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
822{
823 u32 value;
824
825 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
826 value &= ~GENERIC_CTRL_ENABLE;
827 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
828}
829
830static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
831{
832 u32 value;
833
834 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
835 value |= GENERIC_CTRL_ENABLE;
836 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
837}
838
839static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
840 const struct tmds_config *tmds)
841{
842 u32 value;
843
844 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
845 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
846 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
847
848 tegra_hdmi_writel(hdmi, tmds->drive_current,
849 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
850
851 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
852 value |= hdmi->config->fuse_override_value;
853 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
854
855 if (hdmi->config->has_sor_io_peak_current)
856 tegra_hdmi_writel(hdmi, tmds->peak_current,
857 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
858}
859
860static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
861{
862 int err;
863
864 err = tegra_hdmi_setup_audio(hdmi);
865 if (err < 0) {
866 tegra_hdmi_disable_audio_infoframe(hdmi);
867 tegra_hdmi_disable_audio(hdmi);
868 } else {
869 tegra_hdmi_setup_audio_infoframe(hdmi);
870 tegra_hdmi_enable_audio_infoframe(hdmi);
871 tegra_hdmi_enable_audio(hdmi);
872 }
873
874 return err;
875}
876
877static bool tegra_output_is_hdmi(struct tegra_output *output)
878{
879 return output->connector.display_info.is_hdmi;
880}
881
882static enum drm_connector_status
883tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
884{
885 struct tegra_output *output = connector_to_output(connector);
886 struct tegra_hdmi *hdmi = to_hdmi(output);
887 enum drm_connector_status status;
888
889 status = tegra_output_connector_detect(connector, force);
890 if (status == connector_status_connected)
891 return status;
892
893 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
894 return status;
895}
896
897#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
898
899static const struct debugfs_reg32 tegra_hdmi_regs[] = {
900 DEBUGFS_REG32(HDMI_CTXSW),
901 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
902 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
903 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
904 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
905 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
906 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
907 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
908 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
909 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
910 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
911 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
912 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
913 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
914 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
915 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
916 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
917 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
918 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
919 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
920 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
921 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
922 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
923 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
924 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
925 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
945 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
946 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
947 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
948 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
949 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
950 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
951 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
952 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
953 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
954 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
955 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
956 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
957 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
958 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
959 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
960 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
961 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
962 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
963 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
964 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
965 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
966 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
967 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
968 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
969 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
970 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
971 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
972 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
973 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
974 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
975 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
976 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
977 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
978 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
979 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
980 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
981 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
982 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
983 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
984 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
985 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
986 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
987 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
988 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
989 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
990 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
991 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
992 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
993 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
994 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
995 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
996 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
997 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
998 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
1000 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
1002 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
1003 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
1004 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
1005 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1006 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1007 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1008 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1009 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1010 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1018 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1019 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1020 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1021 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1022 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1023 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1024 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1025 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1026 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1027 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1028 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1029 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1030 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1031 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1032 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1033 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1034 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1035 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1036 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1037 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1038 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1039 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1040 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1041 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1042 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1043 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1044 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1045 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1046 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1047 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1048 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1049 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1050 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1051 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1052 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1053 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1054 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1055 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1056 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1057 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1058 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1059 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1060 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1061 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1062 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1063 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1064};
1065
1066static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1067{
1068 struct drm_info_node *node = s->private;
1069 struct tegra_hdmi *hdmi = node->info_ent->data;
1070 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1071 struct drm_device *drm = node->minor->dev;
1072 unsigned int i;
1073 int err = 0;
1074
1075 drm_modeset_lock_all(drm);
1076
1077 if (!crtc || !crtc->state->active) {
1078 err = -EBUSY;
1079 goto unlock;
1080 }
1081
1082 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1083 unsigned int offset = tegra_hdmi_regs[i].offset;
1084
1085 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1086 offset, tegra_hdmi_readl(hdmi, offset));
1087 }
1088
1089unlock:
1090 drm_modeset_unlock_all(drm);
1091 return err;
1092}
1093
1094static struct drm_info_list debugfs_files[] = {
1095 { "regs", tegra_hdmi_show_regs, 0, NULL },
1096};
1097
1098static int tegra_hdmi_late_register(struct drm_connector *connector)
1099{
1100 struct tegra_output *output = connector_to_output(connector);
1101 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1102 struct drm_minor *minor = connector->dev->primary;
1103 struct dentry *root = connector->debugfs_entry;
1104 struct tegra_hdmi *hdmi = to_hdmi(output);
1105
1106 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1107 GFP_KERNEL);
1108 if (!hdmi->debugfs_files)
1109 return -ENOMEM;
1110
1111 for (i = 0; i < count; i++)
1112 hdmi->debugfs_files[i].data = hdmi;
1113
1114 drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1115
1116 return 0;
1117}
1118
1119static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1120{
1121 struct tegra_output *output = connector_to_output(connector);
1122 struct drm_minor *minor = connector->dev->primary;
1123 unsigned int count = ARRAY_SIZE(debugfs_files);
1124 struct tegra_hdmi *hdmi = to_hdmi(output);
1125
1126 drm_debugfs_remove_files(hdmi->debugfs_files, count,
1127 connector->debugfs_entry, minor);
1128 kfree(hdmi->debugfs_files);
1129 hdmi->debugfs_files = NULL;
1130}
1131
1132static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1133 .reset = drm_atomic_helper_connector_reset,
1134 .detect = tegra_hdmi_connector_detect,
1135 .fill_modes = drm_helper_probe_single_connector_modes,
1136 .destroy = tegra_output_connector_destroy,
1137 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1138 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1139 .late_register = tegra_hdmi_late_register,
1140 .early_unregister = tegra_hdmi_early_unregister,
1141};
1142
1143static enum drm_mode_status
1144tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1145 const struct drm_display_mode *mode)
1146{
1147 struct tegra_output *output = connector_to_output(connector);
1148 struct tegra_hdmi *hdmi = to_hdmi(output);
1149 unsigned long pclk = mode->clock * 1000;
1150 enum drm_mode_status status = MODE_OK;
1151 struct clk *parent;
1152 long err;
1153
1154 parent = clk_get_parent(hdmi->clk_parent);
1155
1156 err = clk_round_rate(parent, pclk * 4);
1157 if (err <= 0)
1158 status = MODE_NOCLOCK;
1159
1160 return status;
1161}
1162
1163static const struct drm_connector_helper_funcs
1164tegra_hdmi_connector_helper_funcs = {
1165 .get_modes = tegra_output_connector_get_modes,
1166 .mode_valid = tegra_hdmi_connector_mode_valid,
1167};
1168
1169static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1170{
1171 struct tegra_output *output = encoder_to_output(encoder);
1172 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1173 struct tegra_hdmi *hdmi = to_hdmi(output);
1174 u32 value;
1175 int err;
1176
1177 tegra_hdmi_audio_lock(hdmi);
1178
1179 /*
1180 * The following accesses registers of the display controller, so make
1181 * sure it's only executed when the output is attached to one.
1182 */
1183 if (dc) {
1184 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1185 value &= ~HDMI_ENABLE;
1186 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1187
1188 tegra_dc_commit(dc);
1189 }
1190
1191 if (!hdmi->dvi) {
1192 if (hdmi->stereo)
1193 tegra_hdmi_disable_stereo_infoframe(hdmi);
1194
1195 tegra_hdmi_disable_audio_infoframe(hdmi);
1196 tegra_hdmi_disable_avi_infoframe(hdmi);
1197 tegra_hdmi_disable_audio(hdmi);
1198 }
1199
1200 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1201 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1202
1203 hdmi->pixel_clock = 0;
1204
1205 tegra_hdmi_audio_unlock(hdmi);
1206
1207 err = host1x_client_suspend(&hdmi->client);
1208 if (err < 0)
1209 dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1210}
1211
1212static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1213{
1214 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1215 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1216 struct tegra_output *output = encoder_to_output(encoder);
1217 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1218 struct tegra_hdmi *hdmi = to_hdmi(output);
1219 unsigned int pulse_start, div82;
1220 int retries = 1000;
1221 u32 value;
1222 int err;
1223
1224 err = host1x_client_resume(&hdmi->client);
1225 if (err < 0) {
1226 dev_err(hdmi->dev, "failed to resume: %d\n", err);
1227 return;
1228 }
1229
1230 tegra_hdmi_audio_lock(hdmi);
1231
1232 /*
1233 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1234 * is used for interoperability between the HDA codec driver and the
1235 * HDMI driver.
1236 */
1237 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1238 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1239
1240 hdmi->pixel_clock = mode->clock * 1000;
1241 h_sync_width = mode->hsync_end - mode->hsync_start;
1242 h_back_porch = mode->htotal - mode->hsync_end;
1243 h_front_porch = mode->hsync_start - mode->hdisplay;
1244
1245 err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1246 if (err < 0) {
1247 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1248 err);
1249 }
1250
1251 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1252
1253 /* power up sequence */
1254 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1255 value &= ~SOR_PLL_PDBG;
1256 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1257
1258 usleep_range(10, 20);
1259
1260 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1261 value &= ~SOR_PLL_PWR;
1262 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1263
1264 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1265 DC_DISP_DISP_TIMING_OPTIONS);
1266 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1267 DC_DISP_DISP_COLOR_CONTROL);
1268
1269 /* video_preamble uses h_pulse2 */
1270 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1271
1272 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1273
1274 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1275 PULSE_LAST_END_A;
1276 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1277
1278 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1279 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1280
1281 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1282 VSYNC_WINDOW_ENABLE;
1283 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1284
1285 if (dc->pipe)
1286 value = HDMI_SRC_DISPLAYB;
1287 else
1288 value = HDMI_SRC_DISPLAYA;
1289
1290 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1291 (mode->vdisplay == 576)))
1292 tegra_hdmi_writel(hdmi,
1293 value | ARM_VIDEO_RANGE_FULL,
1294 HDMI_NV_PDISP_INPUT_CONTROL);
1295 else
1296 tegra_hdmi_writel(hdmi,
1297 value | ARM_VIDEO_RANGE_LIMITED,
1298 HDMI_NV_PDISP_INPUT_CONTROL);
1299
1300 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1301 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1302 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1303
1304 hdmi->dvi = !tegra_output_is_hdmi(output);
1305 if (!hdmi->dvi) {
1306 /*
1307 * Make sure that the audio format has been configured before
1308 * enabling audio, otherwise we may try to divide by zero.
1309 */
1310 if (hdmi->format.sample_rate > 0) {
1311 err = tegra_hdmi_setup_audio(hdmi);
1312 if (err < 0)
1313 hdmi->dvi = true;
1314 }
1315 }
1316
1317 if (hdmi->config->has_hda)
1318 tegra_hdmi_write_eld(hdmi);
1319
1320 rekey = HDMI_REKEY_DEFAULT;
1321 value = HDMI_CTRL_REKEY(rekey);
1322 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1323 h_front_porch - rekey - 18) / 32);
1324
1325 if (!hdmi->dvi)
1326 value |= HDMI_CTRL_ENABLE;
1327
1328 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1329
1330 if (!hdmi->dvi) {
1331 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1332 tegra_hdmi_setup_audio_infoframe(hdmi);
1333
1334 if (hdmi->stereo)
1335 tegra_hdmi_setup_stereo_infoframe(hdmi);
1336 }
1337
1338 /* TMDS CONFIG */
1339 for (i = 0; i < hdmi->config->num_tmds; i++) {
1340 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1341 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1342 break;
1343 }
1344 }
1345
1346 tegra_hdmi_writel(hdmi,
1347 SOR_SEQ_PU_PC(0) |
1348 SOR_SEQ_PU_PC_ALT(0) |
1349 SOR_SEQ_PD_PC(8) |
1350 SOR_SEQ_PD_PC_ALT(8),
1351 HDMI_NV_PDISP_SOR_SEQ_CTL);
1352
1353 value = SOR_SEQ_INST_WAIT_TIME(1) |
1354 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1355 SOR_SEQ_INST_HALT |
1356 SOR_SEQ_INST_PIN_A_LOW |
1357 SOR_SEQ_INST_PIN_B_LOW |
1358 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1359
1360 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1361 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1362
1363 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1364 value &= ~SOR_CSTM_ROTCLK(~0);
1365 value |= SOR_CSTM_ROTCLK(2);
1366 value |= SOR_CSTM_PLLDIV;
1367 value &= ~SOR_CSTM_LVDS_ENABLE;
1368 value &= ~SOR_CSTM_MODE_MASK;
1369 value |= SOR_CSTM_MODE_TMDS;
1370 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1371
1372 /* start SOR */
1373 tegra_hdmi_writel(hdmi,
1374 SOR_PWR_NORMAL_STATE_PU |
1375 SOR_PWR_NORMAL_START_NORMAL |
1376 SOR_PWR_SAFE_STATE_PD |
1377 SOR_PWR_SETTING_NEW_TRIGGER,
1378 HDMI_NV_PDISP_SOR_PWR);
1379 tegra_hdmi_writel(hdmi,
1380 SOR_PWR_NORMAL_STATE_PU |
1381 SOR_PWR_NORMAL_START_NORMAL |
1382 SOR_PWR_SAFE_STATE_PD |
1383 SOR_PWR_SETTING_NEW_DONE,
1384 HDMI_NV_PDISP_SOR_PWR);
1385
1386 do {
1387 BUG_ON(--retries < 0);
1388 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1389 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1390
1391 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1392 SOR_STATE_ASY_OWNER_HEAD0 |
1393 SOR_STATE_ASY_SUBOWNER_BOTH |
1394 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1395 SOR_STATE_ASY_DEPOL_POS;
1396
1397 /* setup sync polarities */
1398 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1399 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1400
1401 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1402 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1403
1404 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1405 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1406
1407 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1408 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1409
1410 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1411
1412 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1413 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1414
1415 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1416 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1417 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1418 HDMI_NV_PDISP_SOR_STATE1);
1419 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1420
1421 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1422 value |= HDMI_ENABLE;
1423 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1424
1425 tegra_dc_commit(dc);
1426
1427 if (!hdmi->dvi) {
1428 tegra_hdmi_enable_avi_infoframe(hdmi);
1429 tegra_hdmi_enable_audio_infoframe(hdmi);
1430 tegra_hdmi_enable_audio(hdmi);
1431
1432 if (hdmi->stereo)
1433 tegra_hdmi_enable_stereo_infoframe(hdmi);
1434 }
1435
1436 /* TODO: add HDCP support */
1437
1438 tegra_hdmi_audio_unlock(hdmi);
1439}
1440
1441static int
1442tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1443 struct drm_crtc_state *crtc_state,
1444 struct drm_connector_state *conn_state)
1445{
1446 struct tegra_output *output = encoder_to_output(encoder);
1447 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1448 unsigned long pclk = crtc_state->mode.clock * 1000;
1449 struct tegra_hdmi *hdmi = to_hdmi(output);
1450 int err;
1451
1452 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1453 pclk, 0);
1454 if (err < 0) {
1455 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1456 return err;
1457 }
1458
1459 return err;
1460}
1461
1462static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1463 .disable = tegra_hdmi_encoder_disable,
1464 .enable = tegra_hdmi_encoder_enable,
1465 .atomic_check = tegra_hdmi_encoder_atomic_check,
1466};
1467
1468static int tegra_hdmi_hw_params(struct device *dev, void *data,
1469 struct hdmi_codec_daifmt *fmt,
1470 struct hdmi_codec_params *hparms)
1471{
1472 struct tegra_hdmi *hdmi = data;
1473 int ret = 0;
1474
1475 tegra_hdmi_audio_lock(hdmi);
1476
1477 hdmi->format.sample_rate = hparms->sample_rate;
1478 hdmi->format.channels = hparms->channels;
1479
1480 if (hdmi->pixel_clock && !hdmi->dvi)
1481 ret = tegra_hdmi_reconfigure_audio(hdmi);
1482
1483 tegra_hdmi_audio_unlock(hdmi);
1484
1485 return ret;
1486}
1487
1488static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1489{
1490 struct tegra_hdmi *hdmi = data;
1491 int ret;
1492
1493 ret = host1x_client_resume(&hdmi->client);
1494 if (ret < 0)
1495 dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1496
1497 return ret;
1498}
1499
1500static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1501{
1502 struct tegra_hdmi *hdmi = data;
1503 int ret;
1504
1505 tegra_hdmi_audio_lock(hdmi);
1506
1507 hdmi->format.sample_rate = 0;
1508 hdmi->format.channels = 0;
1509
1510 tegra_hdmi_audio_unlock(hdmi);
1511
1512 ret = host1x_client_suspend(&hdmi->client);
1513 if (ret < 0)
1514 dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1515}
1516
1517static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1518 .hw_params = tegra_hdmi_hw_params,
1519 .audio_startup = tegra_hdmi_audio_startup,
1520 .audio_shutdown = tegra_hdmi_audio_shutdown,
1521};
1522
1523static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1524{
1525 struct hdmi_codec_pdata codec_data = {};
1526
1527 if (hdmi->config->has_hda)
1528 return 0;
1529
1530 codec_data.ops = &tegra_hdmi_codec_ops;
1531 codec_data.data = hdmi;
1532 codec_data.spdif = 1;
1533
1534 hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1535 HDMI_CODEC_DRV_NAME,
1536 PLATFORM_DEVID_AUTO,
1537 &codec_data,
1538 sizeof(codec_data));
1539 if (IS_ERR(hdmi->audio_pdev))
1540 return PTR_ERR(hdmi->audio_pdev);
1541
1542 hdmi->format.channels = 2;
1543
1544 return 0;
1545}
1546
1547static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1548{
1549 if (hdmi->audio_pdev)
1550 platform_device_unregister(hdmi->audio_pdev);
1551}
1552
1553static int tegra_hdmi_init(struct host1x_client *client)
1554{
1555 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1556 struct drm_device *drm = dev_get_drvdata(client->host);
1557 struct drm_connector *connector;
1558 int err;
1559
1560 hdmi->output.dev = client->dev;
1561
1562 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1563 DRM_MODE_ENCODER_TMDS, NULL);
1564 drm_encoder_helper_add(&hdmi->output.encoder,
1565 &tegra_hdmi_encoder_helper_funcs);
1566
1567 if (hdmi->output.bridge) {
1568 err = drm_bridge_attach(&hdmi->output.encoder, hdmi->output.bridge,
1569 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1570 if (err) {
1571 dev_err(client->dev, "failed to attach bridge: %d\n",
1572 err);
1573 return err;
1574 }
1575
1576 connector = drm_bridge_connector_init(drm, &hdmi->output.encoder);
1577 if (IS_ERR(connector)) {
1578 dev_err(client->dev,
1579 "failed to initialize bridge connector: %pe\n",
1580 connector);
1581 return PTR_ERR(connector);
1582 }
1583 } else {
1584 drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1585 &tegra_hdmi_connector_funcs,
1586 DRM_MODE_CONNECTOR_HDMIA,
1587 hdmi->output.ddc);
1588 drm_connector_helper_add(&hdmi->output.connector,
1589 &tegra_hdmi_connector_helper_funcs);
1590 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1591
1592 drm_connector_attach_encoder(&hdmi->output.connector,
1593 &hdmi->output.encoder);
1594 drm_connector_register(&hdmi->output.connector);
1595 }
1596
1597 err = tegra_output_init(drm, &hdmi->output);
1598 if (err < 0) {
1599 dev_err(client->dev, "failed to initialize output: %d\n", err);
1600 return err;
1601 }
1602
1603 hdmi->output.encoder.possible_crtcs = 0x3;
1604
1605 err = regulator_enable(hdmi->hdmi);
1606 if (err < 0) {
1607 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1608 err);
1609 goto output_exit;
1610 }
1611
1612 err = regulator_enable(hdmi->pll);
1613 if (err < 0) {
1614 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1615 goto disable_hdmi;
1616 }
1617
1618 err = regulator_enable(hdmi->vdd);
1619 if (err < 0) {
1620 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1621 goto disable_pll;
1622 }
1623
1624 err = tegra_hdmi_codec_register(hdmi);
1625 if (err < 0) {
1626 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1627 goto disable_vdd;
1628 }
1629
1630 return 0;
1631
1632disable_vdd:
1633 regulator_disable(hdmi->vdd);
1634disable_pll:
1635 regulator_disable(hdmi->pll);
1636disable_hdmi:
1637 regulator_disable(hdmi->hdmi);
1638output_exit:
1639 tegra_output_exit(&hdmi->output);
1640
1641 return err;
1642}
1643
1644static int tegra_hdmi_exit(struct host1x_client *client)
1645{
1646 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1647
1648 tegra_hdmi_codec_unregister(hdmi);
1649
1650 tegra_output_exit(&hdmi->output);
1651
1652 regulator_disable(hdmi->vdd);
1653 regulator_disable(hdmi->pll);
1654 regulator_disable(hdmi->hdmi);
1655
1656 return 0;
1657}
1658
1659static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1660{
1661 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1662 struct device *dev = client->dev;
1663 int err;
1664
1665 err = reset_control_assert(hdmi->rst);
1666 if (err < 0) {
1667 dev_err(dev, "failed to assert reset: %d\n", err);
1668 return err;
1669 }
1670
1671 usleep_range(1000, 2000);
1672
1673 clk_disable_unprepare(hdmi->clk);
1674 pm_runtime_put_sync(dev);
1675
1676 return 0;
1677}
1678
1679static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1680{
1681 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1682 struct device *dev = client->dev;
1683 int err;
1684
1685 err = pm_runtime_resume_and_get(dev);
1686 if (err < 0) {
1687 dev_err(dev, "failed to get runtime PM: %d\n", err);
1688 return err;
1689 }
1690
1691 err = clk_prepare_enable(hdmi->clk);
1692 if (err < 0) {
1693 dev_err(dev, "failed to enable clock: %d\n", err);
1694 goto put_rpm;
1695 }
1696
1697 usleep_range(1000, 2000);
1698
1699 err = reset_control_deassert(hdmi->rst);
1700 if (err < 0) {
1701 dev_err(dev, "failed to deassert reset: %d\n", err);
1702 goto disable_clk;
1703 }
1704
1705 return 0;
1706
1707disable_clk:
1708 clk_disable_unprepare(hdmi->clk);
1709put_rpm:
1710 pm_runtime_put_sync(dev);
1711 return err;
1712}
1713
1714static const struct host1x_client_ops hdmi_client_ops = {
1715 .init = tegra_hdmi_init,
1716 .exit = tegra_hdmi_exit,
1717 .suspend = tegra_hdmi_runtime_suspend,
1718 .resume = tegra_hdmi_runtime_resume,
1719};
1720
1721static const struct tegra_hdmi_config tegra20_hdmi_config = {
1722 .tmds = tegra20_tmds_config,
1723 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1724 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1725 .fuse_override_value = 1 << 31,
1726 .has_sor_io_peak_current = false,
1727 .has_hda = false,
1728 .has_hbr = false,
1729};
1730
1731static const struct tegra_hdmi_config tegra30_hdmi_config = {
1732 .tmds = tegra30_tmds_config,
1733 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1734 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1735 .fuse_override_value = 1 << 31,
1736 .has_sor_io_peak_current = false,
1737 .has_hda = true,
1738 .has_hbr = false,
1739};
1740
1741static const struct tegra_hdmi_config tegra114_hdmi_config = {
1742 .tmds = tegra114_tmds_config,
1743 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1744 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1745 .fuse_override_value = 1 << 31,
1746 .has_sor_io_peak_current = true,
1747 .has_hda = true,
1748 .has_hbr = true,
1749};
1750
1751static const struct tegra_hdmi_config tegra124_hdmi_config = {
1752 .tmds = tegra124_tmds_config,
1753 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1754 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1755 .fuse_override_value = 1 << 31,
1756 .has_sor_io_peak_current = true,
1757 .has_hda = true,
1758 .has_hbr = true,
1759};
1760
1761static const struct of_device_id tegra_hdmi_of_match[] = {
1762 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1763 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1764 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1765 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1766 { },
1767};
1768MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1769
1770static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1771{
1772 struct tegra_hdmi *hdmi = data;
1773 u32 value;
1774
1775 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1776 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1777
1778 if (value & INT_CODEC_SCRATCH0) {
1779 unsigned int format;
1780 u32 value;
1781
1782 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1783
1784 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1785 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1786
1787 tegra_hda_parse_format(format, &hdmi->format);
1788 tegra_hdmi_reconfigure_audio(hdmi);
1789 } else {
1790 tegra_hdmi_disable_audio_infoframe(hdmi);
1791 tegra_hdmi_disable_audio(hdmi);
1792 }
1793 }
1794
1795 return IRQ_HANDLED;
1796}
1797
1798static int tegra_hdmi_probe(struct platform_device *pdev)
1799{
1800 struct tegra_hdmi *hdmi;
1801 int err;
1802
1803 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1804 if (!hdmi)
1805 return -ENOMEM;
1806
1807 hdmi->config = of_device_get_match_data(&pdev->dev);
1808 hdmi->dev = &pdev->dev;
1809
1810 hdmi->audio_source = AUTO;
1811 hdmi->stereo = false;
1812 hdmi->dvi = false;
1813
1814 mutex_init(&hdmi->audio_lock);
1815
1816 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1817 if (IS_ERR(hdmi->clk)) {
1818 dev_err(&pdev->dev, "failed to get clock\n");
1819 return PTR_ERR(hdmi->clk);
1820 }
1821
1822 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1823 if (IS_ERR(hdmi->rst)) {
1824 dev_err(&pdev->dev, "failed to get reset\n");
1825 return PTR_ERR(hdmi->rst);
1826 }
1827
1828 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1829 if (IS_ERR(hdmi->clk_parent))
1830 return PTR_ERR(hdmi->clk_parent);
1831
1832 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1833 if (err < 0) {
1834 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1835 return err;
1836 }
1837
1838 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1839 err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1840 if (err)
1841 return dev_err_probe(&pdev->dev, err,
1842 "failed to get HDMI regulator\n");
1843
1844 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1845 err = PTR_ERR_OR_ZERO(hdmi->pll);
1846 if (err)
1847 return dev_err_probe(&pdev->dev, err,
1848 "failed to get PLL regulator\n");
1849
1850 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1851 err = PTR_ERR_OR_ZERO(hdmi->vdd);
1852 if (err)
1853 return dev_err_probe(&pdev->dev, err,
1854 "failed to get VDD regulator\n");
1855
1856 hdmi->output.dev = &pdev->dev;
1857
1858 err = tegra_output_probe(&hdmi->output);
1859 if (err < 0)
1860 return err;
1861
1862 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
1863 if (IS_ERR(hdmi->regs)) {
1864 err = PTR_ERR(hdmi->regs);
1865 goto remove;
1866 }
1867
1868 err = platform_get_irq(pdev, 0);
1869 if (err < 0)
1870 goto remove;
1871
1872 hdmi->irq = err;
1873
1874 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1875 dev_name(hdmi->dev), hdmi);
1876 if (err < 0) {
1877 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1878 hdmi->irq, err);
1879 goto remove;
1880 }
1881
1882 platform_set_drvdata(pdev, hdmi);
1883
1884 err = devm_pm_runtime_enable(&pdev->dev);
1885 if (err)
1886 goto remove;
1887
1888 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1889 if (err)
1890 goto remove;
1891
1892 INIT_LIST_HEAD(&hdmi->client.list);
1893 hdmi->client.ops = &hdmi_client_ops;
1894 hdmi->client.dev = &pdev->dev;
1895
1896 err = host1x_client_register(&hdmi->client);
1897 if (err < 0) {
1898 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1899 err);
1900 goto remove;
1901 }
1902
1903 return 0;
1904
1905remove:
1906 tegra_output_remove(&hdmi->output);
1907 return err;
1908}
1909
1910static void tegra_hdmi_remove(struct platform_device *pdev)
1911{
1912 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1913
1914 host1x_client_unregister(&hdmi->client);
1915
1916 tegra_output_remove(&hdmi->output);
1917}
1918
1919struct platform_driver tegra_hdmi_driver = {
1920 .driver = {
1921 .name = "tegra-hdmi",
1922 .of_match_table = tegra_hdmi_of_match,
1923 },
1924 .probe = tegra_hdmi_probe,
1925 .remove = tegra_hdmi_remove,
1926};