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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015-2022, NVIDIA Corporation.
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/dma-mapping.h>
9#include <linux/host1x.h>
10#include <linux/iommu.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/reset.h>
17
18#include <soc/tegra/mc.h>
19
20#include "drm.h"
21#include "falcon.h"
22#include "riscv.h"
23#include "vic.h"
24
25#define NVDEC_FALCON_DEBUGINFO 0x1094
26#define NVDEC_TFBIF_TRANSCFG 0x2c44
27
28struct nvdec_config {
29 const char *firmware;
30 unsigned int version;
31 bool supports_sid;
32 bool has_riscv;
33 bool has_extra_clocks;
34};
35
36struct nvdec {
37 struct falcon falcon;
38
39 void __iomem *regs;
40 struct tegra_drm_client client;
41 struct host1x_channel *channel;
42 struct device *dev;
43 struct clk_bulk_data clks[3];
44 unsigned int num_clks;
45 struct reset_control *reset;
46
47 /* Platform configuration */
48 const struct nvdec_config *config;
49
50 /* RISC-V specific data */
51 struct tegra_drm_riscv riscv;
52 phys_addr_t carveout_base;
53};
54
55static inline struct nvdec *to_nvdec(struct tegra_drm_client *client)
56{
57 return container_of(client, struct nvdec, client);
58}
59
60static inline void nvdec_writel(struct nvdec *nvdec, u32 value,
61 unsigned int offset)
62{
63 writel(value, nvdec->regs + offset);
64}
65
66static int nvdec_boot_falcon(struct nvdec *nvdec)
67{
68 u32 stream_id;
69 int err;
70
71 if (nvdec->config->supports_sid && tegra_dev_iommu_get_stream_id(nvdec->dev, &stream_id)) {
72 u32 value;
73
74 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
75 nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
76
77 nvdec_writel(nvdec, stream_id, VIC_THI_STREAMID0);
78 nvdec_writel(nvdec, stream_id, VIC_THI_STREAMID1);
79 }
80
81 err = falcon_boot(&nvdec->falcon);
82 if (err < 0)
83 return err;
84
85 err = falcon_wait_idle(&nvdec->falcon);
86 if (err < 0) {
87 dev_err(nvdec->dev, "falcon boot timed out\n");
88 return err;
89 }
90
91 return 0;
92}
93
94static int nvdec_wait_debuginfo(struct nvdec *nvdec, const char *phase)
95{
96 int err;
97 u32 val;
98
99 err = readl_poll_timeout(nvdec->regs + NVDEC_FALCON_DEBUGINFO, val, val == 0x0, 10, 100000);
100 if (err) {
101 dev_err(nvdec->dev, "failed to boot %s, debuginfo=0x%x\n", phase, val);
102 return err;
103 }
104
105 return 0;
106}
107
108static int nvdec_boot_riscv(struct nvdec *nvdec)
109{
110 int err;
111
112 err = reset_control_acquire(nvdec->reset);
113 if (err)
114 return err;
115
116 nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);
117
118 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
119 &nvdec->riscv.bl_desc);
120 if (err) {
121 dev_err(nvdec->dev, "failed to execute bootloader\n");
122 goto release_reset;
123 }
124
125 err = nvdec_wait_debuginfo(nvdec, "bootloader");
126 if (err)
127 goto release_reset;
128
129 err = reset_control_reset(nvdec->reset);
130 if (err)
131 goto release_reset;
132
133 nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);
134
135 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
136 &nvdec->riscv.os_desc);
137 if (err) {
138 dev_err(nvdec->dev, "failed to execute firmware\n");
139 goto release_reset;
140 }
141
142 err = nvdec_wait_debuginfo(nvdec, "firmware");
143 if (err)
144 goto release_reset;
145
146release_reset:
147 reset_control_release(nvdec->reset);
148
149 return err;
150}
151
152static int nvdec_init(struct host1x_client *client)
153{
154 struct tegra_drm_client *drm = host1x_to_drm_client(client);
155 struct drm_device *dev = dev_get_drvdata(client->host);
156 struct tegra_drm *tegra = dev->dev_private;
157 struct nvdec *nvdec = to_nvdec(drm);
158 int err;
159
160 err = host1x_client_iommu_attach(client);
161 if (err < 0 && err != -ENODEV) {
162 dev_err(nvdec->dev, "failed to attach to domain: %d\n", err);
163 return err;
164 }
165
166 nvdec->channel = host1x_channel_request(client);
167 if (!nvdec->channel) {
168 err = -ENOMEM;
169 goto detach;
170 }
171
172 client->syncpts[0] = host1x_syncpt_request(client, 0);
173 if (!client->syncpts[0]) {
174 err = -ENOMEM;
175 goto free_channel;
176 }
177
178 err = tegra_drm_register_client(tegra, drm);
179 if (err < 0)
180 goto free_syncpt;
181
182 /*
183 * Inherit the DMA parameters (such as maximum segment size) from the
184 * parent host1x device.
185 */
186 client->dev->dma_parms = client->host->dma_parms;
187
188 return 0;
189
190free_syncpt:
191 host1x_syncpt_put(client->syncpts[0]);
192free_channel:
193 host1x_channel_put(nvdec->channel);
194detach:
195 host1x_client_iommu_detach(client);
196
197 return err;
198}
199
200static int nvdec_exit(struct host1x_client *client)
201{
202 struct tegra_drm_client *drm = host1x_to_drm_client(client);
203 struct drm_device *dev = dev_get_drvdata(client->host);
204 struct tegra_drm *tegra = dev->dev_private;
205 struct nvdec *nvdec = to_nvdec(drm);
206 int err;
207
208 /* avoid a dangling pointer just in case this disappears */
209 client->dev->dma_parms = NULL;
210
211 err = tegra_drm_unregister_client(tegra, drm);
212 if (err < 0)
213 return err;
214
215 pm_runtime_dont_use_autosuspend(client->dev);
216 pm_runtime_force_suspend(client->dev);
217
218 host1x_syncpt_put(client->syncpts[0]);
219 host1x_channel_put(nvdec->channel);
220 host1x_client_iommu_detach(client);
221
222 nvdec->channel = NULL;
223
224 if (client->group) {
225 dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys,
226 nvdec->falcon.firmware.size, DMA_TO_DEVICE);
227 tegra_drm_free(tegra, nvdec->falcon.firmware.size,
228 nvdec->falcon.firmware.virt,
229 nvdec->falcon.firmware.iova);
230 } else {
231 dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size,
232 nvdec->falcon.firmware.virt,
233 nvdec->falcon.firmware.iova);
234 }
235
236 return 0;
237}
238
239static const struct host1x_client_ops nvdec_client_ops = {
240 .init = nvdec_init,
241 .exit = nvdec_exit,
242};
243
244static int nvdec_load_falcon_firmware(struct nvdec *nvdec)
245{
246 struct host1x_client *client = &nvdec->client.base;
247 struct tegra_drm *tegra = nvdec->client.drm;
248 dma_addr_t iova;
249 size_t size;
250 void *virt;
251 int err;
252
253 if (nvdec->falcon.firmware.virt)
254 return 0;
255
256 err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware);
257 if (err < 0)
258 return err;
259
260 size = nvdec->falcon.firmware.size;
261
262 if (!client->group) {
263 virt = dma_alloc_coherent(nvdec->dev, size, &iova, GFP_KERNEL);
264 if (!virt)
265 return -ENOMEM;
266 } else {
267 virt = tegra_drm_alloc(tegra, size, &iova);
268 if (IS_ERR(virt))
269 return PTR_ERR(virt);
270 }
271
272 nvdec->falcon.firmware.virt = virt;
273 nvdec->falcon.firmware.iova = iova;
274
275 err = falcon_load_firmware(&nvdec->falcon);
276 if (err < 0)
277 goto cleanup;
278
279 /*
280 * In this case we have received an IOVA from the shared domain, so we
281 * need to make sure to get the physical address so that the DMA API
282 * knows what memory pages to flush the cache for.
283 */
284 if (client->group) {
285 dma_addr_t phys;
286
287 phys = dma_map_single(nvdec->dev, virt, size, DMA_TO_DEVICE);
288
289 err = dma_mapping_error(nvdec->dev, phys);
290 if (err < 0)
291 goto cleanup;
292
293 nvdec->falcon.firmware.phys = phys;
294 }
295
296 return 0;
297
298cleanup:
299 if (!client->group)
300 dma_free_coherent(nvdec->dev, size, virt, iova);
301 else
302 tegra_drm_free(tegra, size, virt, iova);
303
304 return err;
305}
306
307static __maybe_unused int nvdec_runtime_resume(struct device *dev)
308{
309 struct nvdec *nvdec = dev_get_drvdata(dev);
310 int err;
311
312 err = clk_bulk_prepare_enable(nvdec->num_clks, nvdec->clks);
313 if (err < 0)
314 return err;
315
316 usleep_range(10, 20);
317
318 if (nvdec->config->has_riscv) {
319 err = nvdec_boot_riscv(nvdec);
320 if (err < 0)
321 goto disable;
322 } else {
323 err = nvdec_load_falcon_firmware(nvdec);
324 if (err < 0)
325 goto disable;
326
327 err = nvdec_boot_falcon(nvdec);
328 if (err < 0)
329 goto disable;
330 }
331
332 return 0;
333
334disable:
335 clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);
336 return err;
337}
338
339static __maybe_unused int nvdec_runtime_suspend(struct device *dev)
340{
341 struct nvdec *nvdec = dev_get_drvdata(dev);
342
343 host1x_channel_stop(nvdec->channel);
344
345 clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);
346
347 return 0;
348}
349
350static int nvdec_open_channel(struct tegra_drm_client *client,
351 struct tegra_drm_context *context)
352{
353 struct nvdec *nvdec = to_nvdec(client);
354
355 context->channel = host1x_channel_get(nvdec->channel);
356 if (!context->channel)
357 return -ENOMEM;
358
359 return 0;
360}
361
362static void nvdec_close_channel(struct tegra_drm_context *context)
363{
364 host1x_channel_put(context->channel);
365}
366
367static int nvdec_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
368{
369 *supported = true;
370
371 return 0;
372}
373
374static const struct tegra_drm_client_ops nvdec_ops = {
375 .open_channel = nvdec_open_channel,
376 .close_channel = nvdec_close_channel,
377 .submit = tegra_drm_submit,
378 .get_streamid_offset = tegra_drm_get_streamid_offset_thi,
379 .can_use_memory_ctx = nvdec_can_use_memory_ctx,
380};
381
382#define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin"
383
384static const struct nvdec_config nvdec_t210_config = {
385 .firmware = NVIDIA_TEGRA_210_NVDEC_FIRMWARE,
386 .version = 0x21,
387 .supports_sid = false,
388};
389
390#define NVIDIA_TEGRA_186_NVDEC_FIRMWARE "nvidia/tegra186/nvdec.bin"
391
392static const struct nvdec_config nvdec_t186_config = {
393 .firmware = NVIDIA_TEGRA_186_NVDEC_FIRMWARE,
394 .version = 0x18,
395 .supports_sid = true,
396};
397
398#define NVIDIA_TEGRA_194_NVDEC_FIRMWARE "nvidia/tegra194/nvdec.bin"
399
400static const struct nvdec_config nvdec_t194_config = {
401 .firmware = NVIDIA_TEGRA_194_NVDEC_FIRMWARE,
402 .version = 0x19,
403 .supports_sid = true,
404};
405
406static const struct nvdec_config nvdec_t234_config = {
407 .version = 0x23,
408 .supports_sid = true,
409 .has_riscv = true,
410 .has_extra_clocks = true,
411};
412
413static const struct of_device_id tegra_nvdec_of_match[] = {
414 { .compatible = "nvidia,tegra210-nvdec", .data = &nvdec_t210_config },
415 { .compatible = "nvidia,tegra186-nvdec", .data = &nvdec_t186_config },
416 { .compatible = "nvidia,tegra194-nvdec", .data = &nvdec_t194_config },
417 { .compatible = "nvidia,tegra234-nvdec", .data = &nvdec_t234_config },
418 { },
419};
420MODULE_DEVICE_TABLE(of, tegra_nvdec_of_match);
421
422static int nvdec_probe(struct platform_device *pdev)
423{
424 struct device *dev = &pdev->dev;
425 struct host1x_syncpt **syncpts;
426 struct nvdec *nvdec;
427 u32 host_class;
428 int err;
429
430 /* inherit DMA mask from host1x parent */
431 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
432 if (err < 0) {
433 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
434 return err;
435 }
436
437 nvdec = devm_kzalloc(dev, sizeof(*nvdec), GFP_KERNEL);
438 if (!nvdec)
439 return -ENOMEM;
440
441 nvdec->config = of_device_get_match_data(dev);
442
443 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
444 if (!syncpts)
445 return -ENOMEM;
446
447 nvdec->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
448 if (IS_ERR(nvdec->regs))
449 return PTR_ERR(nvdec->regs);
450
451 nvdec->clks[0].id = "nvdec";
452 nvdec->num_clks = 1;
453
454 if (nvdec->config->has_extra_clocks) {
455 nvdec->num_clks = 3;
456 nvdec->clks[1].id = "fuse";
457 nvdec->clks[2].id = "tsec_pka";
458 }
459
460 err = devm_clk_bulk_get(dev, nvdec->num_clks, nvdec->clks);
461 if (err) {
462 dev_err(&pdev->dev, "failed to get clock(s)\n");
463 return err;
464 }
465
466 err = clk_set_rate(nvdec->clks[0].clk, ULONG_MAX);
467 if (err < 0) {
468 dev_err(&pdev->dev, "failed to set clock rate\n");
469 return err;
470 }
471
472 err = of_property_read_u32(dev->of_node, "nvidia,host1x-class", &host_class);
473 if (err < 0)
474 host_class = HOST1X_CLASS_NVDEC;
475
476 if (nvdec->config->has_riscv) {
477 struct tegra_mc *mc;
478
479 mc = devm_tegra_memory_controller_get(dev);
480 if (IS_ERR(mc)) {
481 dev_err_probe(dev, PTR_ERR(mc),
482 "failed to get memory controller handle\n");
483 return PTR_ERR(mc);
484 }
485
486 err = tegra_mc_get_carveout_info(mc, 1, &nvdec->carveout_base, NULL);
487 if (err) {
488 dev_err(dev, "failed to get carveout info: %d\n", err);
489 return err;
490 }
491
492 nvdec->reset = devm_reset_control_get_exclusive_released(dev, "nvdec");
493 if (IS_ERR(nvdec->reset)) {
494 dev_err_probe(dev, PTR_ERR(nvdec->reset), "failed to get reset\n");
495 return PTR_ERR(nvdec->reset);
496 }
497
498 nvdec->riscv.dev = dev;
499 nvdec->riscv.regs = nvdec->regs;
500
501 err = tegra_drm_riscv_read_descriptors(&nvdec->riscv);
502 if (err < 0)
503 return err;
504 } else {
505 nvdec->falcon.dev = dev;
506 nvdec->falcon.regs = nvdec->regs;
507
508 err = falcon_init(&nvdec->falcon);
509 if (err < 0)
510 return err;
511 }
512
513 platform_set_drvdata(pdev, nvdec);
514
515 INIT_LIST_HEAD(&nvdec->client.base.list);
516 nvdec->client.base.ops = &nvdec_client_ops;
517 nvdec->client.base.dev = dev;
518 nvdec->client.base.class = host_class;
519 nvdec->client.base.syncpts = syncpts;
520 nvdec->client.base.num_syncpts = 1;
521 nvdec->dev = dev;
522
523 INIT_LIST_HEAD(&nvdec->client.list);
524 nvdec->client.version = nvdec->config->version;
525 nvdec->client.ops = &nvdec_ops;
526
527 err = host1x_client_register(&nvdec->client.base);
528 if (err < 0) {
529 dev_err(dev, "failed to register host1x client: %d\n", err);
530 goto exit_falcon;
531 }
532
533 pm_runtime_enable(dev);
534 pm_runtime_use_autosuspend(dev);
535 pm_runtime_set_autosuspend_delay(dev, 500);
536
537 return 0;
538
539exit_falcon:
540 falcon_exit(&nvdec->falcon);
541
542 return err;
543}
544
545static void nvdec_remove(struct platform_device *pdev)
546{
547 struct nvdec *nvdec = platform_get_drvdata(pdev);
548
549 pm_runtime_disable(&pdev->dev);
550 host1x_client_unregister(&nvdec->client.base);
551 falcon_exit(&nvdec->falcon);
552}
553
554static const struct dev_pm_ops nvdec_pm_ops = {
555 SET_RUNTIME_PM_OPS(nvdec_runtime_suspend, nvdec_runtime_resume, NULL)
556 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
557 pm_runtime_force_resume)
558};
559
560struct platform_driver tegra_nvdec_driver = {
561 .driver = {
562 .name = "tegra-nvdec",
563 .of_match_table = tegra_nvdec_of_match,
564 .pm = &nvdec_pm_ops
565 },
566 .probe = nvdec_probe,
567 .remove = nvdec_remove,
568};
569
570#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
571MODULE_FIRMWARE(NVIDIA_TEGRA_210_NVDEC_FIRMWARE);
572#endif
573#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
574MODULE_FIRMWARE(NVIDIA_TEGRA_186_NVDEC_FIRMWARE);
575#endif
576#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
577MODULE_FIRMWARE(NVIDIA_TEGRA_194_NVDEC_FIRMWARE);
578#endif