projects/linux·blob master · refs

1592 lines · 44.9 KiB

1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie <[email protected]>
7 * Gerd Hoffmann <[email protected]>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29#include <linux/dma-mapping.h>
30#include <linux/virtio.h>
31#include <linux/virtio_config.h>
32#include <linux/virtio_ring.h>
33
34#include <drm/drm_edid.h>
35#include <drm/drm_print.h>
36
37#include "virtgpu_drv.h"
38#include "virtgpu_trace.h"
39
40#define MAX_INLINE_CMD_SIZE 96
41#define MAX_INLINE_RESP_SIZE 24
42#define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
43 + MAX_INLINE_CMD_SIZE \
44 + MAX_INLINE_RESP_SIZE)
45
46static void convert_to_hw_box(struct virtio_gpu_box *dst,
47 const struct drm_virtgpu_3d_box *src)
48{
49 dst->x = cpu_to_le32(src->x);
50 dst->y = cpu_to_le32(src->y);
51 dst->z = cpu_to_le32(src->z);
52 dst->w = cpu_to_le32(src->w);
53 dst->h = cpu_to_le32(src->h);
54 dst->d = cpu_to_le32(src->d);
55}
56
57void virtio_gpu_ctrl_ack(struct virtqueue *vq)
58{
59 struct drm_device *dev = vq->vdev->priv;
60 struct virtio_gpu_device *vgdev = dev->dev_private;
61
62 schedule_work(&vgdev->ctrlq.dequeue_work);
63}
64
65void virtio_gpu_cursor_ack(struct virtqueue *vq)
66{
67 struct drm_device *dev = vq->vdev->priv;
68 struct virtio_gpu_device *vgdev = dev->dev_private;
69
70 schedule_work(&vgdev->cursorq.dequeue_work);
71}
72
73int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
74{
75 vgdev->vbufs = kmem_cache_create("virtio-gpu-vbufs",
76 VBUFFER_SIZE,
77 __alignof__(struct virtio_gpu_vbuffer),
78 0, NULL);
79 if (!vgdev->vbufs)
80 return -ENOMEM;
81 return 0;
82}
83
84void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
85{
86 kmem_cache_destroy(vgdev->vbufs);
87 vgdev->vbufs = NULL;
88}
89
90/* For drm_panic */
91static struct virtio_gpu_vbuffer*
92virtio_gpu_panic_get_vbuf(struct virtio_gpu_device *vgdev, int size)
93{
94 struct virtio_gpu_vbuffer *vbuf;
95
96 vbuf = kmem_cache_zalloc(vgdev->vbufs, GFP_ATOMIC);
97
98 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
99 vbuf->size = size;
100 vbuf->resp_cb = NULL;
101 vbuf->resp_size = sizeof(struct virtio_gpu_ctrl_hdr);
102 vbuf->resp_buf = (void *)vbuf->buf + size;
103 return vbuf;
104}
105
106static struct virtio_gpu_vbuffer*
107virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
108 int size, int resp_size, void *resp_buf,
109 virtio_gpu_resp_cb resp_cb)
110{
111 struct virtio_gpu_vbuffer *vbuf;
112
113 vbuf = kmem_cache_zalloc(vgdev->vbufs, GFP_KERNEL | __GFP_NOFAIL);
114
115 BUG_ON(size > MAX_INLINE_CMD_SIZE ||
116 size < sizeof(struct virtio_gpu_ctrl_hdr));
117 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
118 vbuf->size = size;
119
120 vbuf->resp_cb = resp_cb;
121 vbuf->resp_size = resp_size;
122 if (resp_size <= MAX_INLINE_RESP_SIZE)
123 vbuf->resp_buf = (void *)vbuf->buf + size;
124 else
125 vbuf->resp_buf = resp_buf;
126 BUG_ON(!vbuf->resp_buf);
127 return vbuf;
128}
129
130static struct virtio_gpu_ctrl_hdr *
131virtio_gpu_vbuf_ctrl_hdr(struct virtio_gpu_vbuffer *vbuf)
132{
133 /* this assumes a vbuf contains a command that starts with a
134 * virtio_gpu_ctrl_hdr, which is true for both ctrl and cursor
135 * virtqueues.
136 */
137 return (struct virtio_gpu_ctrl_hdr *)vbuf->buf;
138}
139
140static struct virtio_gpu_update_cursor*
141virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
142 struct virtio_gpu_vbuffer **vbuffer_p)
143{
144 struct virtio_gpu_vbuffer *vbuf;
145
146 vbuf = virtio_gpu_get_vbuf
147 (vgdev, sizeof(struct virtio_gpu_update_cursor),
148 0, NULL, NULL);
149 if (IS_ERR(vbuf)) {
150 *vbuffer_p = NULL;
151 return ERR_CAST(vbuf);
152 }
153 *vbuffer_p = vbuf;
154 return (struct virtio_gpu_update_cursor *)vbuf->buf;
155}
156
157/* For drm_panic */
158static void *virtio_gpu_panic_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
159 struct virtio_gpu_vbuffer **vbuffer_p,
160 int cmd_size)
161{
162 struct virtio_gpu_vbuffer *vbuf;
163
164 vbuf = virtio_gpu_panic_get_vbuf(vgdev, cmd_size);
165 *vbuffer_p = vbuf;
166 return (struct virtio_gpu_command *)vbuf->buf;
167}
168
169static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
170 virtio_gpu_resp_cb cb,
171 struct virtio_gpu_vbuffer **vbuffer_p,
172 int cmd_size, int resp_size,
173 void *resp_buf)
174{
175 struct virtio_gpu_vbuffer *vbuf;
176
177 vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size,
178 resp_size, resp_buf, cb);
179 *vbuffer_p = vbuf;
180 return (struct virtio_gpu_command *)vbuf->buf;
181}
182
183static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
184 struct virtio_gpu_vbuffer **vbuffer_p,
185 int size)
186{
187 return virtio_gpu_alloc_cmd_resp(vgdev, NULL, vbuffer_p, size,
188 sizeof(struct virtio_gpu_ctrl_hdr),
189 NULL);
190}
191
192static void *virtio_gpu_alloc_cmd_cb(struct virtio_gpu_device *vgdev,
193 struct virtio_gpu_vbuffer **vbuffer_p,
194 int size,
195 virtio_gpu_resp_cb cb)
196{
197 return virtio_gpu_alloc_cmd_resp(vgdev, cb, vbuffer_p, size,
198 sizeof(struct virtio_gpu_ctrl_hdr),
199 NULL);
200}
201
202static void free_vbuf(struct virtio_gpu_device *vgdev,
203 struct virtio_gpu_vbuffer *vbuf)
204{
205 if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
206 kfree(vbuf->resp_buf);
207 kvfree(vbuf->data_buf);
208 kmem_cache_free(vgdev->vbufs, vbuf);
209}
210
211void virtio_gpu_reclaim_vbufs(struct virtio_gpu_device *vgdev)
212{
213 struct virtio_gpu_vbuffer *vbuf;
214
215 while ((vbuf = virtqueue_detach_unused_buf(vgdev->ctrlq.vq))) {
216 if (vbuf->objs)
217 virtio_gpu_array_put_free(vbuf->objs);
218 if (vbuf->resp_cb_data)
219 virtio_gpu_cleanup_object(vbuf->resp_cb_data);
220 free_vbuf(vgdev, vbuf);
221 }
222 while ((vbuf = virtqueue_detach_unused_buf(vgdev->cursorq.vq)))
223 free_vbuf(vgdev, vbuf);
224}
225
226static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
227{
228 struct virtio_gpu_vbuffer *vbuf;
229 unsigned int len;
230 int freed = 0;
231
232 while ((vbuf = virtqueue_get_buf(vq, &len))) {
233 list_add_tail(&vbuf->list, reclaim_list);
234 freed++;
235 }
236 if (freed == 0)
237 DRM_DEBUG("Huh? zero vbufs reclaimed");
238}
239
240void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
241{
242 struct virtio_gpu_device *vgdev =
243 container_of(work, struct virtio_gpu_device,
244 ctrlq.dequeue_work);
245 struct list_head reclaim_list;
246 struct virtio_gpu_vbuffer *entry, *tmp;
247 struct virtio_gpu_ctrl_hdr *resp;
248 u64 fence_id;
249
250 INIT_LIST_HEAD(&reclaim_list);
251 spin_lock(&vgdev->ctrlq.qlock);
252 do {
253 virtqueue_disable_cb(vgdev->ctrlq.vq);
254 reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list);
255
256 } while (!virtqueue_enable_cb(vgdev->ctrlq.vq));
257 spin_unlock(&vgdev->ctrlq.qlock);
258
259 /*
260 * Sync guest-bound transfers before signalling anything, so that a
261 * waiter cannot read the backing pages while what the device wrote is
262 * still in a bounce buffer. This cannot be folded into the loop below:
263 * virtio_gpu_fence_event_process() also signals every earlier fence in
264 * the same context, so any entry there may signal this entry's fence.
265 */
266 list_for_each_entry(entry, &reclaim_list, list) {
267 if (entry->sync_for_cpu) {
268 struct virtio_gpu_object *bo =
269 gem_to_virtio_gpu_obj(entry->objs->objs[0]);
270
271 dma_sync_sgtable_for_cpu(vgdev->vdev->dev.parent,
272 bo->base.sgt, DMA_FROM_DEVICE);
273 /*
274 * Release, so a transfer the other way that skips its
275 * wait on the strength of this cannot go on to read
276 * the backing pages before the sync above is visible.
277 * Nothing orders the two otherwise: where the mapping
278 * bounces on a coherent device the sync is a plain
279 * copy, and dma_direct_sync_sg_for_cpu() emits its
280 * barrier only for the non-coherent case.
281 */
282 smp_store_release(&bo->from_host_pending, false);
283 }
284 }
285
286 list_for_each_entry(entry, &reclaim_list, list) {
287 resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
288
289 trace_virtio_gpu_cmd_response(vgdev->ctrlq.vq, resp, entry->seqno);
290
291 if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) {
292 if (le32_to_cpu(resp->type) >= VIRTIO_GPU_RESP_ERR_UNSPEC) {
293 struct virtio_gpu_ctrl_hdr *cmd;
294
295 cmd = virtio_gpu_vbuf_ctrl_hdr(entry);
296 DRM_ERROR_RATELIMITED("response 0x%x (command 0x%x)\n",
297 le32_to_cpu(resp->type),
298 le32_to_cpu(cmd->type));
299 } else
300 DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
301 }
302 if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
303 fence_id = le64_to_cpu(resp->fence_id);
304 virtio_gpu_fence_event_process(vgdev, fence_id);
305 }
306 if (entry->resp_cb)
307 entry->resp_cb(vgdev, entry);
308 }
309 wake_up(&vgdev->ctrlq.ack_queue);
310
311 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
312 if (entry->objs)
313 virtio_gpu_array_put_free_delayed(vgdev, entry->objs);
314 list_del(&entry->list);
315 free_vbuf(vgdev, entry);
316 }
317}
318
319void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
320{
321 struct virtio_gpu_device *vgdev =
322 container_of(work, struct virtio_gpu_device,
323 cursorq.dequeue_work);
324 struct list_head reclaim_list;
325 struct virtio_gpu_vbuffer *entry, *tmp;
326
327 INIT_LIST_HEAD(&reclaim_list);
328 spin_lock(&vgdev->cursorq.qlock);
329 do {
330 virtqueue_disable_cb(vgdev->cursorq.vq);
331 reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list);
332 } while (!virtqueue_enable_cb(vgdev->cursorq.vq));
333 spin_unlock(&vgdev->cursorq.qlock);
334
335 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
336 struct virtio_gpu_ctrl_hdr *resp =
337 (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
338
339 trace_virtio_gpu_cmd_response(vgdev->cursorq.vq, resp, entry->seqno);
340 list_del(&entry->list);
341 free_vbuf(vgdev, entry);
342 }
343 wake_up(&vgdev->cursorq.ack_queue);
344}
345
346/* Create sg_table from a vmalloc'd buffer. */
347static struct sg_table *vmalloc_to_sgt(char *data, uint32_t size, int *sg_ents)
348{
349 int ret, s, i;
350 struct sg_table *sgt;
351 struct scatterlist *sg;
352 struct page *pg;
353
354 if (WARN_ON(!PAGE_ALIGNED(data)))
355 return NULL;
356
357 sgt = kmalloc_obj(*sgt);
358 if (!sgt)
359 return NULL;
360
361 *sg_ents = DIV_ROUND_UP(size, PAGE_SIZE);
362 ret = sg_alloc_table(sgt, *sg_ents, GFP_KERNEL);
363 if (ret) {
364 kfree(sgt);
365 return NULL;
366 }
367
368 for_each_sgtable_sg(sgt, sg, i) {
369 pg = vmalloc_to_page(data);
370 if (!pg) {
371 sg_free_table(sgt);
372 kfree(sgt);
373 return NULL;
374 }
375
376 s = min_t(int, PAGE_SIZE, size);
377 sg_set_page(sg, pg, s, 0);
378
379 size -= s;
380 data += s;
381 }
382
383 return sgt;
384}
385
386/* For drm_panic */
387static int virtio_gpu_panic_queue_ctrl_sgs(struct virtio_gpu_device *vgdev,
388 struct virtio_gpu_vbuffer *vbuf,
389 int elemcnt,
390 struct scatterlist **sgs,
391 int outcnt,
392 int incnt)
393{
394 struct virtqueue *vq = vgdev->ctrlq.vq;
395 int ret;
396
397 if (vgdev->has_indirect)
398 elemcnt = 1;
399
400 if (vq->num_free < elemcnt)
401 return -ENOMEM;
402
403 ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
404 WARN_ON(ret);
405
406 vbuf->seqno = ++vgdev->ctrlq.seqno;
407 trace_virtio_gpu_cmd_queue(vq, virtio_gpu_vbuf_ctrl_hdr(vbuf), vbuf->seqno);
408
409 atomic_inc(&vgdev->pending_commands);
410
411 return 0;
412}
413
414int virtio_gpu_wait_queue(struct virtio_gpu_queue *vgvq, unsigned int num_elem)
415{
416 int ret;
417
418 /* Wait up to 5 seconds for enough free slots to become available */
419 ret = wait_event_timeout(vgvq->ack_queue,
420 vgvq->vq->num_free >= num_elem,
421 5 * HZ);
422 if (ret == 0)
423 return -ETIMEDOUT;
424
425 return 0;
426}
427
428static int virtio_gpu_queue_ctrl_sgs(struct virtio_gpu_device *vgdev,
429 struct virtio_gpu_vbuffer *vbuf,
430 struct virtio_gpu_fence *fence,
431 int elemcnt,
432 struct scatterlist **sgs,
433 int outcnt,
434 int incnt)
435{
436 struct virtqueue *vq = vgdev->ctrlq.vq;
437 int ret, idx;
438
439 if (!drm_dev_enter(vgdev->ddev, &idx)) {
440 if (fence && vbuf->objs)
441 virtio_gpu_array_unlock_resv(vbuf->objs);
442 free_vbuf(vgdev, vbuf);
443 return -ENODEV;
444 }
445
446 if (vgdev->has_indirect)
447 elemcnt = 1;
448
449again:
450 spin_lock(&vgdev->ctrlq.qlock);
451
452 if (vq->num_free < elemcnt) {
453 spin_unlock(&vgdev->ctrlq.qlock);
454 virtio_gpu_notify(vgdev);
455 wait_event(vgdev->ctrlq.ack_queue,
456 vq->num_free >= elemcnt || vgdev->vqs_released);
457 /*
458 * Set by virtio_gpu_release_vqs() to unblock
459 * synchronize_srcu() wait in drm_dev_unplug().
460 */
461 if (vgdev->vqs_released) {
462 if (fence && vbuf->objs)
463 virtio_gpu_array_unlock_resv(vbuf->objs);
464 free_vbuf(vgdev, vbuf);
465 drm_dev_exit(idx);
466 return -ENODEV;
467 }
468 goto again;
469 }
470
471 /* now that the position of the vbuf in the virtqueue is known, we can
472 * finally set the fence id
473 */
474 if (fence) {
475 virtio_gpu_fence_emit(vgdev, virtio_gpu_vbuf_ctrl_hdr(vbuf),
476 fence);
477 if (vbuf->objs) {
478 virtio_gpu_array_add_fence(vbuf->objs, &fence->f);
479 virtio_gpu_array_unlock_resv(vbuf->objs);
480 }
481 }
482
483 ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
484 WARN_ON(ret);
485
486 vbuf->seqno = ++vgdev->ctrlq.seqno;
487 trace_virtio_gpu_cmd_queue(vq, virtio_gpu_vbuf_ctrl_hdr(vbuf), vbuf->seqno);
488
489 atomic_inc(&vgdev->pending_commands);
490
491 spin_unlock(&vgdev->ctrlq.qlock);
492
493 drm_dev_exit(idx);
494 return 0;
495}
496
497/* For drm_panic */
498static int virtio_gpu_panic_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
499 struct virtio_gpu_vbuffer *vbuf)
500{
501 struct scatterlist *sgs[3], vcmd, vresp;
502 int elemcnt = 0, outcnt = 0, incnt = 0;
503
504 /* set up vcmd */
505 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
506 elemcnt++;
507 sgs[outcnt] = &vcmd;
508 outcnt++;
509
510 /* set up vresp */
511 if (vbuf->resp_size) {
512 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
513 elemcnt++;
514 sgs[outcnt + incnt] = &vresp;
515 incnt++;
516 }
517
518 return virtio_gpu_panic_queue_ctrl_sgs(vgdev, vbuf,
519 elemcnt, sgs,
520 outcnt, incnt);
521}
522
523static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
524 struct virtio_gpu_vbuffer *vbuf,
525 struct virtio_gpu_fence *fence)
526{
527 struct scatterlist *sgs[3], vcmd, vout, vresp;
528 struct sg_table *sgt = NULL;
529 int elemcnt = 0, outcnt = 0, incnt = 0, ret;
530
531 /* set up vcmd */
532 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
533 elemcnt++;
534 sgs[outcnt] = &vcmd;
535 outcnt++;
536
537 /* set up vout */
538 if (vbuf->data_size) {
539 if (is_vmalloc_addr(vbuf->data_buf)) {
540 int sg_ents;
541
542 sgt = vmalloc_to_sgt(vbuf->data_buf, vbuf->data_size,
543 &sg_ents);
544 if (!sgt) {
545 if (fence && vbuf->objs)
546 virtio_gpu_array_unlock_resv(vbuf->objs);
547 return -ENOMEM;
548 }
549
550 elemcnt += sg_ents;
551 sgs[outcnt] = sgt->sgl;
552 } else {
553 sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
554 elemcnt++;
555 sgs[outcnt] = &vout;
556 }
557 outcnt++;
558 }
559
560 /* set up vresp */
561 if (vbuf->resp_size) {
562 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
563 elemcnt++;
564 sgs[outcnt + incnt] = &vresp;
565 incnt++;
566 }
567
568 ret = virtio_gpu_queue_ctrl_sgs(vgdev, vbuf, fence, elemcnt, sgs, outcnt,
569 incnt);
570
571 if (sgt) {
572 sg_free_table(sgt);
573 kfree(sgt);
574 }
575 return ret;
576}
577
578/* For drm_panic */
579void virtio_gpu_panic_notify(struct virtio_gpu_device *vgdev)
580{
581 bool notify;
582
583 if (!atomic_read(&vgdev->pending_commands))
584 return;
585
586 atomic_set(&vgdev->pending_commands, 0);
587 notify = virtqueue_kick_prepare(vgdev->ctrlq.vq);
588
589 if (notify)
590 virtqueue_notify(vgdev->ctrlq.vq);
591}
592
593void virtio_gpu_notify(struct virtio_gpu_device *vgdev)
594{
595 bool notify;
596
597 if (!atomic_read(&vgdev->pending_commands))
598 return;
599
600 spin_lock(&vgdev->ctrlq.qlock);
601 atomic_set(&vgdev->pending_commands, 0);
602 notify = virtqueue_kick_prepare(vgdev->ctrlq.vq);
603 spin_unlock(&vgdev->ctrlq.qlock);
604
605 if (notify)
606 virtqueue_notify(vgdev->ctrlq.vq);
607}
608
609static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
610 struct virtio_gpu_vbuffer *vbuf)
611{
612 return virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, NULL);
613}
614
615static void virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
616 struct virtio_gpu_vbuffer *vbuf)
617{
618 struct virtqueue *vq = vgdev->cursorq.vq;
619 struct scatterlist *sgs[1], ccmd;
620 int idx, ret, outcnt;
621 bool notify;
622
623 if (!drm_dev_enter(vgdev->ddev, &idx)) {
624 free_vbuf(vgdev, vbuf);
625 return;
626 }
627
628 sg_init_one(&ccmd, vbuf->buf, vbuf->size);
629 sgs[0] = &ccmd;
630 outcnt = 1;
631
632 spin_lock(&vgdev->cursorq.qlock);
633retry:
634 ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
635 if (ret == -ENOSPC) {
636 spin_unlock(&vgdev->cursorq.qlock);
637 wait_event(vgdev->cursorq.ack_queue,
638 vq->num_free >= outcnt || vgdev->vqs_released);
639 /* See comment in virtio_gpu_queue_ctrl_sgs(). */
640 if (vgdev->vqs_released) {
641 free_vbuf(vgdev, vbuf);
642 drm_dev_exit(idx);
643 return;
644 }
645 spin_lock(&vgdev->cursorq.qlock);
646 goto retry;
647 } else {
648 vbuf->seqno = ++vgdev->cursorq.seqno;
649 trace_virtio_gpu_cmd_queue(vq,
650 virtio_gpu_vbuf_ctrl_hdr(vbuf),
651 vbuf->seqno);
652
653 notify = virtqueue_kick_prepare(vq);
654 }
655
656 spin_unlock(&vgdev->cursorq.qlock);
657
658 if (notify)
659 virtqueue_notify(vq);
660
661 drm_dev_exit(idx);
662}
663
664/* just create gem objects for userspace and long lived objects,
665 * just use dma_alloced pages for the queue objects?
666 */
667
668/* create a basic resource */
669void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
670 struct virtio_gpu_object *bo,
671 struct virtio_gpu_object_params *params,
672 struct virtio_gpu_object_array *objs,
673 struct virtio_gpu_fence *fence)
674{
675 struct virtio_gpu_resource_create_2d *cmd_p;
676 struct virtio_gpu_vbuffer *vbuf;
677
678 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
679 memset(cmd_p, 0, sizeof(*cmd_p));
680 vbuf->objs = objs;
681
682 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
683 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
684 cmd_p->format = cpu_to_le32(params->format);
685 cmd_p->width = cpu_to_le32(params->width);
686 cmd_p->height = cpu_to_le32(params->height);
687
688 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
689 bo->created = true;
690}
691
692static void virtio_gpu_cmd_unref_cb(struct virtio_gpu_device *vgdev,
693 struct virtio_gpu_vbuffer *vbuf)
694{
695 struct virtio_gpu_object *bo;
696
697 bo = vbuf->resp_cb_data;
698 vbuf->resp_cb_data = NULL;
699
700 virtio_gpu_cleanup_object(bo);
701}
702
703void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
704 struct virtio_gpu_object *bo,
705 bool no_cb)
706{
707 struct virtio_gpu_resource_unref *cmd_p;
708 struct virtio_gpu_vbuffer *vbuf;
709 int ret;
710
711 if (no_cb) {
712 cmd_p = virtio_gpu_alloc_cmd_cb(vgdev, &vbuf, sizeof(*cmd_p),
713 NULL);
714 } else {
715 cmd_p = virtio_gpu_alloc_cmd_cb(vgdev, &vbuf, sizeof(*cmd_p),
716 virtio_gpu_cmd_unref_cb);
717 }
718
719 memset(cmd_p, 0, sizeof(*cmd_p));
720
721 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
722 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
723
724 vbuf->resp_cb_data = bo;
725 ret = virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
726 if (ret < 0)
727 virtio_gpu_cleanup_object(bo);
728}
729
730void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
731 uint32_t scanout_id, uint32_t resource_id,
732 uint32_t width, uint32_t height,
733 uint32_t x, uint32_t y)
734{
735 struct virtio_gpu_set_scanout *cmd_p;
736 struct virtio_gpu_vbuffer *vbuf;
737
738 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
739 memset(cmd_p, 0, sizeof(*cmd_p));
740
741 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
742 cmd_p->resource_id = cpu_to_le32(resource_id);
743 cmd_p->scanout_id = cpu_to_le32(scanout_id);
744 cmd_p->r.width = cpu_to_le32(width);
745 cmd_p->r.height = cpu_to_le32(height);
746 cmd_p->r.x = cpu_to_le32(x);
747 cmd_p->r.y = cpu_to_le32(y);
748
749 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
750}
751
752/* For drm_panic */
753void virtio_gpu_panic_cmd_resource_flush(struct virtio_gpu_device *vgdev,
754 uint32_t resource_id,
755 uint32_t x, uint32_t y,
756 uint32_t width, uint32_t height)
757{
758 struct virtio_gpu_resource_flush *cmd_p;
759 struct virtio_gpu_vbuffer *vbuf;
760
761 cmd_p = virtio_gpu_panic_alloc_cmd_resp(vgdev, &vbuf, sizeof(*cmd_p));
762 memset(cmd_p, 0, sizeof(*cmd_p));
763 vbuf->objs = NULL;
764
765 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
766 cmd_p->resource_id = cpu_to_le32(resource_id);
767 cmd_p->r.width = cpu_to_le32(width);
768 cmd_p->r.height = cpu_to_le32(height);
769 cmd_p->r.x = cpu_to_le32(x);
770 cmd_p->r.y = cpu_to_le32(y);
771
772 virtio_gpu_panic_queue_ctrl_buffer(vgdev, vbuf);
773}
774
775void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
776 uint32_t resource_id,
777 uint32_t x, uint32_t y,
778 uint32_t width, uint32_t height,
779 struct virtio_gpu_object_array *objs,
780 struct virtio_gpu_fence *fence)
781{
782 struct virtio_gpu_resource_flush *cmd_p;
783 struct virtio_gpu_vbuffer *vbuf;
784
785 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
786 memset(cmd_p, 0, sizeof(*cmd_p));
787 vbuf->objs = objs;
788
789 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
790 cmd_p->resource_id = cpu_to_le32(resource_id);
791 cmd_p->r.width = cpu_to_le32(width);
792 cmd_p->r.height = cpu_to_le32(height);
793 cmd_p->r.x = cpu_to_le32(x);
794 cmd_p->r.y = cpu_to_le32(y);
795
796 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
797}
798
799/* For drm_panic */
800int virtio_gpu_panic_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
801 uint64_t offset,
802 uint32_t width, uint32_t height,
803 uint32_t x, uint32_t y,
804 struct virtio_gpu_object_array *objs)
805{
806 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
807 struct virtio_gpu_transfer_to_host_2d *cmd_p;
808 struct virtio_gpu_vbuffer *vbuf;
809 bool use_dma_api = virtio_gpu_use_dma_api(vgdev->vdev);
810
811 if (virtio_gpu_is_shmem(bo) && use_dma_api)
812 dma_sync_sgtable_for_device(vgdev->vdev->dev.parent,
813 bo->base.sgt, DMA_TO_DEVICE);
814
815 cmd_p = virtio_gpu_panic_alloc_cmd_resp(vgdev, &vbuf, sizeof(*cmd_p));
816 memset(cmd_p, 0, sizeof(*cmd_p));
817 vbuf->objs = objs;
818
819 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
820 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
821 cmd_p->offset = cpu_to_le64(offset);
822 cmd_p->r.width = cpu_to_le32(width);
823 cmd_p->r.height = cpu_to_le32(height);
824 cmd_p->r.x = cpu_to_le32(x);
825 cmd_p->r.y = cpu_to_le32(y);
826
827 return virtio_gpu_panic_queue_ctrl_buffer(vgdev, vbuf);
828}
829
830void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
831 uint64_t offset,
832 uint32_t width, uint32_t height,
833 uint32_t x, uint32_t y,
834 struct virtio_gpu_object_array *objs,
835 struct virtio_gpu_fence *fence)
836{
837 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
838 struct virtio_gpu_transfer_to_host_2d *cmd_p;
839 struct virtio_gpu_vbuffer *vbuf;
840 bool use_dma_api = virtio_gpu_use_dma_api(vgdev->vdev);
841
842 if (virtio_gpu_is_shmem(bo) && use_dma_api)
843 dma_sync_sgtable_for_device(vgdev->vdev->dev.parent,
844 bo->base.sgt, DMA_TO_DEVICE);
845
846 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
847 memset(cmd_p, 0, sizeof(*cmd_p));
848 vbuf->objs = objs;
849
850 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
851 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
852 cmd_p->offset = cpu_to_le64(offset);
853 cmd_p->r.width = cpu_to_le32(width);
854 cmd_p->r.height = cpu_to_le32(height);
855 cmd_p->r.x = cpu_to_le32(x);
856 cmd_p->r.y = cpu_to_le32(y);
857
858 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
859}
860
861static void
862virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
863 uint32_t resource_id,
864 struct virtio_gpu_mem_entry *ents,
865 uint32_t nents,
866 struct virtio_gpu_fence *fence)
867{
868 struct virtio_gpu_resource_attach_backing *cmd_p;
869 struct virtio_gpu_vbuffer *vbuf;
870
871 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
872 memset(cmd_p, 0, sizeof(*cmd_p));
873
874 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
875 cmd_p->resource_id = cpu_to_le32(resource_id);
876 cmd_p->nr_entries = cpu_to_le32(nents);
877
878 vbuf->data_buf = ents;
879 vbuf->data_size = sizeof(*ents) * nents;
880
881 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
882}
883
884static void
885virtio_gpu_cmd_resource_detach_backing(struct virtio_gpu_device *vgdev,
886 uint32_t resource_id,
887 struct virtio_gpu_fence *fence)
888{
889 struct virtio_gpu_resource_detach_backing *cmd_p;
890 struct virtio_gpu_vbuffer *vbuf;
891
892 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
893 memset(cmd_p, 0, sizeof(*cmd_p));
894
895 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING);
896 cmd_p->resource_id = cpu_to_le32(resource_id);
897
898 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
899}
900
901static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
902 struct virtio_gpu_vbuffer *vbuf)
903{
904 struct virtio_gpu_resp_display_info *resp =
905 (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
906 int i;
907
908 spin_lock(&vgdev->display_info_lock);
909 for (i = 0; i < vgdev->num_scanouts; i++) {
910 vgdev->outputs[i].info = resp->pmodes[i];
911 if (resp->pmodes[i].enabled) {
912 DRM_DEBUG("output %d: %dx%d+%d+%d", i,
913 le32_to_cpu(resp->pmodes[i].r.width),
914 le32_to_cpu(resp->pmodes[i].r.height),
915 le32_to_cpu(resp->pmodes[i].r.x),
916 le32_to_cpu(resp->pmodes[i].r.y));
917 } else {
918 DRM_DEBUG("output %d: disabled", i);
919 }
920 }
921
922 vgdev->display_info_pending = false;
923 spin_unlock(&vgdev->display_info_lock);
924 wake_up(&vgdev->resp_wq);
925}
926
927static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
928 struct virtio_gpu_vbuffer *vbuf)
929{
930 struct virtio_gpu_get_capset_info *cmd =
931 (struct virtio_gpu_get_capset_info *)vbuf->buf;
932 struct virtio_gpu_resp_capset_info *resp =
933 (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
934 int i = le32_to_cpu(cmd->capset_index);
935
936 spin_lock(&vgdev->display_info_lock);
937 if (vgdev->capsets) {
938 vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
939 vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
940 vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
941 } else {
942 DRM_ERROR("invalid capset memory.");
943 }
944 spin_unlock(&vgdev->display_info_lock);
945 wake_up(&vgdev->resp_wq);
946}
947
948static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
949 struct virtio_gpu_vbuffer *vbuf)
950{
951 struct virtio_gpu_get_capset *cmd =
952 (struct virtio_gpu_get_capset *)vbuf->buf;
953 struct virtio_gpu_resp_capset *resp =
954 (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
955 struct virtio_gpu_drv_cap_cache *cache_ent;
956
957 spin_lock(&vgdev->display_info_lock);
958 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
959 if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
960 cache_ent->id == le32_to_cpu(cmd->capset_id)) {
961 memcpy(cache_ent->caps_cache, resp->capset_data,
962 cache_ent->size);
963 /* Copy must occur before is_valid is signalled. */
964 smp_wmb();
965 atomic_set(&cache_ent->is_valid, 1);
966 break;
967 }
968 }
969 spin_unlock(&vgdev->display_info_lock);
970 wake_up_all(&vgdev->resp_wq);
971}
972
973static int virtio_get_edid_block(void *data, u8 *buf,
974 unsigned int block, size_t len)
975{
976 struct virtio_gpu_resp_edid *resp = data;
977 size_t start = block * EDID_LENGTH;
978
979 if (start + len > le32_to_cpu(resp->size) ||
980 start + len > sizeof(resp->edid))
981 return -EINVAL;
982 memcpy(buf, resp->edid + start, len);
983 return 0;
984}
985
986static void virtio_gpu_cmd_get_edid_cb(struct virtio_gpu_device *vgdev,
987 struct virtio_gpu_vbuffer *vbuf)
988{
989 struct virtio_gpu_cmd_get_edid *cmd =
990 (struct virtio_gpu_cmd_get_edid *)vbuf->buf;
991 struct virtio_gpu_resp_edid *resp =
992 (struct virtio_gpu_resp_edid *)vbuf->resp_buf;
993 uint32_t scanout = le32_to_cpu(cmd->scanout);
994 struct virtio_gpu_output *output;
995 const struct drm_edid *new_edid, *old_edid;
996
997 if (scanout >= vgdev->num_scanouts)
998 return;
999 output = vgdev->outputs + scanout;
1000
1001 new_edid = drm_edid_read_custom(&output->conn, virtio_get_edid_block, resp);
1002 drm_edid_connector_update(&output->conn, new_edid);
1003
1004 spin_lock(&vgdev->display_info_lock);
1005 old_edid = output->drm_edid;
1006 output->drm_edid = new_edid;
1007 spin_unlock(&vgdev->display_info_lock);
1008
1009 drm_edid_free(old_edid);
1010 wake_up(&vgdev->resp_wq);
1011}
1012
1013int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
1014{
1015 struct virtio_gpu_ctrl_hdr *cmd_p;
1016 struct virtio_gpu_vbuffer *vbuf;
1017 void *resp_buf;
1018
1019 resp_buf = kzalloc_obj(struct virtio_gpu_resp_display_info);
1020 if (!resp_buf)
1021 return -ENOMEM;
1022
1023 cmd_p = virtio_gpu_alloc_cmd_resp
1024 (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf,
1025 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info),
1026 resp_buf);
1027 memset(cmd_p, 0, sizeof(*cmd_p));
1028
1029 vgdev->display_info_pending = true;
1030 cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
1031 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1032 return 0;
1033}
1034
1035int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
1036{
1037 struct virtio_gpu_get_capset_info *cmd_p;
1038 struct virtio_gpu_vbuffer *vbuf;
1039 void *resp_buf;
1040
1041 resp_buf = kzalloc_obj(struct virtio_gpu_resp_capset_info);
1042 if (!resp_buf)
1043 return -ENOMEM;
1044
1045 cmd_p = virtio_gpu_alloc_cmd_resp
1046 (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf,
1047 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info),
1048 resp_buf);
1049 memset(cmd_p, 0, sizeof(*cmd_p));
1050
1051 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
1052 cmd_p->capset_index = cpu_to_le32(idx);
1053 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1054 return 0;
1055}
1056
1057int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
1058 int idx, int version,
1059 struct virtio_gpu_drv_cap_cache **cache_p)
1060{
1061 struct virtio_gpu_get_capset *cmd_p;
1062 struct virtio_gpu_vbuffer *vbuf;
1063 int max_size;
1064 struct virtio_gpu_drv_cap_cache *cache_ent;
1065 struct virtio_gpu_drv_cap_cache *search_ent;
1066 void *resp_buf;
1067
1068 *cache_p = NULL;
1069
1070 if (idx >= vgdev->num_capsets)
1071 return -EINVAL;
1072
1073 if (version > vgdev->capsets[idx].max_version)
1074 return -EINVAL;
1075
1076 cache_ent = kzalloc_obj(*cache_ent);
1077 if (!cache_ent)
1078 return -ENOMEM;
1079
1080 max_size = vgdev->capsets[idx].max_size;
1081 cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
1082 if (!cache_ent->caps_cache) {
1083 kfree(cache_ent);
1084 return -ENOMEM;
1085 }
1086
1087 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
1088 GFP_KERNEL);
1089 if (!resp_buf) {
1090 kfree(cache_ent->caps_cache);
1091 kfree(cache_ent);
1092 return -ENOMEM;
1093 }
1094
1095 cache_ent->version = version;
1096 cache_ent->id = vgdev->capsets[idx].id;
1097 atomic_set(&cache_ent->is_valid, 0);
1098 cache_ent->size = max_size;
1099 spin_lock(&vgdev->display_info_lock);
1100 /* Search while under lock in case it was added by another task. */
1101 list_for_each_entry(search_ent, &vgdev->cap_cache, head) {
1102 if (search_ent->id == vgdev->capsets[idx].id &&
1103 search_ent->version == version) {
1104 *cache_p = search_ent;
1105 break;
1106 }
1107 }
1108 if (!*cache_p)
1109 list_add_tail(&cache_ent->head, &vgdev->cap_cache);
1110 spin_unlock(&vgdev->display_info_lock);
1111
1112 if (*cache_p) {
1113 /* Entry was found, so free everything that was just created. */
1114 kfree(resp_buf);
1115 kfree(cache_ent->caps_cache);
1116 kfree(cache_ent);
1117 return 0;
1118 }
1119
1120 cmd_p = virtio_gpu_alloc_cmd_resp
1121 (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p),
1122 sizeof(struct virtio_gpu_resp_capset) + max_size,
1123 resp_buf);
1124 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
1125 cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
1126 cmd_p->capset_version = cpu_to_le32(version);
1127 *cache_p = cache_ent;
1128 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1129
1130 return 0;
1131}
1132
1133int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev)
1134{
1135 struct virtio_gpu_cmd_get_edid *cmd_p;
1136 struct virtio_gpu_vbuffer *vbuf;
1137 void *resp_buf;
1138 int scanout;
1139
1140 if (WARN_ON(!vgdev->has_edid))
1141 return -EINVAL;
1142
1143 for (scanout = 0; scanout < vgdev->num_scanouts; scanout++) {
1144 resp_buf = kzalloc_obj(struct virtio_gpu_resp_edid);
1145 if (!resp_buf)
1146 return -ENOMEM;
1147
1148 cmd_p = virtio_gpu_alloc_cmd_resp
1149 (vgdev, &virtio_gpu_cmd_get_edid_cb, &vbuf,
1150 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_edid),
1151 resp_buf);
1152 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_EDID);
1153 cmd_p->scanout = cpu_to_le32(scanout);
1154 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1155 }
1156
1157 return 0;
1158}
1159
1160void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
1161 uint32_t context_init, uint32_t nlen,
1162 const char *name)
1163{
1164 struct virtio_gpu_ctx_create *cmd_p;
1165 struct virtio_gpu_vbuffer *vbuf;
1166
1167 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1168 memset(cmd_p, 0, sizeof(*cmd_p));
1169
1170 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
1171 cmd_p->hdr.ctx_id = cpu_to_le32(id);
1172 cmd_p->nlen = cpu_to_le32(nlen);
1173 cmd_p->context_init = cpu_to_le32(context_init);
1174 strscpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name));
1175 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1176}
1177
1178void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
1179 uint32_t id)
1180{
1181 struct virtio_gpu_ctx_destroy *cmd_p;
1182 struct virtio_gpu_vbuffer *vbuf;
1183
1184 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1185 memset(cmd_p, 0, sizeof(*cmd_p));
1186
1187 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
1188 cmd_p->hdr.ctx_id = cpu_to_le32(id);
1189 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1190}
1191
1192void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
1193 uint32_t ctx_id,
1194 struct virtio_gpu_object_array *objs)
1195{
1196 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1197 struct virtio_gpu_ctx_resource *cmd_p;
1198 struct virtio_gpu_vbuffer *vbuf;
1199
1200 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1201 memset(cmd_p, 0, sizeof(*cmd_p));
1202 vbuf->objs = objs;
1203
1204 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
1205 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1206 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1207 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1208}
1209
1210void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
1211 uint32_t ctx_id,
1212 struct virtio_gpu_object_array *objs)
1213{
1214 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1215 struct virtio_gpu_ctx_resource *cmd_p;
1216 struct virtio_gpu_vbuffer *vbuf;
1217
1218 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1219 memset(cmd_p, 0, sizeof(*cmd_p));
1220 vbuf->objs = objs;
1221
1222 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
1223 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1224 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1225 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1226}
1227
1228void
1229virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
1230 struct virtio_gpu_object *bo,
1231 struct virtio_gpu_object_params *params,
1232 struct virtio_gpu_object_array *objs,
1233 struct virtio_gpu_fence *fence)
1234{
1235 struct virtio_gpu_resource_create_3d *cmd_p;
1236 struct virtio_gpu_vbuffer *vbuf;
1237
1238 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1239 memset(cmd_p, 0, sizeof(*cmd_p));
1240 vbuf->objs = objs;
1241
1242 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
1243 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1244 cmd_p->format = cpu_to_le32(params->format);
1245 cmd_p->width = cpu_to_le32(params->width);
1246 cmd_p->height = cpu_to_le32(params->height);
1247
1248 cmd_p->target = cpu_to_le32(params->target);
1249 cmd_p->bind = cpu_to_le32(params->bind);
1250 cmd_p->depth = cpu_to_le32(params->depth);
1251 cmd_p->array_size = cpu_to_le32(params->array_size);
1252 cmd_p->last_level = cpu_to_le32(params->last_level);
1253 cmd_p->nr_samples = cpu_to_le32(params->nr_samples);
1254 cmd_p->flags = cpu_to_le32(params->flags);
1255
1256 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1257
1258 bo->created = true;
1259}
1260
1261void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
1262 uint32_t ctx_id,
1263 uint64_t offset, uint32_t level,
1264 uint32_t stride,
1265 uint32_t layer_stride,
1266 struct drm_virtgpu_3d_box *box,
1267 struct virtio_gpu_object_array *objs,
1268 struct virtio_gpu_fence *fence)
1269{
1270 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1271 struct virtio_gpu_transfer_host_3d *cmd_p;
1272 struct virtio_gpu_vbuffer *vbuf;
1273 bool use_dma_api = virtio_gpu_use_dma_api(vgdev->vdev);
1274
1275 if (virtio_gpu_is_shmem(bo) && use_dma_api)
1276 dma_sync_sgtable_for_device(vgdev->vdev->dev.parent,
1277 bo->base.sgt, DMA_TO_DEVICE);
1278
1279 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1280 memset(cmd_p, 0, sizeof(*cmd_p));
1281
1282 vbuf->objs = objs;
1283
1284 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
1285 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1286 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1287 convert_to_hw_box(&cmd_p->box, box);
1288 cmd_p->offset = cpu_to_le64(offset);
1289 cmd_p->level = cpu_to_le32(level);
1290 cmd_p->stride = cpu_to_le32(stride);
1291 cmd_p->layer_stride = cpu_to_le32(layer_stride);
1292
1293 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1294}
1295
1296void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
1297 uint32_t ctx_id,
1298 uint64_t offset, uint32_t level,
1299 uint32_t stride,
1300 uint32_t layer_stride,
1301 struct drm_virtgpu_3d_box *box,
1302 struct virtio_gpu_object_array *objs,
1303 struct virtio_gpu_fence *fence)
1304{
1305 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1306 struct virtio_gpu_transfer_host_3d *cmd_p;
1307 struct virtio_gpu_vbuffer *vbuf;
1308 bool use_dma_api = virtio_gpu_use_dma_api(vgdev->vdev);
1309
1310 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1311 memset(cmd_p, 0, sizeof(*cmd_p));
1312
1313 vbuf->objs = objs;
1314
1315 if (virtio_gpu_is_shmem(bo) && use_dma_api) {
1316 /*
1317 * The device writes only the requested box, so prime the
1318 * mapping with the current contents: otherwise the sync on
1319 * completion would hand back whatever a bounce buffer held for
1320 * the regions the device does not touch.
1321 */
1322 dma_sync_sgtable_for_device(vgdev->vdev->dev.parent,
1323 bo->base.sgt, DMA_TO_DEVICE);
1324 vbuf->sync_for_cpu = true;
1325 /*
1326 * Set under the reservation the caller holds, so a transfer
1327 * the other way cannot miss it and push the guest pages into
1328 * the mapping while the device still owns it.
1329 */
1330 WRITE_ONCE(bo->from_host_pending, true);
1331 }
1332
1333 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
1334 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1335 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1336 convert_to_hw_box(&cmd_p->box, box);
1337 cmd_p->offset = cpu_to_le64(offset);
1338 cmd_p->level = cpu_to_le32(level);
1339 cmd_p->stride = cpu_to_le32(stride);
1340 cmd_p->layer_stride = cpu_to_le32(layer_stride);
1341
1342 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1343}
1344
1345void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
1346 void *data, uint32_t data_size,
1347 uint32_t ctx_id,
1348 struct virtio_gpu_object_array *objs,
1349 struct virtio_gpu_fence *fence)
1350{
1351 struct virtio_gpu_cmd_submit *cmd_p;
1352 struct virtio_gpu_vbuffer *vbuf;
1353
1354 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1355 memset(cmd_p, 0, sizeof(*cmd_p));
1356
1357 vbuf->data_buf = data;
1358 vbuf->data_size = data_size;
1359 vbuf->objs = objs;
1360
1361 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
1362 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1363 cmd_p->size = cpu_to_le32(data_size);
1364
1365 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1366}
1367
1368void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
1369 struct virtio_gpu_object *obj,
1370 struct virtio_gpu_mem_entry *ents,
1371 unsigned int nents)
1372{
1373 if (obj->attached)
1374 return;
1375
1376 virtio_gpu_cmd_resource_attach_backing(vgdev, obj->hw_res_handle,
1377 ents, nents, NULL);
1378
1379 obj->attached = true;
1380}
1381
1382void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
1383 struct virtio_gpu_object *obj,
1384 struct virtio_gpu_fence *fence)
1385{
1386 if (!obj->attached)
1387 return;
1388
1389 virtio_gpu_cmd_resource_detach_backing(vgdev, obj->hw_res_handle,
1390 fence);
1391
1392 obj->attached = false;
1393}
1394
1395void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
1396 struct virtio_gpu_output *output)
1397{
1398 struct virtio_gpu_vbuffer *vbuf;
1399 struct virtio_gpu_update_cursor *cur_p;
1400
1401 output->cursor.pos.scanout_id = cpu_to_le32(output->index);
1402 cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf);
1403 memcpy(cur_p, &output->cursor, sizeof(output->cursor));
1404 virtio_gpu_queue_cursor(vgdev, vbuf);
1405}
1406
1407static void virtio_gpu_cmd_resource_uuid_cb(struct virtio_gpu_device *vgdev,
1408 struct virtio_gpu_vbuffer *vbuf)
1409{
1410 struct virtio_gpu_object *obj =
1411 gem_to_virtio_gpu_obj(vbuf->objs->objs[0]);
1412 struct virtio_gpu_resp_resource_uuid *resp =
1413 (struct virtio_gpu_resp_resource_uuid *)vbuf->resp_buf;
1414 uint32_t resp_type = le32_to_cpu(resp->hdr.type);
1415
1416 spin_lock(&vgdev->resource_export_lock);
1417 WARN_ON(obj->uuid_state != STATE_INITIALIZING);
1418
1419 if (resp_type == VIRTIO_GPU_RESP_OK_RESOURCE_UUID &&
1420 obj->uuid_state == STATE_INITIALIZING) {
1421 import_uuid(&obj->uuid, resp->uuid);
1422 obj->uuid_state = STATE_OK;
1423 } else {
1424 obj->uuid_state = STATE_ERR;
1425 }
1426 spin_unlock(&vgdev->resource_export_lock);
1427
1428 wake_up_all(&vgdev->resp_wq);
1429}
1430
1431int
1432virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
1433 struct virtio_gpu_object_array *objs)
1434{
1435 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1436 struct virtio_gpu_resource_assign_uuid *cmd_p;
1437 struct virtio_gpu_vbuffer *vbuf;
1438 struct virtio_gpu_resp_resource_uuid *resp_buf;
1439
1440 resp_buf = kzalloc_obj(*resp_buf);
1441 if (!resp_buf) {
1442 spin_lock(&vgdev->resource_export_lock);
1443 bo->uuid_state = STATE_ERR;
1444 spin_unlock(&vgdev->resource_export_lock);
1445 virtio_gpu_array_put_free(objs);
1446 return -ENOMEM;
1447 }
1448
1449 cmd_p = virtio_gpu_alloc_cmd_resp
1450 (vgdev, virtio_gpu_cmd_resource_uuid_cb, &vbuf, sizeof(*cmd_p),
1451 sizeof(struct virtio_gpu_resp_resource_uuid), resp_buf);
1452 memset(cmd_p, 0, sizeof(*cmd_p));
1453
1454 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID);
1455 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1456
1457 vbuf->objs = objs;
1458 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1459 return 0;
1460}
1461
1462static void virtio_gpu_cmd_resource_map_cb(struct virtio_gpu_device *vgdev,
1463 struct virtio_gpu_vbuffer *vbuf)
1464{
1465 struct virtio_gpu_object *bo =
1466 gem_to_virtio_gpu_obj(vbuf->objs->objs[0]);
1467 struct virtio_gpu_resp_map_info *resp =
1468 (struct virtio_gpu_resp_map_info *)vbuf->resp_buf;
1469 struct virtio_gpu_object_vram *vram = to_virtio_gpu_vram(bo);
1470 uint32_t resp_type = le32_to_cpu(resp->hdr.type);
1471
1472 spin_lock(&vgdev->host_visible_lock);
1473
1474 if (resp_type == VIRTIO_GPU_RESP_OK_MAP_INFO) {
1475 vram->map_info = resp->map_info;
1476 vram->map_state = STATE_OK;
1477 } else {
1478 vram->map_state = STATE_ERR;
1479 }
1480
1481 spin_unlock(&vgdev->host_visible_lock);
1482 wake_up_all(&vgdev->resp_wq);
1483}
1484
1485int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
1486 struct virtio_gpu_object_array *objs, uint64_t offset)
1487{
1488 struct virtio_gpu_resource_map_blob *cmd_p;
1489 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1490 struct virtio_gpu_vbuffer *vbuf;
1491 struct virtio_gpu_resp_map_info *resp_buf;
1492
1493 resp_buf = kzalloc_obj(*resp_buf);
1494 if (!resp_buf)
1495 return -ENOMEM;
1496
1497 cmd_p = virtio_gpu_alloc_cmd_resp
1498 (vgdev, virtio_gpu_cmd_resource_map_cb, &vbuf, sizeof(*cmd_p),
1499 sizeof(struct virtio_gpu_resp_map_info), resp_buf);
1500 memset(cmd_p, 0, sizeof(*cmd_p));
1501
1502 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB);
1503 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1504 cmd_p->offset = cpu_to_le64(offset);
1505 vbuf->objs = objs;
1506
1507 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1508 return 0;
1509}
1510
1511void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
1512 struct virtio_gpu_object *bo)
1513{
1514 struct virtio_gpu_resource_unmap_blob *cmd_p;
1515 struct virtio_gpu_vbuffer *vbuf;
1516
1517 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1518 memset(cmd_p, 0, sizeof(*cmd_p));
1519
1520 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB);
1521 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1522
1523 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1524}
1525
1526void
1527virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
1528 struct virtio_gpu_object *bo,
1529 struct virtio_gpu_object_params *params,
1530 struct virtio_gpu_mem_entry *ents,
1531 uint32_t nents)
1532{
1533 struct virtio_gpu_resource_create_blob *cmd_p;
1534 struct virtio_gpu_vbuffer *vbuf;
1535
1536 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1537 memset(cmd_p, 0, sizeof(*cmd_p));
1538
1539 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB);
1540 cmd_p->hdr.ctx_id = cpu_to_le32(params->ctx_id);
1541 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1542 cmd_p->blob_mem = cpu_to_le32(params->blob_mem);
1543 cmd_p->blob_flags = cpu_to_le32(params->blob_flags);
1544 cmd_p->blob_id = cpu_to_le64(params->blob_id);
1545 cmd_p->size = cpu_to_le64(params->size);
1546 cmd_p->nr_entries = cpu_to_le32(nents);
1547
1548 vbuf->data_buf = ents;
1549 vbuf->data_size = sizeof(*ents) * nents;
1550
1551 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1552 bo->created = true;
1553
1554 if (nents)
1555 bo->attached = true;
1556}
1557
1558void virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
1559 uint32_t scanout_id,
1560 struct virtio_gpu_object *bo,
1561 struct drm_framebuffer *fb,
1562 uint32_t width, uint32_t height,
1563 uint32_t x, uint32_t y)
1564{
1565 uint32_t i;
1566 struct virtio_gpu_set_scanout_blob *cmd_p;
1567 struct virtio_gpu_vbuffer *vbuf;
1568 uint32_t format = virtio_gpu_translate_format(fb->format->format);
1569
1570 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1571 memset(cmd_p, 0, sizeof(*cmd_p));
1572
1573 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT_BLOB);
1574 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1575 cmd_p->scanout_id = cpu_to_le32(scanout_id);
1576
1577 cmd_p->format = cpu_to_le32(format);
1578 cmd_p->width = cpu_to_le32(fb->width);
1579 cmd_p->height = cpu_to_le32(fb->height);
1580
1581 for (i = 0; i < 4; i++) {
1582 cmd_p->strides[i] = cpu_to_le32(fb->pitches[i]);
1583 cmd_p->offsets[i] = cpu_to_le32(fb->offsets[i]);
1584 }
1585
1586 cmd_p->r.width = cpu_to_le32(width);
1587 cmd_p->r.height = cpu_to_le32(height);
1588 cmd_p->r.x = cpu_to_le32(x);
1589 cmd_p->r.y = cpu_to_le32(y);
1590
1591 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1592}