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| 2 | |
| 3 | * Copyright © 2022 Intel Corporation
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| 5 |
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| 6 | #ifndef _XE_PCODE_API_H_
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| 7 | #define _XE_PCODE_API_H_
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| 8 |
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| 9 |
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| 10 |
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| 11 | #include "regs/xe_reg_defs.h"
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| 12 |
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| 13 | #define PCODE_MAILBOX XE_REG(0x138124)
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| 14 | #define PCODE_READY REG_BIT(31)
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| 15 | #define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
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| 16 | #define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
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| 17 | #define PCODE_MB_COMMAND REG_GENMASK(7, 0)
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| 18 | #define PCODE_ERROR_MASK 0xFF
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| 19 | #define PCODE_SUCCESS 0x0
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| 20 | #define PCODE_ILLEGAL_CMD 0x1
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| 21 | #define PCODE_TIMEOUT 0x2
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| 22 | #define PCODE_ILLEGAL_DATA 0x3
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| 23 | #define PCODE_ILLEGAL_SUBCOMMAND 0x4
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| 24 | #define PCODE_LOCKED 0x6
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| 25 | #define PCODE_GT_RATIO_OUT_OF_RANGE 0x10
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| 26 | #define PCODE_REJECTED 0x11
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| 27 |
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| 28 | #define PCODE_DATA0 XE_REG(0x138128)
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| 29 | #define PCODE_DATA1 XE_REG(0x13812C)
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| 30 |
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| 31 |
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| 32 | #define PCODE_WRITE_MIN_FREQ_TABLE 0x8
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| 33 | #define PCODE_READ_MIN_FREQ_TABLE 0x9
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| 34 | #define PCODE_FREQ_RING_RATIO_SHIFT 16
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| 35 |
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| 36 |
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| 37 | #define DGFX_PCODE_STATUS 0x7E
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| 38 | #define DGFX_GET_INIT_STATUS 0x0
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| 39 | #define DGFX_INIT_STATUS_COMPLETE 0x1
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| 40 | #define DGFX_LINK_DOWNGRADE_STATUS REG_BIT(31)
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| 41 |
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| 42 | #define PCODE_POWER_SETUP 0x7C
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| 43 | #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
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| 44 | #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
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| 45 | #define POWER_SETUP_I1_WATTS REG_BIT(31)
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| 46 | #define POWER_SETUP_I1_SHIFT 6
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| 47 | #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
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| 48 |
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| 49 | #define READ_PSYSGPU_POWER_LIMIT 0x6
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| 50 | #define WRITE_PSYSGPU_POWER_LIMIT 0x7
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| 51 | #define READ_PACKAGE_POWER_LIMIT 0x8
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| 52 | #define WRITE_PACKAGE_POWER_LIMIT 0x9
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| 53 | #define READ_PL_FROM_PCODE 0x0
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| 54 | #define READ_PL_FROM_FW 0x1
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| 55 | #define READ_PL_ACCEPTED 0x2
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| 56 |
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| 57 | #define PCODE_THERMAL_INFO 0x25
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| 58 | #define READ_THERMAL_LIMITS 0x0
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| 59 | #define READ_THERMAL_CONFIG 0x1
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| 60 | #define READ_THERMAL_DATA 0x2
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| 61 | #define PCIE_SENSOR_GROUP_ID 0x2
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| 62 | #define PCIE_SENSOR_MASK REG_GENMASK(31, 16)
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| 63 |
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| 64 | #define PCODE_LATE_BINDING 0x5C
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| 65 | #define GET_CAPABILITY_STATUS 0x0
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| 66 | #define V1_FAN_SUPPORTED REG_BIT(0)
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| 67 | #define VR_PARAMS_SUPPORTED REG_BIT(3)
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| 68 | #define V1_FAN_PROVISIONED REG_BIT(16)
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| 69 | #define VR_PARAMS_PROVISIONED REG_BIT(19)
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| 70 | #define GET_VERSION_LOW 0x1
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| 71 | #define GET_VERSION_HIGH 0x2
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| 72 | #define MAJOR_VERSION_MASK REG_GENMASK(31, 16)
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| 73 | #define MINOR_VERSION_MASK REG_GENMASK(15, 0)
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| 74 | #define HOTFIX_VERSION_MASK REG_GENMASK(31, 16)
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| 75 | #define BUILD_VERSION_MASK REG_GENMASK(15, 0)
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| 76 | #define FAN_TABLE 1
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| 77 | #define VR_CONFIG 2
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| 78 |
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| 79 | #define PCODE_FREQUENCY_CONFIG 0x6e
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| 80 |
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| 81 | #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
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| 82 | #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
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| 83 |
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| 84 | #define PCODE_MBOX_DOMAIN_HBM 0x2
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| 85 |
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| 86 | #define FAN_SPEED_CONTROL 0x7D
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| 87 | #define FSC_READ_NUM_FANS 0x4
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| 88 |
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| 89 | #define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))
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| 90 |
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| 91 | #define BREADCRUMB_VERSION REG_GENMASK(31, 29)
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| 92 | #define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)
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| 93 | #define OVERFLOW_REG_OFFSET REG_GENMASK(14, 12)
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| 94 | #define HISTORY_TRACKING REG_BIT(11)
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| 95 | #define OVERFLOW_SUPPORT REG_BIT(10)
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| 96 | #define AUXINFO_SUPPORT REG_BIT(9)
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| 97 | #define FDO_MODE REG_BIT(4)
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| 98 | #define BOOT_STATUS REG_GENMASK(3, 1)
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| 99 | #define CRITICAL_FAILURE 4
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| 100 | #define NON_CRITICAL_FAILURE 7
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| 101 |
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| 102 |
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| 103 | #define AUXINFO_HISTORY_OFFSET REG_GENMASK(31, 29)
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| 104 |
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| 105 | #define BMG_PCIE_CAP XE_REG(0x138340)
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| 106 | #define LINK_DOWNGRADE REG_GENMASK(1, 0)
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| 107 | #define DOWNGRADE_CAPABLE 2
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| 108 |
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| 109 | #endif
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