projects/linux·blob master · refs

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1// SPDX-License-Identifier: GPL-2.0
2// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3
4use kernel::prelude::*;
5
6use crate::{
7 driver::Bar0,
8 gpu::{
9 Architecture,
10 Chipset, //
11 },
12};
13
14mod ga100;
15mod ga102;
16mod gb100;
17mod gb202;
18mod gh100;
19mod tu102;
20
21pub(crate) trait FbHal {
22 /// Returns the address of the currently-registered sysmem flush page.
23 fn read_sysmem_flush_page(&self, bar: Bar0<'_>) -> u64;
24
25 /// Register `addr` as the address of the sysmem flush page.
26 ///
27 /// This might fail if the address is too large for the receiving register.
28 fn write_sysmem_flush_page(&self, bar: Bar0<'_>, addr: u64) -> Result;
29
30 /// Returns `true` is display is supported.
31 fn supports_display(&self, bar: Bar0<'_>) -> bool;
32
33 /// Returns the VRAM size, in bytes.
34 fn vidmem_size(&self, bar: Bar0<'_>) -> u64;
35
36 /// Returns the amount of VRAM to reserve for the PMU.
37 fn pmu_reserved_size(&self) -> u32;
38
39 /// Returns the non-WPR heap size for this chipset, in bytes.
40 fn non_wpr_heap_size(&self) -> u64;
41
42 /// Returns the FRTS size, in bytes.
43 fn frts_size(&self) -> u64;
44}
45
46/// Returns the HAL corresponding to `chipset`.
47pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal {
48 match chipset.arch() {
49 Architecture::Turing => tu102::TU102_HAL,
50 Architecture::Ampere if chipset == Chipset::GA100 => ga100::GA100_HAL,
51 Architecture::Ampere | Architecture::Ada => ga102::GA102_HAL,
52 Architecture::Hopper => gh100::GH100_HAL,
53 Architecture::BlackwellGB10x => gb100::GB100_HAL,
54 Architecture::BlackwellGB20x => gb202::GB202_HAL,
55 }
56}