| 1 |
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| 2 | |
| 3 | * Defines for the EMIF driver
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| 4 | *
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| 5 | * Copyright (C) 2012 Texas Instruments, Inc.
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| 6 | *
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| 7 | * Benoit Cousson ([email protected])
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| 8 |
|
| 9 | #ifndef __EMIF_H
|
| 10 | #define __EMIF_H
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| 11 |
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| 12 | |
| 13 | * Maximum number of different frequencies supported by EMIF driver
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| 14 | * Determines the number of entries in the pointer array for register
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| 15 | * cache
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| 16 |
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| 17 | #define EMIF_MAX_NUM_FREQUENCIES 6
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| 18 |
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| 19 |
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| 20 | #define DDR_VOLTAGE_STABLE 0
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| 21 | #define DDR_VOLTAGE_RAMPING 1
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| 22 |
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| 23 |
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| 24 | #define EMIF_NORMAL_TIMINGS 0
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| 25 | #define EMIF_DERATED_TIMINGS 1
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| 26 |
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| 27 |
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| 28 | #define EMIF_READ_IDLE_LEN_VAL 5
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| 29 |
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| 30 | |
| 31 | * forced read idle interval to be used when voltage
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| 32 | * is changed as part of DVFS/DPS - 1ms
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| 33 |
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| 34 | #define READ_IDLE_INTERVAL_DVFS (1*1000000)
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| 35 |
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| 36 | |
| 37 | * Forced read idle interval to be used when voltage is stable
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| 38 | * 50us - or maximum value will do
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| 39 |
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| 40 | #define READ_IDLE_INTERVAL_NORMAL (50*1000000)
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| 41 |
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| 42 |
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| 43 | #define DLL_CALIB_INTERVAL_DVFS (1*1000000)
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| 44 |
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| 45 | #define DLL_CALIB_ACK_WAIT_VAL 5
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| 46 |
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| 47 |
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| 48 | #define EMIF_ZQCS_INTERVAL_US (50*1000)
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| 49 |
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| 50 | #define ZQ_SFEXITEN_ENABLE 1
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| 51 | |
| 52 | * ZQ Calibration simultaneously on both chip-selects:
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| 53 | * Needs one calibration resistor per CS
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| 54 |
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| 55 | #define ZQ_DUALCALEN_DISABLE 0
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| 56 | #define ZQ_DUALCALEN_ENABLE 1
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| 57 |
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| 58 | #define T_ZQCS_DEFAULT_NS 90
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| 59 | #define T_ZQCL_DEFAULT_NS 360
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| 60 | #define T_ZQINIT_DEFAULT_NS 1000
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| 61 |
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| 62 |
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| 63 | #define DPD_DISABLE 0
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| 64 | #define DPD_ENABLE 1
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| 65 |
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| 66 | |
| 67 | * Default values for the low-power entry to be used if not provided by user.
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| 68 | * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
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| 69 | * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
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| 70 |
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| 71 | #define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
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| 72 | #define EMIF_LP_MODE_TIMEOUT_POWER 512
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| 73 | #define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
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| 74 |
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| 75 |
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| 76 | #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
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| 77 | #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
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| 78 | #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
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| 79 | #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
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| 80 |
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| 81 |
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| 82 | #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
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| 83 | #define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
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| 84 |
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| 85 |
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| 86 | #define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
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| 87 |
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| 88 | #define EMIF_T_CSTA 3
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| 89 | #define EMIF_T_PDLL_UL 128
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| 90 |
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| 91 |
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| 92 | #define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
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| 93 | #define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
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| 94 | #define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
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| 95 | #define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
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| 96 | #define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
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| 97 | #define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
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| 98 | #define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
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| 99 | #define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
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| 100 | #define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
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| 101 | #define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
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| 102 | #define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
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| 103 | #define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
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| 104 | #define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
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| 105 | #define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
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| 106 | #define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
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| 107 | #define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
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| 108 | #define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
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| 109 | #define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
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| 110 | #define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
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| 111 | #define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
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| 112 | #define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
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| 113 |
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| 114 | #define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
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| 115 |
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| 116 |
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| 117 | #define EMIF_MODULE_ID_AND_REVISION 0x0000
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| 118 | #define EMIF_STATUS 0x0004
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| 119 | #define EMIF_SDRAM_CONFIG 0x0008
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| 120 | #define EMIF_SDRAM_CONFIG_2 0x000c
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| 121 | #define EMIF_SDRAM_REFRESH_CONTROL 0x0010
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| 122 | #define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
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| 123 | #define EMIF_SDRAM_TIMING_1 0x0018
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| 124 | #define EMIF_SDRAM_TIMING_1_SHDW 0x001c
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| 125 | #define EMIF_SDRAM_TIMING_2 0x0020
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| 126 | #define EMIF_SDRAM_TIMING_2_SHDW 0x0024
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| 127 | #define EMIF_SDRAM_TIMING_3 0x0028
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| 128 | #define EMIF_SDRAM_TIMING_3_SHDW 0x002c
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| 129 | #define EMIF_LPDDR2_NVM_TIMING 0x0030
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| 130 | #define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
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| 131 | #define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
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| 132 | #define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
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| 133 | #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
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| 134 | #define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
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| 135 | #define EMIF_OCP_CONFIG 0x0054
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| 136 | #define EMIF_OCP_CONFIG_VALUE_1 0x0058
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| 137 | #define EMIF_OCP_CONFIG_VALUE_2 0x005c
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| 138 | #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
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| 139 | #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
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| 140 | #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
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| 141 | #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
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| 142 | #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
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| 143 | #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
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| 144 | #define EMIF_PERFORMANCE_COUNTER_1 0x0080
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| 145 | #define EMIF_PERFORMANCE_COUNTER_2 0x0084
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| 146 | #define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
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| 147 | #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
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| 148 | #define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
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| 149 | #define EMIF_MISC_REG 0x0094
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| 150 | #define EMIF_DLL_CALIB_CTRL 0x0098
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| 151 | #define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
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| 152 | #define EMIF_END_OF_INTERRUPT 0x00a0
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| 153 | #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
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| 154 | #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
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| 155 | #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
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| 156 | #define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
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| 157 | #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
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| 158 | #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
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| 159 | #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
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| 160 | #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
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| 161 | #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
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| 162 | #define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
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| 163 | #define EMIF_OCP_ERROR_LOG 0x00d0
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| 164 | #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
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| 165 | #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
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| 166 | #define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
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| 167 | #define EMIF_DDR_PHY_CTRL_1 0x00e4
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| 168 | #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
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| 169 | #define EMIF_DDR_PHY_CTRL_2 0x00ec
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| 170 | #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
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| 171 | #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
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| 172 | #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
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| 173 | #define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
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| 174 | #define EMIF_COS_CONFIG 0x0124
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| 175 | #define EMIF_PHY_STATUS_1 0x0140
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| 176 | #define EMIF_PHY_STATUS_2 0x0144
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| 177 | #define EMIF_PHY_STATUS_3 0x0148
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| 178 | #define EMIF_PHY_STATUS_4 0x014c
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| 179 | #define EMIF_PHY_STATUS_5 0x0150
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| 180 | #define EMIF_PHY_STATUS_6 0x0154
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| 181 | #define EMIF_PHY_STATUS_7 0x0158
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| 182 | #define EMIF_PHY_STATUS_8 0x015c
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| 183 | #define EMIF_PHY_STATUS_9 0x0160
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| 184 | #define EMIF_PHY_STATUS_10 0x0164
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| 185 | #define EMIF_PHY_STATUS_11 0x0168
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| 186 | #define EMIF_PHY_STATUS_12 0x016c
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| 187 | #define EMIF_PHY_STATUS_13 0x0170
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| 188 | #define EMIF_PHY_STATUS_14 0x0174
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| 189 | #define EMIF_PHY_STATUS_15 0x0178
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| 190 | #define EMIF_PHY_STATUS_16 0x017c
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| 191 | #define EMIF_PHY_STATUS_17 0x0180
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| 192 | #define EMIF_PHY_STATUS_18 0x0184
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| 193 | #define EMIF_PHY_STATUS_19 0x0188
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| 194 | #define EMIF_PHY_STATUS_20 0x018c
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| 195 | #define EMIF_PHY_STATUS_21 0x0190
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| 196 | #define EMIF_EXT_PHY_CTRL_1 0x0200
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| 197 | #define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
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| 198 | #define EMIF_EXT_PHY_CTRL_2 0x0208
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| 199 | #define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
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| 200 | #define EMIF_EXT_PHY_CTRL_3 0x0210
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| 201 | #define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
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| 202 | #define EMIF_EXT_PHY_CTRL_4 0x0218
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| 203 | #define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
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| 204 | #define EMIF_EXT_PHY_CTRL_5 0x0220
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| 205 | #define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
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| 206 | #define EMIF_EXT_PHY_CTRL_6 0x0228
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| 207 | #define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
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| 208 | #define EMIF_EXT_PHY_CTRL_7 0x0230
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| 209 | #define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
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| 210 | #define EMIF_EXT_PHY_CTRL_8 0x0238
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| 211 | #define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
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| 212 | #define EMIF_EXT_PHY_CTRL_9 0x0240
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| 213 | #define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
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| 214 | #define EMIF_EXT_PHY_CTRL_10 0x0248
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| 215 | #define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
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| 216 | #define EMIF_EXT_PHY_CTRL_11 0x0250
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| 217 | #define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
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| 218 | #define EMIF_EXT_PHY_CTRL_12 0x0258
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| 219 | #define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
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| 220 | #define EMIF_EXT_PHY_CTRL_13 0x0260
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| 221 | #define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
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| 222 | #define EMIF_EXT_PHY_CTRL_14 0x0268
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| 223 | #define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
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| 224 | #define EMIF_EXT_PHY_CTRL_15 0x0270
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| 225 | #define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
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| 226 | #define EMIF_EXT_PHY_CTRL_16 0x0278
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| 227 | #define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
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| 228 | #define EMIF_EXT_PHY_CTRL_17 0x0280
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| 229 | #define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
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| 230 | #define EMIF_EXT_PHY_CTRL_18 0x0288
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| 231 | #define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
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| 232 | #define EMIF_EXT_PHY_CTRL_19 0x0290
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| 233 | #define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
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| 234 | #define EMIF_EXT_PHY_CTRL_20 0x0298
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| 235 | #define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
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| 236 | #define EMIF_EXT_PHY_CTRL_21 0x02a0
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| 237 | #define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
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| 238 | #define EMIF_EXT_PHY_CTRL_22 0x02a8
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| 239 | #define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
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| 240 | #define EMIF_EXT_PHY_CTRL_23 0x02b0
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| 241 | #define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
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| 242 | #define EMIF_EXT_PHY_CTRL_24 0x02b8
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| 243 | #define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
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| 244 | #define EMIF_EXT_PHY_CTRL_25 0x02c0
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| 245 | #define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
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| 246 | #define EMIF_EXT_PHY_CTRL_26 0x02c8
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| 247 | #define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
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| 248 | #define EMIF_EXT_PHY_CTRL_27 0x02d0
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| 249 | #define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
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| 250 | #define EMIF_EXT_PHY_CTRL_28 0x02d8
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| 251 | #define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
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| 252 | #define EMIF_EXT_PHY_CTRL_29 0x02e0
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| 253 | #define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
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| 254 | #define EMIF_EXT_PHY_CTRL_30 0x02e8
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| 255 | #define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
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| 256 |
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| 257 |
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| 258 |
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| 259 |
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| 260 | #define SCHEME_SHIFT 30
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| 261 | #define SCHEME_MASK (0x3 << 30)
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| 262 | #define MODULE_ID_SHIFT 16
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| 263 | #define MODULE_ID_MASK (0xfff << 16)
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| 264 | #define RTL_VERSION_SHIFT 11
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| 265 | #define RTL_VERSION_MASK (0x1f << 11)
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| 266 | #define MAJOR_REVISION_SHIFT 8
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| 267 | #define MAJOR_REVISION_MASK (0x7 << 8)
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| 268 | #define MINOR_REVISION_SHIFT 0
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| 269 | #define MINOR_REVISION_MASK (0x3f << 0)
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| 270 |
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| 271 |
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| 272 | #define BE_SHIFT 31
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| 273 | #define BE_MASK (1 << 31)
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| 274 | #define DUAL_CLK_MODE_SHIFT 30
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| 275 | #define DUAL_CLK_MODE_MASK (1 << 30)
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| 276 | #define FAST_INIT_SHIFT 29
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| 277 | #define FAST_INIT_MASK (1 << 29)
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| 278 | #define RDLVLGATETO_SHIFT 6
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| 279 | #define RDLVLGATETO_MASK (1 << 6)
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| 280 | #define RDLVLTO_SHIFT 5
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| 281 | #define RDLVLTO_MASK (1 << 5)
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| 282 | #define WRLVLTO_SHIFT 4
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| 283 | #define WRLVLTO_MASK (1 << 4)
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| 284 | #define PHY_DLL_READY_SHIFT 2
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| 285 | #define PHY_DLL_READY_MASK (1 << 2)
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| 286 |
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| 287 |
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| 288 | #define SDRAM_TYPE_SHIFT 29
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| 289 | #define SDRAM_TYPE_MASK (0x7 << 29)
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| 290 | #define IBANK_POS_SHIFT 27
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| 291 | #define IBANK_POS_MASK (0x3 << 27)
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| 292 | #define DDR_TERM_SHIFT 24
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| 293 | #define DDR_TERM_MASK (0x7 << 24)
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| 294 | #define DDR2_DDQS_SHIFT 23
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| 295 | #define DDR2_DDQS_MASK (1 << 23)
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| 296 | #define DYN_ODT_SHIFT 21
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| 297 | #define DYN_ODT_MASK (0x3 << 21)
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| 298 | #define DDR_DISABLE_DLL_SHIFT 20
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| 299 | #define DDR_DISABLE_DLL_MASK (1 << 20)
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| 300 | #define SDRAM_DRIVE_SHIFT 18
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| 301 | #define SDRAM_DRIVE_MASK (0x3 << 18)
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| 302 | #define CWL_SHIFT 16
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| 303 | #define CWL_MASK (0x3 << 16)
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| 304 | #define NARROW_MODE_SHIFT 14
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| 305 | #define NARROW_MODE_MASK (0x3 << 14)
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| 306 | #define CL_SHIFT 10
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| 307 | #define CL_MASK (0xf << 10)
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| 308 | #define ROWSIZE_SHIFT 7
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| 309 | #define ROWSIZE_MASK (0x7 << 7)
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| 310 | #define IBANK_SHIFT 4
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| 311 | #define IBANK_MASK (0x7 << 4)
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| 312 | #define EBANK_SHIFT 3
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| 313 | #define EBANK_MASK (1 << 3)
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| 314 | #define PAGESIZE_SHIFT 0
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| 315 | #define PAGESIZE_MASK (0x7 << 0)
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| 316 |
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| 317 |
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| 318 | #define CS1NVMEN_SHIFT 30
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| 319 | #define CS1NVMEN_MASK (1 << 30)
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| 320 | #define EBANK_POS_SHIFT 27
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| 321 | #define EBANK_POS_MASK (1 << 27)
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| 322 | #define RDBNUM_SHIFT 4
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| 323 | #define RDBNUM_MASK (0x3 << 4)
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| 324 | #define RDBSIZE_SHIFT 0
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| 325 | #define RDBSIZE_MASK (0x7 << 0)
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| 326 |
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| 327 |
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| 328 | #define INITREF_DIS_SHIFT 31
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| 329 | #define INITREF_DIS_MASK (1 << 31)
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| 330 | #define SRT_SHIFT 29
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| 331 | #define SRT_MASK (1 << 29)
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| 332 | #define ASR_SHIFT 28
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| 333 | #define ASR_MASK (1 << 28)
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| 334 | #define PASR_SHIFT 24
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| 335 | #define PASR_MASK (0x7 << 24)
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| 336 | #define REFRESH_RATE_SHIFT 0
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| 337 | #define REFRESH_RATE_MASK (0xffff << 0)
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| 338 |
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| 339 |
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| 340 | #define T_RTW_SHIFT 29
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| 341 | #define T_RTW_MASK (0x7 << 29)
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| 342 | #define T_RP_SHIFT 25
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| 343 | #define T_RP_MASK (0xf << 25)
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| 344 | #define T_RCD_SHIFT 21
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| 345 | #define T_RCD_MASK (0xf << 21)
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| 346 | #define T_WR_SHIFT 17
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| 347 | #define T_WR_MASK (0xf << 17)
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| 348 | #define T_RAS_SHIFT 12
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| 349 | #define T_RAS_MASK (0x1f << 12)
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| 350 | #define T_RC_SHIFT 6
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| 351 | #define T_RC_MASK (0x3f << 6)
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| 352 | #define T_RRD_SHIFT 3
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| 353 | #define T_RRD_MASK (0x7 << 3)
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| 354 | #define T_WTR_SHIFT 0
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| 355 | #define T_WTR_MASK (0x7 << 0)
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| 356 |
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| 357 |
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| 358 | #define T_XP_SHIFT 28
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| 359 | #define T_XP_MASK (0x7 << 28)
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| 360 | #define T_ODT_SHIFT 25
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| 361 | #define T_ODT_MASK (0x7 << 25)
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| 362 | #define T_XSNR_SHIFT 16
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| 363 | #define T_XSNR_MASK (0x1ff << 16)
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| 364 | #define T_XSRD_SHIFT 6
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| 365 | #define T_XSRD_MASK (0x3ff << 6)
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| 366 | #define T_RTP_SHIFT 3
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| 367 | #define T_RTP_MASK (0x7 << 3)
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| 368 | #define T_CKE_SHIFT 0
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| 369 | #define T_CKE_MASK (0x7 << 0)
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| 370 |
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| 371 |
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| 372 | #define T_PDLL_UL_SHIFT 28
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| 373 | #define T_PDLL_UL_MASK (0xf << 28)
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| 374 | #define T_CSTA_SHIFT 24
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| 375 | #define T_CSTA_MASK (0xf << 24)
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| 376 | #define T_CKESR_SHIFT 21
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| 377 | #define T_CKESR_MASK (0x7 << 21)
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| 378 | #define ZQ_ZQCS_SHIFT 15
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| 379 | #define ZQ_ZQCS_MASK (0x3f << 15)
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| 380 | #define T_TDQSCKMAX_SHIFT 13
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| 381 | #define T_TDQSCKMAX_MASK (0x3 << 13)
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| 382 | #define T_RFC_SHIFT 4
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| 383 | #define T_RFC_MASK (0x1ff << 4)
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| 384 | #define T_RAS_MAX_SHIFT 0
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| 385 | #define T_RAS_MAX_MASK (0xf << 0)
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| 386 |
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| 387 |
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| 388 | #define PD_TIM_SHIFT 12
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| 389 | #define PD_TIM_MASK (0xf << 12)
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| 390 | #define DPD_EN_SHIFT 11
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| 391 | #define DPD_EN_MASK (1 << 11)
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| 392 | #define LP_MODE_SHIFT 8
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| 393 | #define LP_MODE_MASK (0x7 << 8)
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| 394 | #define SR_TIM_SHIFT 4
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| 395 | #define SR_TIM_MASK (0xf << 4)
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| 396 | #define CS_TIM_SHIFT 0
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| 397 | #define CS_TIM_MASK (0xf << 0)
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| 398 |
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| 399 |
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| 400 | #define VALUE_0_SHIFT 0
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| 401 | #define VALUE_0_MASK (0x7f << 0)
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| 402 |
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| 403 |
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| 404 | #define CS_SHIFT 31
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| 405 | #define CS_MASK (1 << 31)
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| 406 | #define REFRESH_EN_SHIFT 30
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| 407 | #define REFRESH_EN_MASK (1 << 30)
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| 408 | #define ADDRESS_SHIFT 0
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| 409 | #define ADDRESS_MASK (0xff << 0)
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| 410 |
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| 411 |
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| 412 | #define SYS_THRESH_MAX_SHIFT 24
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| 413 | #define SYS_THRESH_MAX_MASK (0xf << 24)
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| 414 | #define MPU_THRESH_MAX_SHIFT 20
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| 415 | #define MPU_THRESH_MAX_MASK (0xf << 20)
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| 416 | #define LL_THRESH_MAX_SHIFT 16
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| 417 | #define LL_THRESH_MAX_MASK (0xf << 16)
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| 418 |
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| 419 |
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| 420 | #define COUNTER1_SHIFT 0
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| 421 | #define COUNTER1_MASK (0xffffffff << 0)
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| 422 |
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| 423 |
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| 424 | #define COUNTER2_SHIFT 0
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| 425 | #define COUNTER2_MASK (0xffffffff << 0)
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| 426 |
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| 427 |
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| 428 | #define CNTR2_MCONNID_EN_SHIFT 31
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| 429 | #define CNTR2_MCONNID_EN_MASK (1 << 31)
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| 430 | #define CNTR2_REGION_EN_SHIFT 30
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| 431 | #define CNTR2_REGION_EN_MASK (1 << 30)
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| 432 | #define CNTR2_CFG_SHIFT 16
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| 433 | #define CNTR2_CFG_MASK (0xf << 16)
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| 434 | #define CNTR1_MCONNID_EN_SHIFT 15
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| 435 | #define CNTR1_MCONNID_EN_MASK (1 << 15)
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| 436 | #define CNTR1_REGION_EN_SHIFT 14
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| 437 | #define CNTR1_REGION_EN_MASK (1 << 14)
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| 438 | #define CNTR1_CFG_SHIFT 0
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| 439 | #define CNTR1_CFG_MASK (0xf << 0)
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| 440 |
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| 441 |
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| 442 | #define MCONNID2_SHIFT 24
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| 443 | #define MCONNID2_MASK (0xff << 24)
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| 444 | #define REGION_SEL2_SHIFT 16
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| 445 | #define REGION_SEL2_MASK (0x3 << 16)
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| 446 | #define MCONNID1_SHIFT 8
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| 447 | #define MCONNID1_MASK (0xff << 8)
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| 448 | #define REGION_SEL1_SHIFT 0
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| 449 | #define REGION_SEL1_MASK (0x3 << 0)
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| 450 |
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| 451 |
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| 452 | #define TOTAL_TIME_SHIFT 0
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| 453 | #define TOTAL_TIME_MASK (0xffffffff << 0)
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| 454 |
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| 455 |
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| 456 | #define ACK_WAIT_SHIFT 16
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| 457 | #define ACK_WAIT_MASK (0xf << 16)
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| 458 | #define DLL_CALIB_INTERVAL_SHIFT 0
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| 459 | #define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
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| 460 |
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| 461 |
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| 462 | #define EOI_SHIFT 0
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| 463 | #define EOI_MASK (1 << 0)
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| 464 |
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| 465 |
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| 466 | #define DNV_SYS_SHIFT 2
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| 467 | #define DNV_SYS_MASK (1 << 2)
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| 468 | #define TA_SYS_SHIFT 1
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| 469 | #define TA_SYS_MASK (1 << 1)
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| 470 | #define ERR_SYS_SHIFT 0
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| 471 | #define ERR_SYS_MASK (1 << 0)
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| 472 |
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| 473 |
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| 474 | #define DNV_LL_SHIFT 2
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| 475 | #define DNV_LL_MASK (1 << 2)
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| 476 | #define TA_LL_SHIFT 1
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| 477 | #define TA_LL_MASK (1 << 1)
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| 478 | #define ERR_LL_SHIFT 0
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| 479 | #define ERR_LL_MASK (1 << 0)
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| 480 |
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| 481 |
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| 482 | #define EN_DNV_SYS_SHIFT 2
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| 483 | #define EN_DNV_SYS_MASK (1 << 2)
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| 484 | #define EN_TA_SYS_SHIFT 1
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| 485 | #define EN_TA_SYS_MASK (1 << 1)
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| 486 | #define EN_ERR_SYS_SHIFT 0
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| 487 | #define EN_ERR_SYS_MASK (1 << 0)
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| 488 |
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| 489 |
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| 490 | #define EN_DNV_LL_SHIFT 2
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| 491 | #define EN_DNV_LL_MASK (1 << 2)
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| 492 | #define EN_TA_LL_SHIFT 1
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| 493 | #define EN_TA_LL_MASK (1 << 1)
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| 494 | #define EN_ERR_LL_SHIFT 0
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| 495 | #define EN_ERR_LL_MASK (1 << 0)
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| 496 |
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| 497 |
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| 498 | #define ZQ_CS1EN_SHIFT 31
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| 499 | #define ZQ_CS1EN_MASK (1 << 31)
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| 500 | #define ZQ_CS0EN_SHIFT 30
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| 501 | #define ZQ_CS0EN_MASK (1 << 30)
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| 502 | #define ZQ_DUALCALEN_SHIFT 29
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| 503 | #define ZQ_DUALCALEN_MASK (1 << 29)
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| 504 | #define ZQ_SFEXITEN_SHIFT 28
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| 505 | #define ZQ_SFEXITEN_MASK (1 << 28)
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| 506 | #define ZQ_ZQINIT_MULT_SHIFT 18
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| 507 | #define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
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| 508 | #define ZQ_ZQCL_MULT_SHIFT 16
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| 509 | #define ZQ_ZQCL_MULT_MASK (0x3 << 16)
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| 510 | #define ZQ_REFINTERVAL_SHIFT 0
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| 511 | #define ZQ_REFINTERVAL_MASK (0xffff << 0)
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| 512 |
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| 513 |
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| 514 | #define TA_CS1EN_SHIFT 31
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| 515 | #define TA_CS1EN_MASK (1 << 31)
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| 516 | #define TA_CS0EN_SHIFT 30
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| 517 | #define TA_CS0EN_MASK (1 << 30)
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| 518 | #define TA_SFEXITEN_SHIFT 28
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| 519 | #define TA_SFEXITEN_MASK (1 << 28)
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| 520 | #define TA_DEVWDT_SHIFT 26
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| 521 | #define TA_DEVWDT_MASK (0x3 << 26)
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| 522 | #define TA_DEVCNT_SHIFT 24
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| 523 | #define TA_DEVCNT_MASK (0x3 << 24)
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| 524 | #define TA_REFINTERVAL_SHIFT 0
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| 525 | #define TA_REFINTERVAL_MASK (0x3fffff << 0)
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| 526 |
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| 527 |
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| 528 | #define MADDRSPACE_SHIFT 14
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| 529 | #define MADDRSPACE_MASK (0x3 << 14)
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| 530 | #define MBURSTSEQ_SHIFT 11
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| 531 | #define MBURSTSEQ_MASK (0x7 << 11)
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| 532 | #define MCMD_SHIFT 8
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| 533 | #define MCMD_MASK (0x7 << 8)
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| 534 | #define MCONNID_SHIFT 0
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| 535 | #define MCONNID_MASK (0xff << 0)
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| 536 |
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| 537 |
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| 538 | #define RDWRLVLFULL_START 0x80000000
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| 539 |
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| 540 |
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| 541 | #define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
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| 542 | #define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
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| 543 | #define READ_LATENCY_SHIFT_4D 0
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| 544 | #define READ_LATENCY_MASK_4D (0xf << 0)
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| 545 |
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| 546 |
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| 547 | #define DLL_HALF_DELAY_SHIFT_4D5 21
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| 548 | #define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
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| 549 | #define READ_LATENCY_SHIFT_4D5 0
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| 550 | #define READ_LATENCY_MASK_4D5 (0x1f << 0)
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| 551 |
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| 552 |
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| 553 | #define DDR_PHY_CTRL_1_SHDW_SHIFT 5
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| 554 | #define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
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| 555 | #define READ_LATENCY_SHDW_SHIFT 0
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| 556 | #define READ_LATENCY_SHDW_MASK (0x1f << 0)
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| 557 |
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| 558 | #define EMIF_SRAM_AM33_REG_LAYOUT 0x00000000
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| 559 | #define EMIF_SRAM_AM43_REG_LAYOUT 0x00000001
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| 560 |
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| 561 | #ifndef __ASSEMBLY__
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| 562 | |
| 563 | * Structure containing shadow of important registers in EMIF
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| 564 | * The calculation function fills in this structure to be later used for
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| 565 | * initialisation and DVFS
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| 566 |
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| 567 | struct emif_regs {
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| 568 | u32 freq;
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| 569 | u32 ref_ctrl_shdw;
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| 570 | u32 ref_ctrl_shdw_derated;
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| 571 | u32 sdram_tim1_shdw;
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| 572 | u32 sdram_tim1_shdw_derated;
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| 573 | u32 sdram_tim2_shdw;
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| 574 | u32 sdram_tim3_shdw;
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| 575 | u32 sdram_tim3_shdw_derated;
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| 576 | u32 pwr_mgmt_ctrl_shdw;
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| 577 | union {
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| 578 | u32 read_idle_ctrl_shdw_normal;
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| 579 | u32 dll_calib_ctrl_shdw_normal;
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| 580 | };
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| 581 | union {
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| 582 | u32 read_idle_ctrl_shdw_volt_ramp;
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| 583 | u32 dll_calib_ctrl_shdw_volt_ramp;
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| 584 | };
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| 585 |
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| 586 | u32 phy_ctrl_1_shdw;
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| 587 | u32 ext_phy_ctrl_2_shdw;
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| 588 | u32 ext_phy_ctrl_3_shdw;
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| 589 | u32 ext_phy_ctrl_4_shdw;
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| 590 | };
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| 591 |
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| 592 | struct ti_emif_pm_functions;
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| 593 |
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| 594 | extern unsigned int ti_emif_sram;
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| 595 | extern unsigned int ti_emif_sram_sz;
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| 596 | extern struct ti_emif_pm_data ti_emif_pm_sram_data;
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| 597 | extern struct emif_regs_amx3 ti_emif_regs_amx3;
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| 598 |
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| 599 | void ti_emif_save_context(void);
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| 600 | void ti_emif_restore_context(void);
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| 601 | void ti_emif_run_hw_leveling(void);
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| 602 | void ti_emif_enter_sr(void);
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| 603 | void ti_emif_exit_sr(void);
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| 604 | void ti_emif_abort_sr(void);
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| 605 |
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| 606 | #endif
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| 607 | #endif
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