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1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <[email protected]>
5 * Copyright (C) 2016 Florian Fainelli <[email protected]>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <linux/delay.h>
21#include <linux/export.h>
22#include <linux/gpio/consumer.h>
23#include <linux/kernel.h>
24#include <linux/math.h>
25#include <linux/minmax.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
29#include <linux/phylink.h>
30#include <linux/etherdevice.h>
31#include <linux/if_bridge.h>
32#include <linux/if_vlan.h>
33#include <net/dsa.h>
34
35#include "b53_regs.h"
36#include "b53_priv.h"
37
38struct b53_mib_desc {
39 u8 size;
40 u8 offset;
41 const char *name;
42};
43
44/* BCM5365 MIB counters */
45static const struct b53_mib_desc b53_mibs_65[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
78};
79
80#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
81
82/* BCM63xx MIB counters */
83static const struct b53_mib_desc b53_mibs_63xx[] = {
84 { 8, 0x00, "TxOctets" },
85 { 4, 0x08, "TxDropPkts" },
86 { 4, 0x0c, "TxQoSPkts" },
87 { 4, 0x10, "TxBroadcastPkts" },
88 { 4, 0x14, "TxMulticastPkts" },
89 { 4, 0x18, "TxUnicastPkts" },
90 { 4, 0x1c, "TxCollisions" },
91 { 4, 0x20, "TxSingleCollision" },
92 { 4, 0x24, "TxMultipleCollision" },
93 { 4, 0x28, "TxDeferredTransmit" },
94 { 4, 0x2c, "TxLateCollision" },
95 { 4, 0x30, "TxExcessiveCollision" },
96 { 4, 0x38, "TxPausePkts" },
97 { 8, 0x3c, "TxQoSOctets" },
98 { 8, 0x44, "RxOctets" },
99 { 4, 0x4c, "RxUndersizePkts" },
100 { 4, 0x50, "RxPausePkts" },
101 { 4, 0x54, "Pkts64Octets" },
102 { 4, 0x58, "Pkts65to127Octets" },
103 { 4, 0x5c, "Pkts128to255Octets" },
104 { 4, 0x60, "Pkts256to511Octets" },
105 { 4, 0x64, "Pkts512to1023Octets" },
106 { 4, 0x68, "Pkts1024to1522Octets" },
107 { 4, 0x6c, "RxOversizePkts" },
108 { 4, 0x70, "RxJabbers" },
109 { 4, 0x74, "RxAlignmentErrors" },
110 { 4, 0x78, "RxFCSErrors" },
111 { 8, 0x7c, "RxGoodOctets" },
112 { 4, 0x84, "RxDropPkts" },
113 { 4, 0x88, "RxUnicastPkts" },
114 { 4, 0x8c, "RxMulticastPkts" },
115 { 4, 0x90, "RxBroadcastPkts" },
116 { 4, 0x94, "RxSAChanges" },
117 { 4, 0x98, "RxFragments" },
118 { 4, 0xa0, "RxSymbolErrors" },
119 { 4, 0xa4, "RxQoSPkts" },
120 { 8, 0xa8, "RxQoSOctets" },
121 { 4, 0xb0, "Pkts1523to2047Octets" },
122 { 4, 0xb4, "Pkts2048to4095Octets" },
123 { 4, 0xb8, "Pkts4096to8191Octets" },
124 { 4, 0xbc, "Pkts8192to9728Octets" },
125 { 4, 0xc0, "RxDiscarded" },
126};
127
128#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
129
130/* MIB counters */
131static const struct b53_mib_desc b53_mibs[] = {
132 { 8, 0x00, "TxOctets" },
133 { 4, 0x08, "TxDropPkts" },
134 { 4, 0x10, "TxBroadcastPkts" },
135 { 4, 0x14, "TxMulticastPkts" },
136 { 4, 0x18, "TxUnicastPkts" },
137 { 4, 0x1c, "TxCollisions" },
138 { 4, 0x20, "TxSingleCollision" },
139 { 4, 0x24, "TxMultipleCollision" },
140 { 4, 0x28, "TxDeferredTransmit" },
141 { 4, 0x2c, "TxLateCollision" },
142 { 4, 0x30, "TxExcessiveCollision" },
143 { 4, 0x38, "TxPausePkts" },
144 { 8, 0x50, "RxOctets" },
145 { 4, 0x58, "RxUndersizePkts" },
146 { 4, 0x5c, "RxPausePkts" },
147 { 4, 0x60, "Pkts64Octets" },
148 { 4, 0x64, "Pkts65to127Octets" },
149 { 4, 0x68, "Pkts128to255Octets" },
150 { 4, 0x6c, "Pkts256to511Octets" },
151 { 4, 0x70, "Pkts512to1023Octets" },
152 { 4, 0x74, "Pkts1024to1522Octets" },
153 { 4, 0x78, "RxOversizePkts" },
154 { 4, 0x7c, "RxJabbers" },
155 { 4, 0x80, "RxAlignmentErrors" },
156 { 4, 0x84, "RxFCSErrors" },
157 { 8, 0x88, "RxGoodOctets" },
158 { 4, 0x90, "RxDropPkts" },
159 { 4, 0x94, "RxUnicastPkts" },
160 { 4, 0x98, "RxMulticastPkts" },
161 { 4, 0x9c, "RxBroadcastPkts" },
162 { 4, 0xa0, "RxSAChanges" },
163 { 4, 0xa4, "RxFragments" },
164 { 4, 0xa8, "RxJumboPkts" },
165 { 4, 0xac, "RxSymbolErrors" },
166 { 4, 0xc0, "RxDiscarded" },
167};
168
169#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
170
171static const struct b53_mib_desc b53_mibs_58xx[] = {
172 { 8, 0x00, "TxOctets" },
173 { 4, 0x08, "TxDropPkts" },
174 { 4, 0x0c, "TxQPKTQ0" },
175 { 4, 0x10, "TxBroadcastPkts" },
176 { 4, 0x14, "TxMulticastPkts" },
177 { 4, 0x18, "TxUnicastPKts" },
178 { 4, 0x1c, "TxCollisions" },
179 { 4, 0x20, "TxSingleCollision" },
180 { 4, 0x24, "TxMultipleCollision" },
181 { 4, 0x28, "TxDeferredCollision" },
182 { 4, 0x2c, "TxLateCollision" },
183 { 4, 0x30, "TxExcessiveCollision" },
184 { 4, 0x34, "TxFrameInDisc" },
185 { 4, 0x38, "TxPausePkts" },
186 { 4, 0x3c, "TxQPKTQ1" },
187 { 4, 0x40, "TxQPKTQ2" },
188 { 4, 0x44, "TxQPKTQ3" },
189 { 4, 0x48, "TxQPKTQ4" },
190 { 4, 0x4c, "TxQPKTQ5" },
191 { 8, 0x50, "RxOctets" },
192 { 4, 0x58, "RxUndersizePkts" },
193 { 4, 0x5c, "RxPausePkts" },
194 { 4, 0x60, "RxPkts64Octets" },
195 { 4, 0x64, "RxPkts65to127Octets" },
196 { 4, 0x68, "RxPkts128to255Octets" },
197 { 4, 0x6c, "RxPkts256to511Octets" },
198 { 4, 0x70, "RxPkts512to1023Octets" },
199 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
200 { 4, 0x78, "RxOversizePkts" },
201 { 4, 0x7c, "RxJabbers" },
202 { 4, 0x80, "RxAlignmentErrors" },
203 { 4, 0x84, "RxFCSErrors" },
204 { 8, 0x88, "RxGoodOctets" },
205 { 4, 0x90, "RxDropPkts" },
206 { 4, 0x94, "RxUnicastPkts" },
207 { 4, 0x98, "RxMulticastPkts" },
208 { 4, 0x9c, "RxBroadcastPkts" },
209 { 4, 0xa0, "RxSAChanges" },
210 { 4, 0xa4, "RxFragments" },
211 { 4, 0xa8, "RxJumboPkt" },
212 { 4, 0xac, "RxSymblErr" },
213 { 4, 0xb0, "InRangeErrCount" },
214 { 4, 0xb4, "OutRangeErrCount" },
215 { 4, 0xb8, "EEELpiEvent" },
216 { 4, 0xbc, "EEELpiDuration" },
217 { 4, 0xc0, "RxDiscard" },
218 { 4, 0xc8, "TxQPKTQ6" },
219 { 4, 0xcc, "TxQPKTQ7" },
220 { 4, 0xd0, "TxPkts64Octets" },
221 { 4, 0xd4, "TxPkts65to127Octets" },
222 { 4, 0xd8, "TxPkts128to255Octets" },
223 { 4, 0xdc, "TxPkts256to511Ocets" },
224 { 4, 0xe0, "TxPkts512to1023Ocets" },
225 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
226};
227
228#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
229
230#define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
231#define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
232
233static int b53_do_vlan_op(struct b53_device *dev, u8 op)
234{
235 unsigned int i;
236
237 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
238
239 for (i = 0; i < 10; i++) {
240 u8 vta;
241
242 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
243 if (!(vta & VTA_START_CMD))
244 return 0;
245
246 usleep_range(100, 200);
247 }
248
249 return -EIO;
250}
251
252static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
253 struct b53_vlan *vlan)
254{
255 if (is5325(dev)) {
256 u32 entry = 0;
257
258 if (vlan->members) {
259 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
260 VA_UNTAG_S_25) | vlan->members;
261 if (dev->core_rev >= 3)
262 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
263 else
264 entry |= VA_VALID_25;
265 }
266
267 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
268 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
269 VTA_RW_STATE_WR | VTA_RW_OP_EN);
270 } else if (is5365(dev)) {
271 u16 entry = 0;
272
273 if (vlan->members)
274 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
275 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
276
277 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
278 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
279 VTA_RW_STATE_WR | VTA_RW_OP_EN);
280 } else {
281 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
282 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
283 (vlan->untag << VTE_UNTAG_S) | vlan->members);
284
285 b53_do_vlan_op(dev, VTA_CMD_WRITE);
286 }
287
288 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
289 vid, vlan->members, vlan->untag);
290}
291
292static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
293 struct b53_vlan *vlan)
294{
295 if (is5325(dev)) {
296 u32 entry = 0;
297
298 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
299 VTA_RW_STATE_RD | VTA_RW_OP_EN);
300 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
301
302 if (dev->core_rev >= 3)
303 vlan->valid = !!(entry & VA_VALID_25_R4);
304 else
305 vlan->valid = !!(entry & VA_VALID_25);
306 vlan->members = entry & VA_MEMBER_MASK;
307 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
308
309 } else if (is5365(dev)) {
310 u16 entry = 0;
311
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
313 VTA_RW_STATE_WR | VTA_RW_OP_EN);
314 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
315
316 vlan->valid = !!(entry & VA_VALID_65);
317 vlan->members = entry & VA_MEMBER_MASK;
318 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
319 } else {
320 u32 entry = 0;
321
322 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
323 b53_do_vlan_op(dev, VTA_CMD_READ);
324 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
325 vlan->members = entry & VTE_MEMBERS;
326 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
327 vlan->valid = true;
328 }
329}
330
331static void b53_set_eap_mode(struct b53_device *dev, int port, int mode)
332{
333 u64 eap_conf;
334
335 if (is5325(dev) || is5365(dev) || dev->chip_id == BCM5389_DEVICE_ID)
336 return;
337
338 b53_read64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), &eap_conf);
339
340 if (is63xx(dev)) {
341 eap_conf &= ~EAP_MODE_MASK_63XX;
342 eap_conf |= (u64)mode << EAP_MODE_SHIFT_63XX;
343 } else {
344 eap_conf &= ~EAP_MODE_MASK;
345 eap_conf |= (u64)mode << EAP_MODE_SHIFT;
346 }
347
348 b53_write64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), eap_conf);
349}
350
351static void b53_set_forwarding(struct b53_device *dev, int enable)
352{
353 u8 mgmt;
354
355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
356
357 if (enable)
358 mgmt |= SM_SW_FWD_EN;
359 else
360 mgmt &= ~SM_SW_FWD_EN;
361
362 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
363
364 if (!is5325(dev)) {
365 /* Include IMP port in dumb forwarding mode */
366 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
367 mgmt |= B53_MII_DUMB_FWDG_EN;
368 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
369
370 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
371 * frames should be flooded or not.
372 */
373 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
374 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IP_MC;
375 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
376 } else {
377 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
378 mgmt |= B53_IP_MC;
379 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
380 }
381}
382
383static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
384 bool enable_filtering)
385{
386 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
387
388 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
389 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
390 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
391
392 if (is5325(dev) || is5365(dev)) {
393 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
394 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
395 } else if (is63xx(dev)) {
396 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
397 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
398 } else {
399 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
400 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
401 }
402
403 vc1 &= ~VC1_RX_MCST_FWD_EN;
404
405 if (enable) {
406 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
407 vc1 |= VC1_RX_MCST_UNTAG_EN;
408 vc4 &= ~VC4_ING_VID_CHECK_MASK;
409 if (enable_filtering) {
410 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
411 vc5 |= VC5_DROP_VTABLE_MISS;
412 } else {
413 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S;
414 vc5 &= ~VC5_DROP_VTABLE_MISS;
415 }
416
417 if (is5325(dev))
418 vc0 &= ~VC0_RESERVED_1;
419
420 if (is5325(dev) || is5365(dev))
421 vc1 |= VC1_RX_MCST_TAG_EN;
422
423 } else {
424 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
425 vc1 &= ~VC1_RX_MCST_UNTAG_EN;
426 vc4 &= ~VC4_ING_VID_CHECK_MASK;
427 vc5 &= ~VC5_DROP_VTABLE_MISS;
428
429 if (is5325(dev) || is5365(dev))
430 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
431 else
432 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
433
434 if (is5325(dev) || is5365(dev))
435 vc1 &= ~VC1_RX_MCST_TAG_EN;
436 }
437
438 if (!is5325(dev) && !is5365(dev))
439 vc5 &= ~VC5_VID_FFF_EN;
440
441 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
442 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
443
444 if (is5325(dev) || is5365(dev)) {
445 /* enable the high 8 bit vid check on 5325 */
446 if (is5325(dev) && enable)
447 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
448 VC3_HIGH_8BIT_EN);
449 else
450 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
451
452 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
453 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
454 } else if (is63xx(dev)) {
455 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
456 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
457 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
458 } else {
459 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
460 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
461 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
462 }
463
464 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
465
466 dev->vlan_enabled = enable;
467
468 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
469 port, enable, enable_filtering);
470}
471
472static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
473{
474 u32 port_mask = 0;
475 u16 max_size = JMS_MIN_SIZE;
476
477 if (is5325(dev) || is5365(dev))
478 return -EINVAL;
479
480 if (enable) {
481 port_mask = dev->enabled_ports;
482 max_size = JMS_MAX_SIZE;
483 if (allow_10_100)
484 port_mask |= JPM_10_100_JUMBO_EN;
485 }
486
487 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
488 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
489}
490
491static int b53_flush_arl(struct b53_device *dev, u8 mask)
492{
493 unsigned int i;
494
495 if (is5325(dev))
496 return 0;
497
498 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
499 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
500
501 for (i = 0; i < 10; i++) {
502 u8 fast_age_ctrl;
503
504 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
505 &fast_age_ctrl);
506
507 if (!(fast_age_ctrl & FAST_AGE_DONE))
508 goto out;
509
510 msleep(1);
511 }
512
513 return -ETIMEDOUT;
514out:
515 /* Only age dynamic entries (default behavior) */
516 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
517 return 0;
518}
519
520static int b53_fast_age_port(struct b53_device *dev, int port)
521{
522 if (is5325(dev))
523 return 0;
524
525 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
526
527 return b53_flush_arl(dev, FAST_AGE_PORT);
528}
529
530static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
531{
532 if (is5325(dev))
533 return 0;
534
535 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
536
537 return b53_flush_arl(dev, FAST_AGE_VLAN);
538}
539
540void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
541{
542 struct b53_device *dev = ds->priv;
543 unsigned int i;
544 u16 pvlan;
545
546 /* BCM5325 CPU port is at 8 */
547 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
548 cpu_port = B53_CPU_PORT;
549
550 /* Enable the IMP port to be in the same VLAN as the other ports
551 * on a per-port basis such that we only have Port i and IMP in
552 * the same VLAN.
553 */
554 b53_for_each_port(dev, i) {
555 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
556 pvlan |= BIT(cpu_port);
557 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
558 }
559}
560EXPORT_SYMBOL(b53_imp_vlan_setup);
561
562static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
563 bool unicast)
564{
565 u16 uc;
566
567 if (is5325(dev)) {
568 if (port == B53_CPU_PORT_25)
569 port = B53_CPU_PORT;
570
571 b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, &uc);
572 if (unicast)
573 uc |= BIT(port) | B53_IEEE_UCAST_DROP_EN;
574 else
575 uc &= ~BIT(port);
576 b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, uc);
577 } else {
578 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
579 if (unicast)
580 uc |= BIT(port);
581 else
582 uc &= ~BIT(port);
583 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
584 }
585}
586
587static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
588 bool multicast)
589{
590 u16 mc;
591
592 if (is5325(dev)) {
593 if (port == B53_CPU_PORT_25)
594 port = B53_CPU_PORT;
595
596 b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, &mc);
597 if (multicast)
598 mc |= BIT(port) | B53_IEEE_MCAST_DROP_EN;
599 else
600 mc &= ~BIT(port);
601 b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, mc);
602 } else {
603 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
604 if (multicast)
605 mc |= BIT(port);
606 else
607 mc &= ~BIT(port);
608 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
609
610 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
611 if (multicast)
612 mc |= BIT(port);
613 else
614 mc &= ~BIT(port);
615 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
616 }
617}
618
619static void b53_port_set_learning(struct b53_device *dev, int port,
620 bool learning)
621{
622 u16 reg;
623
624 if (is5325(dev))
625 return;
626
627 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);
628 if (learning)
629 reg &= ~BIT(port);
630 else
631 reg |= BIT(port);
632 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
633}
634
635static void b53_port_set_isolated(struct b53_device *dev, int port,
636 bool isolated)
637{
638 u8 offset;
639 u16 reg;
640
641 if (is5325(dev))
642 offset = B53_PROTECTED_PORT_SEL_25;
643 else
644 offset = B53_PROTECTED_PORT_SEL;
645
646 b53_read16(dev, B53_CTRL_PAGE, offset, &reg);
647 if (isolated)
648 reg |= BIT(port);
649 else
650 reg &= ~BIT(port);
651 b53_write16(dev, B53_CTRL_PAGE, offset, reg);
652}
653
654static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
655{
656 struct b53_device *dev = ds->priv;
657 u16 reg;
658
659 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
660 if (enable)
661 reg |= BIT(port);
662 else
663 reg &= ~BIT(port);
664 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
665}
666
667int b53_setup_port(struct dsa_switch *ds, int port)
668{
669 struct b53_device *dev = ds->priv;
670
671 b53_port_set_ucast_flood(dev, port, true);
672 b53_port_set_mcast_flood(dev, port, true);
673 b53_port_set_learning(dev, port, false);
674 b53_port_set_isolated(dev, port, false);
675
676 /* Force all traffic to go to the CPU port to prevent the ASIC from
677 * trying to forward to bridged ports on matching FDB entries, then
678 * dropping frames because it isn't allowed to forward there.
679 */
680 if (dsa_is_user_port(ds, port))
681 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED);
682
683 if (is5325(dev) &&
684 in_range(port, 1, 4)) {
685 u8 reg;
686
687 b53_read8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, &reg);
688 reg &= ~PD_MODE_POWER_DOWN_PORT(0);
689 if (dsa_is_unused_port(ds, port))
690 reg |= PD_MODE_POWER_DOWN_PORT(port);
691 else
692 reg &= ~PD_MODE_POWER_DOWN_PORT(port);
693 b53_write8(dev, B53_CTRL_PAGE, B53_PD_MODE_CTRL_25, reg);
694 }
695
696 return 0;
697}
698EXPORT_SYMBOL(b53_setup_port);
699
700int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
701{
702 struct b53_device *dev = ds->priv;
703 unsigned int cpu_port;
704 int ret = 0;
705 u16 pvlan;
706
707 if (!dsa_is_user_port(ds, port))
708 return 0;
709
710 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
711
712 if (dev->ops->phy_enable)
713 dev->ops->phy_enable(dev, port);
714
715 if (dev->ops->irq_enable)
716 ret = dev->ops->irq_enable(dev, port);
717 if (ret)
718 return ret;
719
720 /* Clear the Rx and Tx disable bits and set to no spanning tree */
721 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
722
723 /* Set this port, and only this one to be in the default VLAN,
724 * if member of a bridge, restore its membership prior to
725 * bringing down this port.
726 */
727 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
728 pvlan &= ~0x1ff;
729 pvlan |= BIT(port);
730 pvlan |= dev->ports[port].vlan_ctl_mask;
731 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
732
733 b53_imp_vlan_setup(ds, cpu_port);
734
735 /* If EEE was enabled, restore it */
736 if (dev->ports[port].eee.eee_enabled)
737 b53_eee_enable_set(ds, port, true);
738
739 return 0;
740}
741EXPORT_SYMBOL(b53_enable_port);
742
743void b53_disable_port(struct dsa_switch *ds, int port)
744{
745 struct b53_device *dev = ds->priv;
746 u8 reg;
747
748 /* Disable Tx/Rx for the port */
749 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
750 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
751 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
752
753 if (dev->ops->phy_disable)
754 dev->ops->phy_disable(dev, port);
755
756 if (dev->ops->irq_disable)
757 dev->ops->irq_disable(dev, port);
758}
759EXPORT_SYMBOL(b53_disable_port);
760
761void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
762{
763 struct b53_device *dev = ds->priv;
764 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
765 u8 hdr_ctl, val;
766 u16 reg;
767
768 /* Resolve which bit controls the Broadcom tag */
769 switch (port) {
770 case 8:
771 val = BRCM_HDR_P8_EN;
772 break;
773 case 7:
774 val = BRCM_HDR_P7_EN;
775 break;
776 case 5:
777 val = BRCM_HDR_P5_EN;
778 break;
779 default:
780 val = 0;
781 break;
782 }
783
784 /* Enable management mode if tagging is requested */
785 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
786 if (tag_en)
787 hdr_ctl |= SM_SW_FWD_MODE;
788 else
789 hdr_ctl &= ~SM_SW_FWD_MODE;
790 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
791
792 /* Configure the appropriate IMP port */
793 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
794 if (port == 8)
795 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
796 else if (port == 5)
797 hdr_ctl |= GC_FRM_MGMT_PORT_M;
798 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
799
800 /* B53_BRCM_HDR not present on devices with legacy tags */
801 if (dev->tag_protocol == DSA_TAG_PROTO_BRCM_LEGACY ||
802 dev->tag_protocol == DSA_TAG_PROTO_BRCM_LEGACY_FCS)
803 return;
804
805 /* Enable Broadcom tags for IMP port */
806 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
807 if (tag_en)
808 hdr_ctl |= val;
809 else
810 hdr_ctl &= ~val;
811 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
812
813 /* Registers below are only accessible on newer devices */
814 if (!is58xx(dev))
815 return;
816
817 /* Enable reception Broadcom tag for CPU TX (switch RX) to
818 * allow us to tag outgoing frames
819 */
820 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
821 if (tag_en)
822 reg &= ~BIT(port);
823 else
824 reg |= BIT(port);
825 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
826
827 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
828 * allow delivering frames to the per-port net_devices
829 */
830 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
831 if (tag_en)
832 reg &= ~BIT(port);
833 else
834 reg |= BIT(port);
835 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
836}
837EXPORT_SYMBOL(b53_brcm_hdr_setup);
838
839static void b53_enable_cpu_port(struct b53_device *dev, int port)
840{
841 u8 port_ctrl;
842
843 /* BCM5325 CPU port is at 8 */
844 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
845 port = B53_CPU_PORT;
846
847 port_ctrl = PORT_CTRL_RX_BCST_EN |
848 PORT_CTRL_RX_MCST_EN |
849 PORT_CTRL_RX_UCST_EN;
850 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
851
852 b53_brcm_hdr_setup(dev->ds, port);
853}
854
855static void b53_enable_mib(struct b53_device *dev)
856{
857 u8 gc;
858
859 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
860 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
861 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
862}
863
864static void b53_enable_stp(struct b53_device *dev)
865{
866 u8 gc;
867
868 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
869 gc |= GC_RX_BPDU_EN;
870 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
871}
872
873static u16 b53_default_pvid(struct b53_device *dev)
874{
875 return 0;
876}
877
878static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
879{
880 struct b53_device *dev = ds->priv;
881
882 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
883}
884
885static bool b53_vlan_port_may_join_untagged(struct dsa_switch *ds, int port)
886{
887 struct b53_device *dev = ds->priv;
888 struct dsa_port *dp;
889
890 if (!dev->vlan_filtering)
891 return true;
892
893 dp = dsa_to_port(ds, port);
894
895 if (dsa_port_is_cpu(dp))
896 return true;
897
898 return dp->bridge == NULL;
899}
900
901int b53_configure_vlan(struct dsa_switch *ds)
902{
903 struct b53_device *dev = ds->priv;
904 struct b53_vlan vl = { 0 };
905 struct b53_vlan *v;
906 int i, def_vid;
907 u16 vid;
908
909 def_vid = b53_default_pvid(dev);
910
911 /* clear all vlan entries */
912 if (is5325(dev) || is5365(dev)) {
913 for (i = def_vid; i < dev->num_vlans; i++)
914 b53_set_vlan_entry(dev, i, &vl);
915 } else {
916 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
917 }
918
919 b53_enable_vlan(dev, -1, dev->vlan_enabled, dev->vlan_filtering);
920
921 /* Create an untagged VLAN entry for the default PVID in case
922 * CONFIG_VLAN_8021Q is disabled and there are no calls to
923 * dsa_user_vlan_rx_add_vid() to create the default VLAN
924 * entry. Do this only when the tagging protocol is not
925 * DSA_TAG_PROTO_NONE
926 */
927 v = &dev->vlans[def_vid];
928 b53_for_each_port(dev, i) {
929 if (!b53_vlan_port_may_join_untagged(ds, i))
930 continue;
931
932 vl.members |= BIT(i);
933 if (!b53_vlan_port_needs_forced_tagged(ds, i))
934 vl.untag = vl.members;
935 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(i),
936 def_vid);
937 }
938 b53_set_vlan_entry(dev, def_vid, &vl);
939
940 if (dev->vlan_filtering) {
941 /* Upon initial call we have not set-up any VLANs, but upon
942 * system resume, we need to restore all VLAN entries.
943 */
944 for (vid = def_vid + 1; vid < dev->num_vlans; vid++) {
945 v = &dev->vlans[vid];
946
947 if (!v->members)
948 continue;
949
950 b53_set_vlan_entry(dev, vid, v);
951 b53_fast_age_vlan(dev, vid);
952 }
953
954 b53_for_each_port(dev, i) {
955 if (!dsa_is_cpu_port(ds, i))
956 b53_write16(dev, B53_VLAN_PAGE,
957 B53_VLAN_PORT_DEF_TAG(i),
958 dev->ports[i].pvid);
959 }
960 }
961
962 return 0;
963}
964EXPORT_SYMBOL(b53_configure_vlan);
965
966static void b53_switch_reset_gpio(struct b53_device *dev)
967{
968 struct gpio_desc *gpio = dev->reset_gpio;
969
970 if (IS_ERR(gpio))
971 return;
972
973 /* Reset sequence: RESET low(50ms)->high(20ms)
974 */
975 gpiod_set_value(gpio, 0);
976 mdelay(50);
977
978 gpiod_set_value(gpio, 1);
979 mdelay(20);
980
981 dev->current_page = 0xff;
982}
983
984static int b53_switch_reset(struct b53_device *dev)
985{
986 unsigned int timeout = 1000;
987 u8 mgmt, reg;
988
989 b53_switch_reset_gpio(dev);
990
991 if (is539x(dev)) {
992 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
993 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
994 }
995
996 /* This is specific to 58xx devices here, do not use is58xx() which
997 * covers the larger Starfigther 2 family, including 7445/7278 which
998 * still use this driver as a library and need to perform the reset
999 * earlier.
1000 */
1001 if (dev->chip_id == BCM58XX_DEVICE_ID ||
1002 dev->chip_id == BCM583XX_DEVICE_ID) {
1003 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
1004 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
1005 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
1006
1007 do {
1008 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
1009 if (!(reg & SW_RST))
1010 break;
1011
1012 usleep_range(1000, 2000);
1013 } while (timeout-- > 0);
1014
1015 if (timeout == 0) {
1016 dev_err(dev->dev,
1017 "Timeout waiting for SW_RST to clear!\n");
1018 return -ETIMEDOUT;
1019 }
1020 }
1021
1022 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
1023
1024 if (!(mgmt & SM_SW_FWD_EN)) {
1025 mgmt &= ~SM_SW_FWD_MODE;
1026 mgmt |= SM_SW_FWD_EN;
1027
1028 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
1029 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
1030
1031 if (!(mgmt & SM_SW_FWD_EN)) {
1032 dev_err(dev->dev, "Failed to enable switch!\n");
1033 return -EINVAL;
1034 }
1035 }
1036
1037 b53_enable_mib(dev);
1038 b53_enable_stp(dev);
1039
1040 return b53_flush_arl(dev, FAST_AGE_STATIC);
1041}
1042
1043static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
1044{
1045 struct b53_device *priv = ds->priv;
1046 u16 value = 0;
1047 int ret;
1048
1049 if (priv->ops->phy_read16)
1050 ret = priv->ops->phy_read16(priv, addr, reg, &value);
1051 else
1052 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
1053 reg * 2, &value);
1054
1055 return ret ? ret : value;
1056}
1057
1058static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
1059{
1060 struct b53_device *priv = ds->priv;
1061
1062 if (priv->ops->phy_write16)
1063 return priv->ops->phy_write16(priv, addr, reg, val);
1064
1065 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
1066}
1067
1068static int b53_reset_switch(struct b53_device *priv)
1069{
1070 /* reset vlans */
1071 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
1072 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
1073
1074 priv->serdes_lane = B53_INVALID_LANE;
1075
1076 return b53_switch_reset(priv);
1077}
1078
1079static int b53_apply_config(struct b53_device *priv)
1080{
1081 /* disable switching */
1082 b53_set_forwarding(priv, 0);
1083
1084 b53_configure_vlan(priv->ds);
1085
1086 /* enable switching */
1087 b53_set_forwarding(priv, 1);
1088
1089 return 0;
1090}
1091
1092static void b53_reset_mib(struct b53_device *priv)
1093{
1094 u8 gc;
1095
1096 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
1097
1098 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
1099 msleep(1);
1100 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
1101 msleep(1);
1102}
1103
1104static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
1105{
1106 if (is5365(dev))
1107 return b53_mibs_65;
1108 else if (is63xx(dev))
1109 return b53_mibs_63xx;
1110 else if (is58xx(dev))
1111 return b53_mibs_58xx;
1112 else
1113 return b53_mibs;
1114}
1115
1116static unsigned int b53_get_mib_size(struct b53_device *dev)
1117{
1118 if (is5365(dev))
1119 return B53_MIBS_65_SIZE;
1120 else if (is63xx(dev))
1121 return B53_MIBS_63XX_SIZE;
1122 else if (is58xx(dev))
1123 return B53_MIBS_58XX_SIZE;
1124 else
1125 return B53_MIBS_SIZE;
1126}
1127
1128static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
1129{
1130 /* These ports typically do not have built-in PHYs */
1131 switch (port) {
1132 case B53_CPU_PORT_25:
1133 case 7:
1134 case B53_CPU_PORT:
1135 return NULL;
1136 }
1137
1138 return mdiobus_get_phy(ds->user_mii_bus, port);
1139}
1140
1141void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1142 uint8_t *data)
1143{
1144 struct b53_device *dev = ds->priv;
1145 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1146 unsigned int mib_size = b53_get_mib_size(dev);
1147 struct phy_device *phydev;
1148 unsigned int i;
1149
1150 if (stringset == ETH_SS_STATS) {
1151 for (i = 0; i < mib_size; i++)
1152 ethtool_puts(&data, mibs[i].name);
1153 } else if (stringset == ETH_SS_PHY_STATS) {
1154 phydev = b53_get_phy_device(ds, port);
1155 if (!phydev)
1156 return;
1157
1158 phy_ethtool_get_strings(phydev, data);
1159 }
1160}
1161EXPORT_SYMBOL(b53_get_strings);
1162
1163void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
1164{
1165 struct b53_device *dev = ds->priv;
1166 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1167 unsigned int mib_size = b53_get_mib_size(dev);
1168 const struct b53_mib_desc *s;
1169 unsigned int i;
1170 u64 val = 0;
1171
1172 if (is5365(dev) && port == 5)
1173 port = 8;
1174
1175 mutex_lock(&dev->stats_mutex);
1176
1177 for (i = 0; i < mib_size; i++) {
1178 s = &mibs[i];
1179
1180 if (s->size == 8) {
1181 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1182 } else {
1183 u32 val32;
1184
1185 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1186 &val32);
1187 val = val32;
1188 }
1189 data[i] = (u64)val;
1190 }
1191
1192 mutex_unlock(&dev->stats_mutex);
1193}
1194EXPORT_SYMBOL(b53_get_ethtool_stats);
1195
1196void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1197{
1198 struct phy_device *phydev;
1199
1200 phydev = b53_get_phy_device(ds, port);
1201 if (!phydev)
1202 return;
1203
1204 phy_ethtool_get_stats(phydev, NULL, data);
1205}
1206EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1207
1208int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1209{
1210 struct b53_device *dev = ds->priv;
1211 struct phy_device *phydev;
1212
1213 if (sset == ETH_SS_STATS) {
1214 return b53_get_mib_size(dev);
1215 } else if (sset == ETH_SS_PHY_STATS) {
1216 phydev = b53_get_phy_device(ds, port);
1217 if (!phydev)
1218 return 0;
1219
1220 return phy_ethtool_get_sset_count(phydev);
1221 }
1222
1223 return 0;
1224}
1225EXPORT_SYMBOL(b53_get_sset_count);
1226
1227enum b53_devlink_resource_id {
1228 B53_DEVLINK_PARAM_ID_NONE, /* DEVLINK_RESOURCE_ID_PARENT_TOP */
1229 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1230};
1231
1232static u64 b53_devlink_vlan_table_get(void *priv)
1233{
1234 struct b53_device *dev = priv;
1235 struct b53_vlan *vl;
1236 unsigned int i;
1237 u64 count = 0;
1238
1239 for (i = 0; i < dev->num_vlans; i++) {
1240 vl = &dev->vlans[i];
1241 if (vl->members)
1242 count++;
1243 }
1244
1245 return count;
1246}
1247
1248int b53_setup_devlink_resources(struct dsa_switch *ds)
1249{
1250 struct devlink_resource_size_params size_params;
1251 struct b53_device *dev = ds->priv;
1252 int err;
1253
1254 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1255 dev->num_vlans,
1256 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1257
1258 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1259 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1260 DEVLINK_RESOURCE_ID_PARENT_TOP,
1261 &size_params);
1262 if (err)
1263 goto out;
1264
1265 dsa_devlink_resource_occ_get_register(ds,
1266 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1267 b53_devlink_vlan_table_get, dev);
1268
1269 return 0;
1270out:
1271 dsa_devlink_resources_unregister(ds);
1272 return err;
1273}
1274EXPORT_SYMBOL(b53_setup_devlink_resources);
1275
1276static int b53_setup(struct dsa_switch *ds)
1277{
1278 struct b53_device *dev = ds->priv;
1279 struct b53_vlan *vl;
1280 unsigned int port;
1281 u16 pvid;
1282 int ret;
1283
1284 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1285 * which forces the CPU port to be tagged in all VLANs.
1286 */
1287 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1288
1289 /* The switch does not tell us the original VLAN for untagged
1290 * packets, so keep the CPU port always tagged.
1291 */
1292 ds->untag_vlan_aware_bridge_pvid = true;
1293
1294 if (dev->chip_id == BCM53101_DEVICE_ID) {
1295 /* BCM53101 uses 0.5 second increments */
1296 ds->ageing_time_min = 1 * 500;
1297 ds->ageing_time_max = AGE_TIME_MAX * 500;
1298 } else {
1299 /* Everything else uses 1 second increments */
1300 ds->ageing_time_min = 1 * 1000;
1301 ds->ageing_time_max = AGE_TIME_MAX * 1000;
1302 }
1303
1304 ret = b53_reset_switch(dev);
1305 if (ret) {
1306 dev_err(ds->dev, "failed to reset switch\n");
1307 return ret;
1308 }
1309
1310 /* setup default vlan for filtering mode */
1311 pvid = b53_default_pvid(dev);
1312 vl = &dev->vlans[pvid];
1313 b53_for_each_port(dev, port) {
1314 vl->members |= BIT(port);
1315 if (!b53_vlan_port_needs_forced_tagged(ds, port))
1316 vl->untag |= BIT(port);
1317 }
1318
1319 b53_reset_mib(dev);
1320
1321 ret = b53_apply_config(dev);
1322 if (ret) {
1323 dev_err(ds->dev, "failed to apply configuration\n");
1324 return ret;
1325 }
1326
1327 /* Configure IMP/CPU port, disable all other ports. Enabled
1328 * ports will be configured with .port_enable
1329 */
1330 for (port = 0; port < dev->num_ports; port++) {
1331 if (dsa_is_cpu_port(ds, port))
1332 b53_enable_cpu_port(dev, port);
1333 else
1334 b53_disable_port(ds, port);
1335 }
1336
1337 return b53_setup_devlink_resources(ds);
1338}
1339
1340static void b53_teardown(struct dsa_switch *ds)
1341{
1342 dsa_devlink_resources_unregister(ds);
1343}
1344
1345static void b53_force_link(struct b53_device *dev, int port, int link)
1346{
1347 u8 reg, val, off;
1348
1349 /* Override the port settings */
1350 if (port == dev->imp_port) {
1351 off = B53_PORT_OVERRIDE_CTRL;
1352 val = PORT_OVERRIDE_EN;
1353 } else if (is5325(dev)) {
1354 return;
1355 } else {
1356 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1357 val = GMII_PO_EN;
1358 }
1359
1360 b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1361 reg |= val;
1362 if (link)
1363 reg |= PORT_OVERRIDE_LINK;
1364 else
1365 reg &= ~PORT_OVERRIDE_LINK;
1366 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1367}
1368
1369static void b53_force_port_config(struct b53_device *dev, int port,
1370 int speed, int duplex,
1371 bool tx_pause, bool rx_pause)
1372{
1373 u8 reg, val, off;
1374
1375 /* Override the port settings */
1376 if (port == dev->imp_port) {
1377 off = B53_PORT_OVERRIDE_CTRL;
1378 val = PORT_OVERRIDE_EN;
1379 } else if (is5325(dev)) {
1380 return;
1381 } else {
1382 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1383 val = GMII_PO_EN;
1384 }
1385
1386 b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1387 reg |= val;
1388 if (duplex == DUPLEX_FULL)
1389 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1390 else
1391 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1392
1393 reg &= ~(0x3 << GMII_PO_SPEED_S);
1394 if (is5301x(dev) || is58xx(dev))
1395 reg &= ~PORT_OVERRIDE_SPEED_2000M;
1396
1397 switch (speed) {
1398 case 2000:
1399 reg |= PORT_OVERRIDE_SPEED_2000M;
1400 fallthrough;
1401 case SPEED_1000:
1402 reg |= PORT_OVERRIDE_SPEED_1000M;
1403 break;
1404 case SPEED_100:
1405 reg |= PORT_OVERRIDE_SPEED_100M;
1406 break;
1407 case SPEED_10:
1408 reg |= PORT_OVERRIDE_SPEED_10M;
1409 break;
1410 default:
1411 dev_err(dev->dev, "unknown speed: %d\n", speed);
1412 return;
1413 }
1414
1415 if (is5325(dev))
1416 reg &= ~PORT_OVERRIDE_LP_FLOW_25;
1417 else
1418 reg &= ~(PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW);
1419
1420 if (rx_pause) {
1421 if (is5325(dev))
1422 reg |= PORT_OVERRIDE_LP_FLOW_25;
1423 else
1424 reg |= PORT_OVERRIDE_RX_FLOW;
1425 }
1426
1427 if (tx_pause) {
1428 if (is5325(dev))
1429 reg |= PORT_OVERRIDE_LP_FLOW_25;
1430 else
1431 reg |= PORT_OVERRIDE_TX_FLOW;
1432 }
1433
1434 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1435}
1436
1437static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1438 phy_interface_t interface)
1439{
1440 struct b53_device *dev = ds->priv;
1441 u8 rgmii_ctrl = 0;
1442
1443 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), &rgmii_ctrl);
1444 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1445
1446 if (is6318_268(dev))
1447 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1448
1449 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1450
1451 b53_write8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), rgmii_ctrl);
1452
1453 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1454 phy_modes(interface));
1455}
1456
1457static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port,
1458 phy_interface_t interface)
1459{
1460 struct b53_device *dev = ds->priv;
1461 u8 rgmii_ctrl = 0, off;
1462
1463 if (port == dev->imp_port)
1464 off = B53_RGMII_CTRL_IMP;
1465 else
1466 off = B53_RGMII_CTRL_P(port);
1467
1468 /* Configure the port RGMII clock delay by DLL disabled and
1469 * tx_clk aligned timing (restoring to reset defaults)
1470 */
1471 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1472 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1473
1474 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1475 * sure that we enable the port TX clock internal delay to
1476 * account for this internal delay that is inserted, otherwise
1477 * the switch won't be able to receive correctly.
1478 *
1479 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1480 * any delay neither on transmission nor reception, so the
1481 * BCM53125 must also be configured accordingly to account for
1482 * the lack of delay and introduce
1483 *
1484 * The BCM53125 switch has its RX clock and TX clock control
1485 * swapped, hence the reason why we modify the TX clock path in
1486 * the "RGMII" case
1487 */
1488 if (interface == PHY_INTERFACE_MODE_RGMII_TXID)
1489 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1490 if (interface == PHY_INTERFACE_MODE_RGMII)
1491 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1492
1493 if (dev->chip_id != BCM53115_DEVICE_ID)
1494 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1495
1496 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1497
1498 dev_info(ds->dev, "Configured port %d for %s\n", port,
1499 phy_modes(interface));
1500}
1501
1502static void b53_adjust_5325_mii(struct dsa_switch *ds, int port)
1503{
1504 struct b53_device *dev = ds->priv;
1505 u8 reg = 0;
1506
1507 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1508 &reg);
1509
1510 /* reverse mii needs to be enabled */
1511 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1513 reg | PORT_OVERRIDE_RV_MII_25);
1514 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1515 &reg);
1516
1517 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1518 dev_err(ds->dev,
1519 "Failed to enable reverse MII mode\n");
1520 return;
1521 }
1522 }
1523}
1524
1525void b53_port_event(struct dsa_switch *ds, int port)
1526{
1527 struct b53_device *dev = ds->priv;
1528 bool link;
1529 u16 sts;
1530
1531 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1532 link = !!(sts & BIT(port));
1533 dsa_port_phylink_mac_change(ds, port, link);
1534}
1535EXPORT_SYMBOL(b53_port_event);
1536
1537static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1538 struct phylink_config *config)
1539{
1540 struct b53_device *dev = ds->priv;
1541
1542 /* Internal ports need GMII for PHYLIB */
1543 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1544
1545 /* These switches appear to support MII and RevMII too, but beyond
1546 * this, the code gives very few clues. FIXME: We probably need more
1547 * interface modes here.
1548 *
1549 * According to b53_srab_mux_init(), ports 3..5 can support:
1550 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1551 * However, the interface mode read from the MUX configuration is
1552 * not passed back to DSA, so phylink uses NA.
1553 * DT can specify RGMII for ports 0, 1.
1554 * For MDIO, port 8 can be RGMII_TXID.
1555 */
1556 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1557 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1558
1559 /* BCM63xx RGMII ports support RGMII */
1560 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4))
1561 phy_interface_set_rgmii(config->supported_interfaces);
1562
1563 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1564 MAC_10 | MAC_100;
1565
1566 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1567 * Note: the original code also exclulded Gigagbit for MII, RevMII
1568 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1569 * so will be excluded by the generic validator implementation.
1570 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1571 */
1572 if (!(is5325(dev) || is5365(dev)))
1573 config->mac_capabilities |= MAC_1000;
1574
1575 /* Get the implementation specific capabilities */
1576 if (dev->ops->phylink_get_caps)
1577 dev->ops->phylink_get_caps(dev, port, config);
1578}
1579
1580static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config,
1581 phy_interface_t interface)
1582{
1583 struct dsa_port *dp = dsa_phylink_to_port(config);
1584 struct b53_device *dev = dp->ds->priv;
1585
1586 if (!dev->ops->phylink_mac_select_pcs)
1587 return NULL;
1588
1589 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface);
1590}
1591
1592static void b53_phylink_mac_config(struct phylink_config *config,
1593 unsigned int mode,
1594 const struct phylink_link_state *state)
1595{
1596 struct dsa_port *dp = dsa_phylink_to_port(config);
1597 phy_interface_t interface = state->interface;
1598 struct dsa_switch *ds = dp->ds;
1599 struct b53_device *dev = ds->priv;
1600 int port = dp->index;
1601
1602 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4))
1603 b53_adjust_63xx_rgmii(ds, port, interface);
1604
1605 if (mode == MLO_AN_FIXED) {
1606 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface))
1607 b53_adjust_531x5_rgmii(ds, port, interface);
1608
1609 /* configure MII port if necessary */
1610 if (is5325(dev))
1611 b53_adjust_5325_mii(ds, port);
1612 }
1613}
1614
1615static void b53_phylink_mac_link_down(struct phylink_config *config,
1616 unsigned int mode,
1617 phy_interface_t interface)
1618{
1619 struct dsa_port *dp = dsa_phylink_to_port(config);
1620 struct b53_device *dev = dp->ds->priv;
1621 int port = dp->index;
1622
1623 if (mode == MLO_AN_PHY) {
1624 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4))
1625 b53_force_link(dev, port, false);
1626 return;
1627 }
1628
1629 if (mode == MLO_AN_FIXED) {
1630 b53_force_link(dev, port, false);
1631 return;
1632 }
1633
1634 if (phy_interface_mode_is_8023z(interface) &&
1635 dev->ops->serdes_link_set)
1636 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1637}
1638
1639static void b53_phylink_mac_link_up(struct phylink_config *config,
1640 struct phy_device *phydev,
1641 unsigned int mode,
1642 phy_interface_t interface,
1643 int speed, int duplex,
1644 bool tx_pause, bool rx_pause)
1645{
1646 struct dsa_port *dp = dsa_phylink_to_port(config);
1647 struct dsa_switch *ds = dp->ds;
1648 struct b53_device *dev = ds->priv;
1649 struct ethtool_keee *p = &dev->ports[dp->index].eee;
1650 int port = dp->index;
1651
1652 if (mode == MLO_AN_PHY) {
1653 /* Re-negotiate EEE if it was enabled already */
1654 p->eee_enabled = b53_eee_init(ds, port, phydev);
1655
1656 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4)) {
1657 b53_force_port_config(dev, port, speed, duplex,
1658 tx_pause, rx_pause);
1659 b53_force_link(dev, port, true);
1660 }
1661
1662 return;
1663 }
1664
1665 if (mode == MLO_AN_FIXED) {
1666 /* Force flow control on BCM5301x's CPU port */
1667 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1668 tx_pause = rx_pause = true;
1669
1670 b53_force_port_config(dev, port, speed, duplex,
1671 tx_pause, rx_pause);
1672 b53_force_link(dev, port, true);
1673 return;
1674 }
1675
1676 if (phy_interface_mode_is_8023z(interface) &&
1677 dev->ops->serdes_link_set)
1678 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1679}
1680
1681int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1682 struct netlink_ext_ack *extack)
1683{
1684 struct b53_device *dev = ds->priv;
1685
1686 if (dev->vlan_filtering != vlan_filtering) {
1687 dev->vlan_filtering = vlan_filtering;
1688 b53_apply_config(dev);
1689 }
1690
1691 return 0;
1692}
1693EXPORT_SYMBOL(b53_vlan_filtering);
1694
1695static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1696 const struct switchdev_obj_port_vlan *vlan)
1697{
1698 struct b53_device *dev = ds->priv;
1699
1700 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1701 * receiving VLAN tagged frames at all, we can still allow the port to
1702 * be configured for egress untagged.
1703 */
1704 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1705 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1706 return -EINVAL;
1707
1708 if (vlan->vid >= dev->num_vlans)
1709 return -ERANGE;
1710
1711 b53_enable_vlan(dev, port, true, dev->vlan_filtering);
1712
1713 return 0;
1714}
1715
1716int b53_vlan_add(struct dsa_switch *ds, int port,
1717 const struct switchdev_obj_port_vlan *vlan,
1718 struct netlink_ext_ack *extack)
1719{
1720 struct b53_device *dev = ds->priv;
1721 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1722 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1723 struct b53_vlan *vl;
1724 u16 old_pvid, new_pvid;
1725 int err;
1726
1727 err = b53_vlan_prepare(ds, port, vlan);
1728 if (err)
1729 return err;
1730
1731 if (vlan->vid == 0)
1732 return 0;
1733
1734 old_pvid = dev->ports[port].pvid;
1735 if (pvid)
1736 new_pvid = vlan->vid;
1737 else if (!pvid && vlan->vid == old_pvid)
1738 new_pvid = b53_default_pvid(dev);
1739 else
1740 new_pvid = old_pvid;
1741 dev->ports[port].pvid = new_pvid;
1742
1743 vl = &dev->vlans[vlan->vid];
1744
1745 if (dsa_is_cpu_port(ds, port))
1746 untagged = false;
1747
1748 vl->members |= BIT(port);
1749 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1750 vl->untag |= BIT(port);
1751 else
1752 vl->untag &= ~BIT(port);
1753
1754 if (!dev->vlan_filtering)
1755 return 0;
1756
1757 b53_set_vlan_entry(dev, vlan->vid, vl);
1758 b53_fast_age_vlan(dev, vlan->vid);
1759
1760 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) {
1761 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1762 new_pvid);
1763 b53_fast_age_vlan(dev, old_pvid);
1764 }
1765
1766 return 0;
1767}
1768EXPORT_SYMBOL(b53_vlan_add);
1769
1770int b53_vlan_del(struct dsa_switch *ds, int port,
1771 const struct switchdev_obj_port_vlan *vlan)
1772{
1773 struct b53_device *dev = ds->priv;
1774 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1775 struct b53_vlan *vl;
1776 u16 pvid;
1777
1778 if (vlan->vid == 0)
1779 return 0;
1780
1781 pvid = dev->ports[port].pvid;
1782
1783 vl = &dev->vlans[vlan->vid];
1784
1785 vl->members &= ~BIT(port);
1786
1787 if (pvid == vlan->vid)
1788 pvid = b53_default_pvid(dev);
1789 dev->ports[port].pvid = pvid;
1790
1791 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1792 vl->untag &= ~(BIT(port));
1793
1794 if (!dev->vlan_filtering)
1795 return 0;
1796
1797 b53_set_vlan_entry(dev, vlan->vid, vl);
1798 b53_fast_age_vlan(dev, vlan->vid);
1799
1800 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1801 b53_fast_age_vlan(dev, pvid);
1802
1803 return 0;
1804}
1805EXPORT_SYMBOL(b53_vlan_del);
1806
1807/* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
1808static int b53_arl_op_wait(struct b53_device *dev)
1809{
1810 unsigned int timeout = 10;
1811 u8 reg;
1812
1813 do {
1814 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1815 if (!(reg & ARLTBL_START_DONE))
1816 return 0;
1817
1818 usleep_range(1000, 2000);
1819 } while (timeout--);
1820
1821 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1822
1823 return -ETIMEDOUT;
1824}
1825
1826static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1827{
1828 u8 reg;
1829
1830 if (op > ARLTBL_RW)
1831 return -EINVAL;
1832
1833 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1834 reg |= ARLTBL_START_DONE;
1835 if (op)
1836 reg |= ARLTBL_RW;
1837 else
1838 reg &= ~ARLTBL_RW;
1839 if (dev->vlan_enabled)
1840 reg &= ~ARLTBL_IVL_SVL_SELECT;
1841 else
1842 reg |= ARLTBL_IVL_SVL_SELECT;
1843 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1844
1845 return b53_arl_op_wait(dev);
1846}
1847
1848static void b53_arl_read_entry_25(struct b53_device *dev,
1849 struct b53_arl_entry *ent, u8 idx)
1850{
1851 u8 vid_entry;
1852 u64 mac_vid;
1853
1854 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_VID_ENTRY_25(idx),
1855 &vid_entry);
1856 b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx),
1857 &mac_vid);
1858 b53_arl_to_entry_25(ent, mac_vid, vid_entry);
1859}
1860
1861static void b53_arl_write_entry_25(struct b53_device *dev,
1862 const struct b53_arl_entry *ent, u8 idx)
1863{
1864 u8 vid_entry;
1865 u64 mac_vid;
1866
1867 b53_arl_from_entry_25(&mac_vid, &vid_entry, ent);
1868 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_VID_ENTRY_25(idx), vid_entry);
1869 b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx),
1870 mac_vid);
1871}
1872
1873static void b53_arl_read_entry_89(struct b53_device *dev,
1874 struct b53_arl_entry *ent, u8 idx)
1875{
1876 u64 mac_vid;
1877 u16 fwd_entry;
1878
1879 b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx),
1880 &mac_vid);
1881 b53_read16(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry);
1882 b53_arl_to_entry_89(ent, mac_vid, fwd_entry);
1883}
1884
1885static void b53_arl_write_entry_89(struct b53_device *dev,
1886 const struct b53_arl_entry *ent, u8 idx)
1887{
1888 u32 fwd_entry;
1889 u64 mac_vid;
1890
1891 b53_arl_from_entry_89(&mac_vid, &fwd_entry, ent);
1892 b53_write64(dev, B53_ARLIO_PAGE,
1893 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1894 b53_write16(dev, B53_ARLIO_PAGE,
1895 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1896}
1897
1898static void b53_arl_read_entry_95(struct b53_device *dev,
1899 struct b53_arl_entry *ent, u8 idx)
1900{
1901 u32 fwd_entry;
1902 u64 mac_vid;
1903
1904 b53_read64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx),
1905 &mac_vid);
1906 b53_read32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx), &fwd_entry);
1907 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1908}
1909
1910static void b53_arl_write_entry_95(struct b53_device *dev,
1911 const struct b53_arl_entry *ent, u8 idx)
1912{
1913 u32 fwd_entry;
1914 u64 mac_vid;
1915
1916 b53_arl_from_entry(&mac_vid, &fwd_entry, ent);
1917 b53_write64(dev, B53_ARLIO_PAGE, B53_ARLTBL_MAC_VID_ENTRY(idx),
1918 mac_vid);
1919 b53_write32(dev, B53_ARLIO_PAGE, B53_ARLTBL_DATA_ENTRY(idx),
1920 fwd_entry);
1921}
1922
1923static int b53_arl_read(struct b53_device *dev, const u8 *mac,
1924 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1925{
1926 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1927 unsigned int i;
1928 int ret;
1929
1930 ret = b53_arl_op_wait(dev);
1931 if (ret)
1932 return ret;
1933
1934 bitmap_zero(free_bins, dev->num_arl_bins);
1935
1936 /* Read the bins */
1937 for (i = 0; i < dev->num_arl_bins; i++) {
1938 b53_arl_read_entry(dev, ent, i);
1939
1940 if (!ent->is_valid) {
1941 set_bit(i, free_bins);
1942 continue;
1943 }
1944 if (!ether_addr_equal(ent->mac, mac))
1945 continue;
1946 if (dev->vlan_enabled && ent->vid != vid)
1947 continue;
1948 *idx = i;
1949 return 0;
1950 }
1951
1952 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1953 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1954}
1955
1956static int b53_arl_op(struct b53_device *dev, int op, int port,
1957 const unsigned char *addr, u16 vid, bool is_valid)
1958{
1959 struct b53_arl_entry ent;
1960 u8 idx = 0;
1961 u64 mac;
1962 int ret;
1963
1964 /* Convert the array into a 64-bit MAC */
1965 mac = ether_addr_to_u64(addr);
1966
1967 /* Perform a read for the given MAC and VID */
1968 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1969 if (!is5325m(dev)) {
1970 if (is5325(dev) || is5365(dev))
1971 b53_write8(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1972 else
1973 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1974 }
1975
1976 /* Issue a read operation for this MAC */
1977 ret = b53_arl_rw_op(dev, 1);
1978 if (ret)
1979 return ret;
1980
1981 ret = b53_arl_read(dev, addr, vid, &ent, &idx);
1982
1983 /* If this is a read, just finish now */
1984 if (op)
1985 return ret;
1986
1987 switch (ret) {
1988 case -ETIMEDOUT:
1989 return ret;
1990 case -ENOSPC:
1991 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1992 addr, vid);
1993 return is_valid ? ret : 0;
1994 case -ENOENT:
1995 /* We could not find a matching MAC, so reset to a new entry */
1996 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1997 addr, vid, idx);
1998 break;
1999 default:
2000 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
2001 addr, vid, idx);
2002 break;
2003 }
2004
2005 /* For multicast address, the port is a bitmask and the validity
2006 * is determined by having at least one port being still active
2007 */
2008 if (!is_multicast_ether_addr(addr)) {
2009 ent.port = port;
2010 ent.is_valid = is_valid;
2011 } else {
2012 if (is_valid)
2013 ent.port |= BIT(port);
2014 else
2015 ent.port &= ~BIT(port);
2016
2017 ent.is_valid = !!(ent.port);
2018 }
2019
2020 ent.vid = vid;
2021 ent.is_static = true;
2022 ent.is_age = false;
2023 memcpy(ent.mac, addr, ETH_ALEN);
2024 b53_arl_write_entry(dev, &ent, idx);
2025
2026 return b53_arl_rw_op(dev, 0);
2027}
2028
2029int b53_fdb_add(struct dsa_switch *ds, int port,
2030 const unsigned char *addr, u16 vid,
2031 struct dsa_db db)
2032{
2033 struct b53_device *priv = ds->priv;
2034 int ret;
2035
2036 mutex_lock(&priv->arl_mutex);
2037 ret = b53_arl_op(priv, 0, port, addr, vid, true);
2038 mutex_unlock(&priv->arl_mutex);
2039
2040 return ret;
2041}
2042EXPORT_SYMBOL(b53_fdb_add);
2043
2044int b53_fdb_del(struct dsa_switch *ds, int port,
2045 const unsigned char *addr, u16 vid,
2046 struct dsa_db db)
2047{
2048 struct b53_device *priv = ds->priv;
2049 int ret;
2050
2051 mutex_lock(&priv->arl_mutex);
2052 ret = b53_arl_op(priv, 0, port, addr, vid, false);
2053 mutex_unlock(&priv->arl_mutex);
2054
2055 return ret;
2056}
2057EXPORT_SYMBOL(b53_fdb_del);
2058
2059static void b53_read_arl_srch_ctl(struct b53_device *dev, u8 *val)
2060{
2061 u8 offset;
2062
2063 if (is5325(dev) || is5365(dev))
2064 offset = B53_ARL_SRCH_CTL_25;
2065 else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) ||
2066 is63xx(dev))
2067 offset = B53_ARL_SRCH_CTL_89;
2068 else
2069 offset = B53_ARL_SRCH_CTL;
2070
2071 if (is63xx(dev)) {
2072 u16 val16;
2073
2074 b53_read16(dev, B53_ARLIO_PAGE, offset, &val16);
2075 *val = val16 & 0xff;
2076 } else {
2077 b53_read8(dev, B53_ARLIO_PAGE, offset, val);
2078 }
2079}
2080
2081static void b53_write_arl_srch_ctl(struct b53_device *dev, u8 val)
2082{
2083 u8 offset;
2084
2085 if (is5325(dev) || is5365(dev))
2086 offset = B53_ARL_SRCH_CTL_25;
2087 else if (dev->chip_id == BCM5389_DEVICE_ID || is5397_98(dev) ||
2088 is63xx(dev))
2089 offset = B53_ARL_SRCH_CTL_89;
2090 else
2091 offset = B53_ARL_SRCH_CTL;
2092
2093 if (is63xx(dev))
2094 b53_write16(dev, B53_ARLIO_PAGE, offset, val);
2095 else
2096 b53_write8(dev, B53_ARLIO_PAGE, offset, val);
2097}
2098
2099static int b53_arl_search_wait(struct b53_device *dev)
2100{
2101 unsigned int timeout = 1000;
2102 u8 reg;
2103
2104 do {
2105 b53_read_arl_srch_ctl(dev, &reg);
2106 if (!(reg & ARL_SRCH_STDN))
2107 return -ENOENT;
2108
2109 if (reg & ARL_SRCH_VLID)
2110 return 0;
2111
2112 usleep_range(1000, 2000);
2113 } while (timeout--);
2114
2115 return -ETIMEDOUT;
2116}
2117
2118static void b53_arl_search_read_25(struct b53_device *dev, u8 idx,
2119 struct b53_arl_entry *ent)
2120{
2121 u64 mac_vid;
2122 u8 ext;
2123
2124 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_EXT_25, &ext);
2125 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_0_MACVID_25,
2126 &mac_vid);
2127 b53_arl_search_to_entry_25(ent, mac_vid, ext);
2128}
2129
2130static void b53_arl_search_read_89(struct b53_device *dev, u8 idx,
2131 struct b53_arl_entry *ent)
2132{
2133 u16 fwd_entry;
2134 u64 mac_vid;
2135
2136 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_89,
2137 &mac_vid);
2138 b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_89, &fwd_entry);
2139 b53_arl_to_entry_89(ent, mac_vid, fwd_entry);
2140}
2141
2142static void b53_arl_search_read_63xx(struct b53_device *dev, u8 idx,
2143 struct b53_arl_entry *ent)
2144{
2145 u16 fwd_entry;
2146 u64 mac_vid;
2147
2148 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_MACVID_63XX,
2149 &mac_vid);
2150 b53_read16(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSLT_63XX, &fwd_entry);
2151 b53_arl_search_to_entry_63xx(ent, mac_vid, fwd_entry);
2152}
2153
2154static void b53_arl_search_read_95(struct b53_device *dev, u8 idx,
2155 struct b53_arl_entry *ent)
2156{
2157 u32 fwd_entry;
2158 u64 mac_vid;
2159
2160 b53_read64(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL_MACVID(idx),
2161 &mac_vid);
2162 b53_read32(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_RSTL(idx),
2163 &fwd_entry);
2164 b53_arl_to_entry(ent, mac_vid, fwd_entry);
2165}
2166
2167static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2168 dsa_fdb_dump_cb_t *cb, void *data)
2169{
2170 if (!ent->is_valid)
2171 return 0;
2172
2173 if (is_multicast_ether_addr(ent->mac))
2174 return 0;
2175
2176 if (port != ent->port)
2177 return 0;
2178
2179 return cb(ent->mac, ent->vid, ent->is_static, data);
2180}
2181
2182int b53_fdb_dump(struct dsa_switch *ds, int port,
2183 dsa_fdb_dump_cb_t *cb, void *data)
2184{
2185 unsigned int count = 0, results_per_hit = 1;
2186 struct b53_device *priv = ds->priv;
2187 struct b53_arl_entry results[2];
2188 int ret;
2189
2190 if (priv->num_arl_bins > 2)
2191 results_per_hit = 2;
2192
2193 mutex_lock(&priv->arl_mutex);
2194
2195 /* Start search operation */
2196 b53_write_arl_srch_ctl(priv, ARL_SRCH_STDN);
2197
2198 do {
2199 ret = b53_arl_search_wait(priv);
2200 if (ret)
2201 break;
2202
2203 b53_arl_search_read(priv, 0, &results[0]);
2204 ret = b53_fdb_copy(port, &results[0], cb, data);
2205 if (ret)
2206 break;
2207
2208 if (results_per_hit == 2) {
2209 b53_arl_search_read(priv, 1, &results[1]);
2210 ret = b53_fdb_copy(port, &results[1], cb, data);
2211 if (ret)
2212 break;
2213
2214 if (!results[0].is_valid && !results[1].is_valid)
2215 break;
2216 }
2217
2218 } while (count++ < b53_max_arl_entries(priv) / results_per_hit);
2219
2220 mutex_unlock(&priv->arl_mutex);
2221
2222 return ret;
2223}
2224EXPORT_SYMBOL(b53_fdb_dump);
2225
2226int b53_mdb_add(struct dsa_switch *ds, int port,
2227 const struct switchdev_obj_port_mdb *mdb,
2228 struct dsa_db db)
2229{
2230 struct b53_device *priv = ds->priv;
2231 int ret;
2232
2233 /* 5325 and 5365 require some more massaging, but could
2234 * be supported eventually
2235 */
2236 if (is5325(priv) || is5365(priv))
2237 return -EOPNOTSUPP;
2238
2239 mutex_lock(&priv->arl_mutex);
2240 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
2241 mutex_unlock(&priv->arl_mutex);
2242
2243 return ret;
2244}
2245EXPORT_SYMBOL(b53_mdb_add);
2246
2247int b53_mdb_del(struct dsa_switch *ds, int port,
2248 const struct switchdev_obj_port_mdb *mdb,
2249 struct dsa_db db)
2250{
2251 struct b53_device *priv = ds->priv;
2252 int ret;
2253
2254 mutex_lock(&priv->arl_mutex);
2255 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
2256 mutex_unlock(&priv->arl_mutex);
2257 if (ret)
2258 dev_err(ds->dev, "failed to delete MDB entry\n");
2259
2260 return ret;
2261}
2262EXPORT_SYMBOL(b53_mdb_del);
2263
2264int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
2265 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
2266{
2267 struct b53_device *dev = ds->priv;
2268 struct b53_vlan *vl;
2269 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
2270 u16 pvlan, reg, pvid;
2271 unsigned int i;
2272
2273 /* On 7278, port 7 which connects to the ASP should only receive
2274 * traffic from matching CFP rules.
2275 */
2276 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
2277 return -EINVAL;
2278
2279 pvid = b53_default_pvid(dev);
2280 vl = &dev->vlans[pvid];
2281
2282 if (dev->vlan_filtering) {
2283 /* Make this port leave the all VLANs join since we will have
2284 * proper VLAN entries from now on
2285 */
2286 if (is58xx(dev)) {
2287 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN,
2288 &reg);
2289 reg &= ~BIT(port);
2290 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
2291 reg &= ~BIT(cpu_port);
2292 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN,
2293 reg);
2294 }
2295
2296 b53_get_vlan_entry(dev, pvid, vl);
2297 vl->members &= ~BIT(port);
2298 b53_set_vlan_entry(dev, pvid, vl);
2299 }
2300
2301 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
2302
2303 b53_for_each_port(dev, i) {
2304 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2305 continue;
2306
2307 /* Add this local port to the remote port VLAN control
2308 * membership and update the remote port bitmask
2309 */
2310 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
2311 reg |= BIT(port);
2312 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
2313 dev->ports[i].vlan_ctl_mask = reg;
2314
2315 pvlan |= BIT(i);
2316 }
2317
2318 /* Disable redirection of unknown SA to the CPU port */
2319 b53_set_eap_mode(dev, port, EAP_MODE_BASIC);
2320
2321 /* Configure the local port VLAN control membership to include
2322 * remote ports and update the local port bitmask
2323 */
2324 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
2325 dev->ports[port].vlan_ctl_mask = pvlan;
2326
2327 return 0;
2328}
2329EXPORT_SYMBOL(b53_br_join);
2330
2331void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
2332{
2333 struct b53_device *dev = ds->priv;
2334 struct b53_vlan *vl;
2335 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
2336 unsigned int i;
2337 u16 pvlan, reg, pvid;
2338
2339 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
2340
2341 b53_for_each_port(dev, i) {
2342 /* Don't touch the remaining ports */
2343 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2344 continue;
2345
2346 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
2347 reg &= ~BIT(port);
2348 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
2349 dev->ports[port].vlan_ctl_mask = reg;
2350
2351 /* Prevent self removal to preserve isolation */
2352 if (port != i)
2353 pvlan &= ~BIT(i);
2354 }
2355
2356 /* Enable redirection of unknown SA to the CPU port */
2357 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED);
2358
2359 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
2360 dev->ports[port].vlan_ctl_mask = pvlan;
2361
2362 pvid = b53_default_pvid(dev);
2363 vl = &dev->vlans[pvid];
2364
2365 if (dev->vlan_filtering) {
2366 /* Make this port join all VLANs without VLAN entries */
2367 if (is58xx(dev)) {
2368 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
2369 reg |= BIT(port);
2370 if (!(reg & BIT(cpu_port)))
2371 reg |= BIT(cpu_port);
2372 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
2373 }
2374
2375 b53_get_vlan_entry(dev, pvid, vl);
2376 vl->members |= BIT(port);
2377 b53_set_vlan_entry(dev, pvid, vl);
2378 }
2379}
2380EXPORT_SYMBOL(b53_br_leave);
2381
2382void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
2383{
2384 struct b53_device *dev = ds->priv;
2385 u8 hw_state;
2386 u8 reg;
2387
2388 switch (state) {
2389 case BR_STATE_DISABLED:
2390 hw_state = PORT_CTRL_DIS_STATE;
2391 break;
2392 case BR_STATE_LISTENING:
2393 hw_state = PORT_CTRL_LISTEN_STATE;
2394 break;
2395 case BR_STATE_LEARNING:
2396 hw_state = PORT_CTRL_LEARN_STATE;
2397 break;
2398 case BR_STATE_FORWARDING:
2399 hw_state = PORT_CTRL_FWD_STATE;
2400 break;
2401 case BR_STATE_BLOCKING:
2402 hw_state = PORT_CTRL_BLOCK_STATE;
2403 break;
2404 default:
2405 dev_err(ds->dev, "invalid STP state: %d\n", state);
2406 return;
2407 }
2408
2409 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
2410 reg &= ~PORT_CTRL_STP_STATE_MASK;
2411 reg |= hw_state;
2412 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2413}
2414EXPORT_SYMBOL(b53_br_set_stp_state);
2415
2416void b53_br_fast_age(struct dsa_switch *ds, int port)
2417{
2418 struct b53_device *dev = ds->priv;
2419
2420 if (b53_fast_age_port(dev, port))
2421 dev_err(ds->dev, "fast ageing failed\n");
2422}
2423EXPORT_SYMBOL(b53_br_fast_age);
2424
2425int b53_br_flags_pre(struct dsa_switch *ds, int port,
2426 struct switchdev_brport_flags flags,
2427 struct netlink_ext_ack *extack)
2428{
2429 struct b53_device *dev = ds->priv;
2430 unsigned long mask = (BR_FLOOD | BR_MCAST_FLOOD | BR_ISOLATED);
2431
2432 if (!is5325(dev))
2433 mask |= BR_LEARNING;
2434
2435 if (flags.mask & ~mask)
2436 return -EINVAL;
2437
2438 return 0;
2439}
2440EXPORT_SYMBOL(b53_br_flags_pre);
2441
2442int b53_br_flags(struct dsa_switch *ds, int port,
2443 struct switchdev_brport_flags flags,
2444 struct netlink_ext_ack *extack)
2445{
2446 if (flags.mask & BR_FLOOD)
2447 b53_port_set_ucast_flood(ds->priv, port,
2448 !!(flags.val & BR_FLOOD));
2449 if (flags.mask & BR_MCAST_FLOOD)
2450 b53_port_set_mcast_flood(ds->priv, port,
2451 !!(flags.val & BR_MCAST_FLOOD));
2452 if (flags.mask & BR_LEARNING)
2453 b53_port_set_learning(ds->priv, port,
2454 !!(flags.val & BR_LEARNING));
2455 if (flags.mask & BR_ISOLATED)
2456 b53_port_set_isolated(ds->priv, port,
2457 !!(flags.val & BR_ISOLATED));
2458
2459 return 0;
2460}
2461EXPORT_SYMBOL(b53_br_flags);
2462
2463static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2464{
2465 /* Broadcom switches will accept enabling Broadcom tags on the
2466 * following ports: 5, 7 and 8, any other port is not supported
2467 */
2468 switch (port) {
2469 case B53_CPU_PORT_25:
2470 case 7:
2471 case B53_CPU_PORT:
2472 return true;
2473 }
2474
2475 return false;
2476}
2477
2478static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2479 enum dsa_tag_protocol tag_protocol)
2480{
2481 bool ret = b53_possible_cpu_port(ds, port);
2482
2483 if (!ret) {
2484 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2485 port);
2486 return ret;
2487 }
2488
2489 switch (tag_protocol) {
2490 case DSA_TAG_PROTO_BRCM:
2491 case DSA_TAG_PROTO_BRCM_PREPEND:
2492 dev_warn(ds->dev,
2493 "Port %d is stacked to Broadcom tag switch\n", port);
2494 ret = false;
2495 break;
2496 default:
2497 ret = true;
2498 break;
2499 }
2500
2501 return ret;
2502}
2503
2504enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2505 enum dsa_tag_protocol mprot)
2506{
2507 struct b53_device *dev = ds->priv;
2508
2509 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2510 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2511 goto out;
2512 }
2513
2514 /* Older models require different 6 byte tags */
2515 if (is5325(dev) || is5365(dev)) {
2516 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY_FCS;
2517 goto out;
2518 } else if (is63xx(dev)) {
2519 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2520 goto out;
2521 }
2522
2523 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2524 * which requires us to use the prepended Broadcom tag type
2525 */
2526 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2527 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2528 goto out;
2529 }
2530
2531 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2532out:
2533 return dev->tag_protocol;
2534}
2535EXPORT_SYMBOL(b53_get_tag_protocol);
2536
2537int b53_mirror_add(struct dsa_switch *ds, int port,
2538 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2539 struct netlink_ext_ack *extack)
2540{
2541 struct b53_device *dev = ds->priv;
2542 u16 reg, loc;
2543
2544 if (ingress)
2545 loc = B53_IG_MIR_CTL;
2546 else
2547 loc = B53_EG_MIR_CTL;
2548
2549 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2550 reg |= BIT(port);
2551 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2552
2553 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2554 reg &= ~CAP_PORT_MASK;
2555 reg |= mirror->to_local_port;
2556 reg |= MIRROR_EN;
2557 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2558
2559 return 0;
2560}
2561EXPORT_SYMBOL(b53_mirror_add);
2562
2563void b53_mirror_del(struct dsa_switch *ds, int port,
2564 struct dsa_mall_mirror_tc_entry *mirror)
2565{
2566 struct b53_device *dev = ds->priv;
2567 bool loc_disable = false, other_loc_disable = false;
2568 u16 reg, loc;
2569
2570 if (mirror->ingress)
2571 loc = B53_IG_MIR_CTL;
2572 else
2573 loc = B53_EG_MIR_CTL;
2574
2575 /* Update the desired ingress/egress register */
2576 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2577 reg &= ~BIT(port);
2578 if (!(reg & MIRROR_MASK))
2579 loc_disable = true;
2580 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2581
2582 /* Now look at the other one to know if we can disable mirroring
2583 * entirely
2584 */
2585 if (mirror->ingress)
2586 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
2587 else
2588 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
2589 if (!(reg & MIRROR_MASK))
2590 other_loc_disable = true;
2591
2592 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2593 /* Both no longer have ports, let's disable mirroring */
2594 if (loc_disable && other_loc_disable) {
2595 reg &= ~MIRROR_EN;
2596 reg &= ~mirror->to_local_port;
2597 }
2598 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2599}
2600EXPORT_SYMBOL(b53_mirror_del);
2601
2602/* Returns 0 if EEE was not enabled, or 1 otherwise
2603 */
2604int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2605{
2606 int ret;
2607
2608 if (!b53_support_eee(ds, port))
2609 return 0;
2610
2611 ret = phy_init_eee(phy, false);
2612 if (ret)
2613 return 0;
2614
2615 b53_eee_enable_set(ds, port, true);
2616
2617 return 1;
2618}
2619EXPORT_SYMBOL(b53_eee_init);
2620
2621bool b53_support_eee(struct dsa_switch *ds, int port)
2622{
2623 struct b53_device *dev = ds->priv;
2624
2625 return !is5325(dev) && !is5365(dev) && !is63xx(dev);
2626}
2627EXPORT_SYMBOL(b53_support_eee);
2628
2629int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e)
2630{
2631 struct b53_device *dev = ds->priv;
2632 struct ethtool_keee *p = &dev->ports[port].eee;
2633
2634 p->eee_enabled = e->eee_enabled;
2635 b53_eee_enable_set(ds, port, e->eee_enabled);
2636
2637 return 0;
2638}
2639EXPORT_SYMBOL(b53_set_mac_eee);
2640
2641static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2642{
2643 struct b53_device *dev = ds->priv;
2644 bool enable_jumbo;
2645 bool allow_10_100;
2646
2647 if (is5325(dev) || is5365(dev))
2648 return 0;
2649
2650 if (!dsa_is_cpu_port(ds, port))
2651 return 0;
2652
2653 enable_jumbo = (mtu > ETH_DATA_LEN);
2654 allow_10_100 = !is63xx(dev);
2655
2656 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2657}
2658
2659static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2660{
2661 struct b53_device *dev = ds->priv;
2662
2663 if (is5325(dev) || is5365(dev))
2664 return B53_MAX_MTU_25;
2665
2666 return B53_MAX_MTU;
2667}
2668
2669int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2670{
2671 struct b53_device *dev = ds->priv;
2672 u32 atc;
2673 int reg;
2674
2675 if (is63xx(dev))
2676 reg = B53_AGING_TIME_CONTROL_63XX;
2677 else
2678 reg = B53_AGING_TIME_CONTROL;
2679
2680 if (dev->chip_id == BCM53101_DEVICE_ID)
2681 atc = DIV_ROUND_CLOSEST(msecs, 500);
2682 else
2683 atc = DIV_ROUND_CLOSEST(msecs, 1000);
2684
2685 if (!is5325(dev) && !is5365(dev))
2686 atc |= AGE_CHANGE;
2687
2688 b53_write32(dev, B53_MGMT_PAGE, reg, atc);
2689
2690 return 0;
2691}
2692EXPORT_SYMBOL_GPL(b53_set_ageing_time);
2693
2694static const struct phylink_mac_ops b53_phylink_mac_ops = {
2695 .mac_select_pcs = b53_phylink_mac_select_pcs,
2696 .mac_config = b53_phylink_mac_config,
2697 .mac_link_down = b53_phylink_mac_link_down,
2698 .mac_link_up = b53_phylink_mac_link_up,
2699};
2700
2701static const struct dsa_switch_ops b53_switch_ops = {
2702 .get_tag_protocol = b53_get_tag_protocol,
2703 .setup = b53_setup,
2704 .teardown = b53_teardown,
2705 .get_strings = b53_get_strings,
2706 .get_ethtool_stats = b53_get_ethtool_stats,
2707 .get_sset_count = b53_get_sset_count,
2708 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2709 .phy_read = b53_phy_read16,
2710 .phy_write = b53_phy_write16,
2711 .phylink_get_caps = b53_phylink_get_caps,
2712 .port_setup = b53_setup_port,
2713 .port_enable = b53_enable_port,
2714 .port_disable = b53_disable_port,
2715 .support_eee = b53_support_eee,
2716 .set_mac_eee = b53_set_mac_eee,
2717 .set_ageing_time = b53_set_ageing_time,
2718 .port_bridge_join = b53_br_join,
2719 .port_bridge_leave = b53_br_leave,
2720 .port_pre_bridge_flags = b53_br_flags_pre,
2721 .port_bridge_flags = b53_br_flags,
2722 .port_stp_state_set = b53_br_set_stp_state,
2723 .port_fast_age = b53_br_fast_age,
2724 .port_vlan_filtering = b53_vlan_filtering,
2725 .port_vlan_add = b53_vlan_add,
2726 .port_vlan_del = b53_vlan_del,
2727 .port_fdb_dump = b53_fdb_dump,
2728 .port_fdb_add = b53_fdb_add,
2729 .port_fdb_del = b53_fdb_del,
2730 .port_mirror_add = b53_mirror_add,
2731 .port_mirror_del = b53_mirror_del,
2732 .port_mdb_add = b53_mdb_add,
2733 .port_mdb_del = b53_mdb_del,
2734 .port_max_mtu = b53_get_max_mtu,
2735 .port_change_mtu = b53_change_mtu,
2736};
2737
2738static const struct b53_arl_ops b53_arl_ops_25 = {
2739 .arl_read_entry = b53_arl_read_entry_25,
2740 .arl_write_entry = b53_arl_write_entry_25,
2741 .arl_search_read = b53_arl_search_read_25,
2742};
2743
2744static const struct b53_arl_ops b53_arl_ops_89 = {
2745 .arl_read_entry = b53_arl_read_entry_89,
2746 .arl_write_entry = b53_arl_write_entry_89,
2747 .arl_search_read = b53_arl_search_read_89,
2748};
2749
2750static const struct b53_arl_ops b53_arl_ops_63xx = {
2751 .arl_read_entry = b53_arl_read_entry_89,
2752 .arl_write_entry = b53_arl_write_entry_89,
2753 .arl_search_read = b53_arl_search_read_63xx,
2754};
2755
2756static const struct b53_arl_ops b53_arl_ops_95 = {
2757 .arl_read_entry = b53_arl_read_entry_95,
2758 .arl_write_entry = b53_arl_write_entry_95,
2759 .arl_search_read = b53_arl_search_read_95,
2760};
2761
2762struct b53_chip_data {
2763 u32 chip_id;
2764 const char *dev_name;
2765 u16 vlans;
2766 u16 enabled_ports;
2767 u8 imp_port;
2768 u8 cpu_port;
2769 u8 vta_regs[3];
2770 u8 arl_bins;
2771 u16 arl_buckets;
2772 u8 duplex_reg;
2773 u8 jumbo_pm_reg;
2774 u8 jumbo_size_reg;
2775 const struct b53_arl_ops *arl_ops;
2776};
2777
2778#define B53_VTA_REGS \
2779 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2780#define B53_VTA_REGS_9798 \
2781 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2782#define B53_VTA_REGS_63XX \
2783 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2784
2785static const struct b53_chip_data b53_switch_chips[] = {
2786 {
2787 .chip_id = BCM5325_DEVICE_ID,
2788 .dev_name = "BCM5325",
2789 .vlans = 16,
2790 .enabled_ports = 0x3f,
2791 .arl_bins = 2,
2792 .arl_buckets = 1024,
2793 .imp_port = 5,
2794 .duplex_reg = B53_DUPLEX_STAT_FE,
2795 .arl_ops = &b53_arl_ops_25,
2796 },
2797 {
2798 .chip_id = BCM5365_DEVICE_ID,
2799 .dev_name = "BCM5365",
2800 .vlans = 256,
2801 .enabled_ports = 0x3f,
2802 .arl_bins = 2,
2803 .arl_buckets = 1024,
2804 .imp_port = 5,
2805 .duplex_reg = B53_DUPLEX_STAT_FE,
2806 .arl_ops = &b53_arl_ops_25,
2807 },
2808 {
2809 .chip_id = BCM5389_DEVICE_ID,
2810 .dev_name = "BCM5389",
2811 .vlans = 4096,
2812 .enabled_ports = 0x11f,
2813 .arl_bins = 4,
2814 .arl_buckets = 1024,
2815 .imp_port = 8,
2816 .vta_regs = B53_VTA_REGS,
2817 .duplex_reg = B53_DUPLEX_STAT_GE,
2818 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2819 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2820 .arl_ops = &b53_arl_ops_89,
2821 },
2822 {
2823 .chip_id = BCM5395_DEVICE_ID,
2824 .dev_name = "BCM5395",
2825 .vlans = 4096,
2826 .enabled_ports = 0x11f,
2827 .arl_bins = 4,
2828 .arl_buckets = 1024,
2829 .imp_port = 8,
2830 .vta_regs = B53_VTA_REGS,
2831 .duplex_reg = B53_DUPLEX_STAT_GE,
2832 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2833 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2834 .arl_ops = &b53_arl_ops_95,
2835 },
2836 {
2837 .chip_id = BCM5397_DEVICE_ID,
2838 .dev_name = "BCM5397",
2839 .vlans = 4096,
2840 .enabled_ports = 0x11f,
2841 .arl_bins = 4,
2842 .arl_buckets = 1024,
2843 .imp_port = 8,
2844 .vta_regs = B53_VTA_REGS_9798,
2845 .duplex_reg = B53_DUPLEX_STAT_GE,
2846 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2847 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2848 .arl_ops = &b53_arl_ops_89,
2849 },
2850 {
2851 .chip_id = BCM5398_DEVICE_ID,
2852 .dev_name = "BCM5398",
2853 .vlans = 4096,
2854 .enabled_ports = 0x17f,
2855 .arl_bins = 4,
2856 .arl_buckets = 1024,
2857 .imp_port = 8,
2858 .vta_regs = B53_VTA_REGS_9798,
2859 .duplex_reg = B53_DUPLEX_STAT_GE,
2860 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2861 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2862 .arl_ops = &b53_arl_ops_89,
2863 },
2864 {
2865 .chip_id = BCM53101_DEVICE_ID,
2866 .dev_name = "BCM53101",
2867 .vlans = 4096,
2868 .enabled_ports = 0x11f,
2869 .arl_bins = 4,
2870 .arl_buckets = 512,
2871 .vta_regs = B53_VTA_REGS,
2872 .imp_port = 8,
2873 .duplex_reg = B53_DUPLEX_STAT_GE,
2874 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2875 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2876 .arl_ops = &b53_arl_ops_95,
2877 },
2878 {
2879 .chip_id = BCM53115_DEVICE_ID,
2880 .dev_name = "BCM53115",
2881 .vlans = 4096,
2882 .enabled_ports = 0x11f,
2883 .arl_bins = 4,
2884 .arl_buckets = 1024,
2885 .vta_regs = B53_VTA_REGS,
2886 .imp_port = 8,
2887 .duplex_reg = B53_DUPLEX_STAT_GE,
2888 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2889 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2890 .arl_ops = &b53_arl_ops_95,
2891 },
2892 {
2893 .chip_id = BCM53125_DEVICE_ID,
2894 .dev_name = "BCM53125",
2895 .vlans = 4096,
2896 .enabled_ports = 0x1ff,
2897 .arl_bins = 4,
2898 .arl_buckets = 1024,
2899 .imp_port = 8,
2900 .vta_regs = B53_VTA_REGS,
2901 .duplex_reg = B53_DUPLEX_STAT_GE,
2902 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2903 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2904 .arl_ops = &b53_arl_ops_95,
2905 },
2906 {
2907 .chip_id = BCM53128_DEVICE_ID,
2908 .dev_name = "BCM53128",
2909 .vlans = 4096,
2910 .enabled_ports = 0x1ff,
2911 .arl_bins = 4,
2912 .arl_buckets = 1024,
2913 .imp_port = 8,
2914 .vta_regs = B53_VTA_REGS,
2915 .duplex_reg = B53_DUPLEX_STAT_GE,
2916 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2917 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2918 .arl_ops = &b53_arl_ops_95,
2919 },
2920 {
2921 .chip_id = BCM63XX_DEVICE_ID,
2922 .dev_name = "BCM63xx",
2923 .vlans = 4096,
2924 .enabled_ports = 0, /* pdata must provide them */
2925 .arl_bins = 1,
2926 .arl_buckets = 4096,
2927 .imp_port = 8,
2928 .vta_regs = B53_VTA_REGS_63XX,
2929 .duplex_reg = B53_DUPLEX_STAT_63XX,
2930 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2931 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2932 .arl_ops = &b53_arl_ops_63xx,
2933 },
2934 {
2935 .chip_id = BCM53010_DEVICE_ID,
2936 .dev_name = "BCM53010",
2937 .vlans = 4096,
2938 .enabled_ports = 0x1bf,
2939 .arl_bins = 4,
2940 .arl_buckets = 1024,
2941 .imp_port = 8,
2942 .vta_regs = B53_VTA_REGS,
2943 .duplex_reg = B53_DUPLEX_STAT_GE,
2944 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2945 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2946 .arl_ops = &b53_arl_ops_95,
2947 },
2948 {
2949 .chip_id = BCM53011_DEVICE_ID,
2950 .dev_name = "BCM53011",
2951 .vlans = 4096,
2952 .enabled_ports = 0x1bf,
2953 .arl_bins = 4,
2954 .arl_buckets = 1024,
2955 .imp_port = 8,
2956 .vta_regs = B53_VTA_REGS,
2957 .duplex_reg = B53_DUPLEX_STAT_GE,
2958 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2959 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2960 .arl_ops = &b53_arl_ops_95,
2961 },
2962 {
2963 .chip_id = BCM53012_DEVICE_ID,
2964 .dev_name = "BCM53012",
2965 .vlans = 4096,
2966 .enabled_ports = 0x1bf,
2967 .arl_bins = 4,
2968 .arl_buckets = 1024,
2969 .imp_port = 8,
2970 .vta_regs = B53_VTA_REGS,
2971 .duplex_reg = B53_DUPLEX_STAT_GE,
2972 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2973 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2974 .arl_ops = &b53_arl_ops_95,
2975 },
2976 {
2977 .chip_id = BCM53018_DEVICE_ID,
2978 .dev_name = "BCM53018",
2979 .vlans = 4096,
2980 .enabled_ports = 0x1bf,
2981 .arl_bins = 4,
2982 .arl_buckets = 1024,
2983 .imp_port = 8,
2984 .vta_regs = B53_VTA_REGS,
2985 .duplex_reg = B53_DUPLEX_STAT_GE,
2986 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2987 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2988 .arl_ops = &b53_arl_ops_95,
2989 },
2990 {
2991 .chip_id = BCM53019_DEVICE_ID,
2992 .dev_name = "BCM53019",
2993 .vlans = 4096,
2994 .enabled_ports = 0x1bf,
2995 .arl_bins = 4,
2996 .arl_buckets = 1024,
2997 .imp_port = 8,
2998 .vta_regs = B53_VTA_REGS,
2999 .duplex_reg = B53_DUPLEX_STAT_GE,
3000 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3001 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3002 .arl_ops = &b53_arl_ops_95,
3003 },
3004 {
3005 .chip_id = BCM58XX_DEVICE_ID,
3006 .dev_name = "BCM585xx/586xx/88312",
3007 .vlans = 4096,
3008 .enabled_ports = 0x1ff,
3009 .arl_bins = 4,
3010 .arl_buckets = 1024,
3011 .imp_port = 8,
3012 .vta_regs = B53_VTA_REGS,
3013 .duplex_reg = B53_DUPLEX_STAT_GE,
3014 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3015 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3016 .arl_ops = &b53_arl_ops_95,
3017 },
3018 {
3019 .chip_id = BCM583XX_DEVICE_ID,
3020 .dev_name = "BCM583xx/11360",
3021 .vlans = 4096,
3022 .enabled_ports = 0x103,
3023 .arl_bins = 4,
3024 .arl_buckets = 1024,
3025 .imp_port = 8,
3026 .vta_regs = B53_VTA_REGS,
3027 .duplex_reg = B53_DUPLEX_STAT_GE,
3028 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3029 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3030 .arl_ops = &b53_arl_ops_95,
3031 },
3032 /* Starfighter 2 */
3033 {
3034 .chip_id = BCM4908_DEVICE_ID,
3035 .dev_name = "BCM4908",
3036 .vlans = 4096,
3037 .enabled_ports = 0x1bf,
3038 .arl_bins = 4,
3039 .arl_buckets = 256,
3040 .imp_port = 8,
3041 .vta_regs = B53_VTA_REGS,
3042 .duplex_reg = B53_DUPLEX_STAT_GE,
3043 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3044 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3045 .arl_ops = &b53_arl_ops_95,
3046 },
3047 {
3048 .chip_id = BCM7445_DEVICE_ID,
3049 .dev_name = "BCM7445",
3050 .vlans = 4096,
3051 .enabled_ports = 0x1ff,
3052 .arl_bins = 4,
3053 .arl_buckets = 1024,
3054 .imp_port = 8,
3055 .vta_regs = B53_VTA_REGS,
3056 .duplex_reg = B53_DUPLEX_STAT_GE,
3057 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3058 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3059 .arl_ops = &b53_arl_ops_95,
3060 },
3061 {
3062 .chip_id = BCM7278_DEVICE_ID,
3063 .dev_name = "BCM7278",
3064 .vlans = 4096,
3065 .enabled_ports = 0x1ff,
3066 .arl_bins = 4,
3067 .arl_buckets = 256,
3068 .imp_port = 8,
3069 .vta_regs = B53_VTA_REGS,
3070 .duplex_reg = B53_DUPLEX_STAT_GE,
3071 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3072 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3073 .arl_ops = &b53_arl_ops_95,
3074 },
3075 {
3076 .chip_id = BCM53134_DEVICE_ID,
3077 .dev_name = "BCM53134",
3078 .vlans = 4096,
3079 .enabled_ports = 0x12f,
3080 .imp_port = 8,
3081 .cpu_port = B53_CPU_PORT,
3082 .vta_regs = B53_VTA_REGS,
3083 .arl_bins = 4,
3084 .arl_buckets = 1024,
3085 .duplex_reg = B53_DUPLEX_STAT_GE,
3086 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
3087 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
3088 .arl_ops = &b53_arl_ops_95,
3089 },
3090};
3091
3092static int b53_switch_init(struct b53_device *dev)
3093{
3094 u32 chip_id = dev->chip_id;
3095 unsigned int i;
3096
3097 if (is63xx(dev))
3098 chip_id = BCM63XX_DEVICE_ID;
3099
3100 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
3101 const struct b53_chip_data *chip = &b53_switch_chips[i];
3102
3103 if (chip->chip_id == chip_id) {
3104 if (!dev->enabled_ports)
3105 dev->enabled_ports = chip->enabled_ports;
3106 dev->name = chip->dev_name;
3107 dev->duplex_reg = chip->duplex_reg;
3108 dev->vta_regs[0] = chip->vta_regs[0];
3109 dev->vta_regs[1] = chip->vta_regs[1];
3110 dev->vta_regs[2] = chip->vta_regs[2];
3111 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
3112 dev->imp_port = chip->imp_port;
3113 dev->num_vlans = chip->vlans;
3114 dev->num_arl_bins = chip->arl_bins;
3115 dev->num_arl_buckets = chip->arl_buckets;
3116 dev->arl_ops = chip->arl_ops;
3117 break;
3118 }
3119 }
3120
3121 /* check which BCM5325x version we have */
3122 if (is5325(dev)) {
3123 u8 vc4;
3124
3125 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
3126
3127 /* check reserved bits */
3128 switch (vc4 & 3) {
3129 case 1:
3130 /* BCM5325E */
3131 break;
3132 case 3:
3133 /* BCM5325F - do not use port 4 */
3134 dev->enabled_ports &= ~BIT(4);
3135 break;
3136 default:
3137/* On the BCM47XX SoCs this is the supported internal switch.*/
3138#ifndef CONFIG_BCM47XX
3139 /* BCM5325M */
3140 return -EINVAL;
3141#else
3142 break;
3143#endif
3144 }
3145 }
3146
3147 if (is5325e(dev))
3148 dev->num_arl_buckets = 512;
3149
3150 dev->num_ports = fls(dev->enabled_ports);
3151
3152 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
3153
3154 /* Include non standard CPU port built-in PHYs to be probed */
3155 if (is539x(dev) || is531x5(dev)) {
3156 for (i = 0; i < dev->num_ports; i++) {
3157 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
3158 !b53_possible_cpu_port(dev->ds, i))
3159 dev->ds->phys_mii_mask |= BIT(i);
3160 }
3161 }
3162
3163 dev->ports = devm_kcalloc(dev->dev,
3164 dev->num_ports, sizeof(struct b53_port),
3165 GFP_KERNEL);
3166 if (!dev->ports)
3167 return -ENOMEM;
3168
3169 dev->vlans = devm_kcalloc(dev->dev,
3170 dev->num_vlans, sizeof(struct b53_vlan),
3171 GFP_KERNEL);
3172 if (!dev->vlans)
3173 return -ENOMEM;
3174
3175 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
3176
3177 if (PTR_ERR(dev->reset_gpio) == -EPROBE_DEFER)
3178 return -EPROBE_DEFER;
3179
3180 return 0;
3181}
3182
3183struct b53_device *b53_switch_alloc(struct device *base,
3184 const struct b53_io_ops *ops,
3185 void *priv)
3186{
3187 struct dsa_switch *ds;
3188 struct b53_device *dev;
3189
3190 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
3191 if (!ds)
3192 return NULL;
3193
3194 ds->dev = base;
3195
3196 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
3197 if (!dev)
3198 return NULL;
3199
3200 ds->priv = dev;
3201 dev->dev = base;
3202
3203 dev->ds = ds;
3204 dev->priv = priv;
3205 dev->ops = ops;
3206 ds->ops = &b53_switch_ops;
3207 ds->phylink_mac_ops = &b53_phylink_mac_ops;
3208 dev->vlan_enabled = true;
3209 dev->vlan_filtering = false;
3210 /* Let DSA handle the case were multiple bridges span the same switch
3211 * device and different VLAN awareness settings are requested, which
3212 * would be breaking filtering semantics for any of the other bridge
3213 * devices. (not hardware supported)
3214 */
3215 ds->vlan_filtering_is_global = true;
3216
3217 mutex_init(&dev->reg_mutex);
3218 mutex_init(&dev->stats_mutex);
3219 mutex_init(&dev->arl_mutex);
3220
3221 return dev;
3222}
3223EXPORT_SYMBOL(b53_switch_alloc);
3224
3225int b53_switch_detect(struct b53_device *dev)
3226{
3227 u32 id32;
3228 u16 tmp;
3229 u8 id8;
3230 int ret;
3231
3232 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
3233 if (ret)
3234 return ret;
3235
3236 switch (id8) {
3237 case 0:
3238 /* BCM5325 and BCM5365 do not have this register so reads
3239 * return 0. But the read operation did succeed, so assume this
3240 * is one of them.
3241 *
3242 * Next check if we can write to the 5325's VTA register; for
3243 * 5365 it is read only.
3244 */
3245 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
3246 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
3247
3248 if (tmp == 0xf) {
3249 u32 phy_id;
3250 int val;
3251
3252 dev->chip_id = BCM5325_DEVICE_ID;
3253
3254 val = b53_phy_read16(dev->ds, 0, MII_PHYSID1);
3255 phy_id = (val & 0xffff) << 16;
3256 val = b53_phy_read16(dev->ds, 0, MII_PHYSID2);
3257 phy_id |= (val & 0xfff0);
3258
3259 if (phy_id == 0x00406330)
3260 dev->variant_id = B53_VARIANT_5325M;
3261 else if (phy_id == 0x0143bc30)
3262 dev->variant_id = B53_VARIANT_5325E;
3263 } else {
3264 dev->chip_id = BCM5365_DEVICE_ID;
3265 }
3266 break;
3267 case BCM5389_DEVICE_ID:
3268 case BCM5395_DEVICE_ID:
3269 case BCM5397_DEVICE_ID:
3270 case BCM5398_DEVICE_ID:
3271 dev->chip_id = id8;
3272 break;
3273 default:
3274 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
3275 if (ret)
3276 return ret;
3277
3278 switch (id32) {
3279 case BCM53101_DEVICE_ID:
3280 case BCM53115_DEVICE_ID:
3281 case BCM53125_DEVICE_ID:
3282 case BCM53128_DEVICE_ID:
3283 case BCM53010_DEVICE_ID:
3284 case BCM53011_DEVICE_ID:
3285 case BCM53012_DEVICE_ID:
3286 case BCM53018_DEVICE_ID:
3287 case BCM53019_DEVICE_ID:
3288 case BCM53134_DEVICE_ID:
3289 dev->chip_id = id32;
3290 break;
3291 default:
3292 dev_err(dev->dev,
3293 "unsupported switch detected (BCM53%02x/BCM%x)\n",
3294 id8, id32);
3295 return -ENODEV;
3296 }
3297 }
3298
3299 if (dev->chip_id == BCM5325_DEVICE_ID)
3300 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
3301 &dev->core_rev);
3302 else
3303 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
3304 &dev->core_rev);
3305}
3306EXPORT_SYMBOL(b53_switch_detect);
3307
3308int b53_switch_register(struct b53_device *dev)
3309{
3310 int ret;
3311
3312 if (dev->pdata) {
3313 dev->chip_id = dev->pdata->chip_id;
3314 dev->enabled_ports = dev->pdata->enabled_ports;
3315 }
3316
3317 if (!dev->chip_id && b53_switch_detect(dev))
3318 return -EINVAL;
3319
3320 ret = b53_switch_init(dev);
3321 if (ret)
3322 return ret;
3323
3324 dev_info(dev->dev, "found switch: %s, rev %i\n",
3325 dev->name, dev->core_rev);
3326
3327 return dsa_register_switch(dev->ds);
3328}
3329EXPORT_SYMBOL(b53_switch_register);
3330
3331MODULE_AUTHOR("Jonas Gorski <[email protected]>");
3332MODULE_DESCRIPTION("B53 switch library");
3333MODULE_LICENSE("Dual BSD/GPL");