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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2024 Linaro Ltd.
5 */
6
7#include <linux/array_size.h>
8#include <linux/log2.h>
9
10#include "../ipa_data.h"
11#include "../ipa_endpoint.h"
12#include "../ipa_mem.h"
13#include "../ipa_version.h"
14
15/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */
16enum ipa_resource_type {
17 /* Source resource types; first must have value 0 */
18 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
19 IPA_RESOURCE_TYPE_SRC_HDR_SECTORS,
20 IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER,
21 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
22 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
23 IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS,
24 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
25 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
26
27 /* Destination resource types; first must have value 0 */
28 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
29 IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS,
30 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
31};
32
33/* Resource groups used for an SoC having IPA v3.1 */
34enum ipa_rsrc_group_id {
35 /* Source resource group identifiers */
36 IPA_RSRC_GROUP_SRC_UL = 0,
37 IPA_RSRC_GROUP_SRC_DL,
38 IPA_RSRC_GROUP_SRC_DIAG,
39 IPA_RSRC_GROUP_SRC_DMA,
40 IPA_RSRC_GROUP_SRC_UNUSED,
41 IPA_RSRC_GROUP_SRC_UC_RX_Q,
42 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
43
44 /* Destination resource group identifiers */
45 IPA_RSRC_GROUP_DST_UL = 0,
46 IPA_RSRC_GROUP_DST_DL,
47 IPA_RSRC_GROUP_DST_DIAG_DPL,
48 IPA_RSRC_GROUP_DST_DMA,
49 IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL,
50 IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE,
51 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
52};
53
54/* QSB configuration data for an SoC having IPA v3.1 */
55static const struct ipa_qsb_data ipa_qsb_data[] = {
56 [IPA_QSB_MASTER_DDR] = {
57 .max_writes = 8,
58 .max_reads = 8,
59 },
60 [IPA_QSB_MASTER_PCIE] = {
61 .max_writes = 2,
62 .max_reads = 8,
63 },
64};
65
66/* Endpoint data for an SoC having IPA v3.1 */
67static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
68 [IPA_ENDPOINT_AP_COMMAND_TX] = {
69 .ee_id = GSI_EE_AP,
70 .channel_id = 6,
71 .endpoint_id = 22,
72 .toward_ipa = true,
73 .channel = {
74 .tre_count = 256,
75 .event_count = 256,
76 .tlv_count = 18,
77 },
78 .endpoint = {
79 .config = {
80 .resource_group = IPA_RSRC_GROUP_SRC_UL,
81 .dma_mode = true,
82 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
83 .tx = {
84 .seq_type = IPA_SEQ_DMA,
85 },
86 },
87 },
88 },
89 [IPA_ENDPOINT_AP_LAN_RX] = {
90 .ee_id = GSI_EE_AP,
91 .channel_id = 7,
92 .endpoint_id = 15,
93 .toward_ipa = false,
94 .channel = {
95 .tre_count = 256,
96 .event_count = 256,
97 .tlv_count = 8,
98 },
99 .endpoint = {
100 .config = {
101 .resource_group = IPA_RSRC_GROUP_SRC_UL,
102 .aggregation = true,
103 .status_enable = true,
104 .rx = {
105 .buffer_size = 8192,
106 .pad_align = ilog2(sizeof(u32)),
107 .aggr_time_limit = 500,
108 },
109 },
110 },
111 },
112 [IPA_ENDPOINT_AP_MODEM_TX] = {
113 .ee_id = GSI_EE_AP,
114 .channel_id = 5,
115 .endpoint_id = 3,
116 .toward_ipa = true,
117 .channel = {
118 .tre_count = 512,
119 .event_count = 512,
120 .tlv_count = 16,
121 },
122 .endpoint = {
123 .filter_support = true,
124 .config = {
125 .resource_group = IPA_RSRC_GROUP_SRC_UL,
126 .checksum = true,
127 .qmap = true,
128 .status_enable = true,
129 .tx = {
130 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
131 .status_endpoint =
132 IPA_ENDPOINT_MODEM_AP_RX,
133 },
134 },
135 },
136 },
137 [IPA_ENDPOINT_AP_MODEM_RX] = {
138 .ee_id = GSI_EE_AP,
139 .channel_id = 8,
140 .endpoint_id = 16,
141 .toward_ipa = false,
142 .channel = {
143 .tre_count = 256,
144 .event_count = 256,
145 .tlv_count = 8,
146 },
147 .endpoint = {
148 .config = {
149 .resource_group = IPA_RSRC_GROUP_DST_DL,
150 .checksum = true,
151 .qmap = true,
152 .aggregation = true,
153 .rx = {
154 .buffer_size = 8192,
155 .aggr_time_limit = 500,
156 .aggr_close_eof = true,
157 },
158 },
159 },
160 },
161 [IPA_ENDPOINT_MODEM_LAN_TX] = {
162 .ee_id = GSI_EE_MODEM,
163 .channel_id = 4,
164 .endpoint_id = 9,
165 .toward_ipa = true,
166 .endpoint = {
167 .filter_support = true,
168 },
169 },
170 [IPA_ENDPOINT_MODEM_AP_TX] = {
171 .ee_id = GSI_EE_MODEM,
172 .channel_id = 0,
173 .endpoint_id = 5,
174 .toward_ipa = true,
175 .endpoint = {
176 .filter_support = true,
177 },
178 },
179 [IPA_ENDPOINT_MODEM_AP_RX] = {
180 .ee_id = GSI_EE_MODEM,
181 .channel_id = 5,
182 .endpoint_id = 18,
183 .toward_ipa = false,
184 },
185};
186
187/* Source resource configuration data for an SoC having IPA v3.1 */
188static const struct ipa_resource ipa_resource_src[] = {
189 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
190 .limits[IPA_RSRC_GROUP_SRC_UL] = {
191 .min = 3, .max = 255,
192 },
193 .limits[IPA_RSRC_GROUP_SRC_DL] = {
194 .min = 3, .max = 255,
195 },
196 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
197 .min = 1, .max = 255,
198 },
199 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
200 .min = 1, .max = 255,
201 },
202 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
203 .min = 2, .max = 255,
204 },
205 },
206 [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = {
207 .limits[IPA_RSRC_GROUP_SRC_UL] = {
208 .min = 0, .max = 255,
209 },
210 .limits[IPA_RSRC_GROUP_SRC_DL] = {
211 .min = 0, .max = 255,
212 },
213 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
214 .min = 0, .max = 255,
215 },
216 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
217 .min = 0, .max = 255,
218 },
219 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
220 .min = 0, .max = 255,
221 },
222 },
223 [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = {
224 .limits[IPA_RSRC_GROUP_SRC_UL] = {
225 .min = 0, .max = 255,
226 },
227 .limits[IPA_RSRC_GROUP_SRC_DL] = {
228 .min = 0, .max = 255,
229 },
230 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
231 .min = 0, .max = 255,
232 },
233 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
234 .min = 0, .max = 255,
235 },
236 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
237 .min = 0, .max = 255,
238 },
239 },
240 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
241 .limits[IPA_RSRC_GROUP_SRC_UL] = {
242 .min = 14, .max = 14,
243 },
244 .limits[IPA_RSRC_GROUP_SRC_DL] = {
245 .min = 16, .max = 16,
246 },
247 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
248 .min = 5, .max = 5,
249 },
250 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
251 .min = 5, .max = 5,
252 },
253 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
254 .min = 8, .max = 8,
255 },
256 },
257 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
258 .limits[IPA_RSRC_GROUP_SRC_UL] = {
259 .min = 19, .max = 19,
260 },
261 .limits[IPA_RSRC_GROUP_SRC_DL] = {
262 .min = 26, .max = 26,
263 },
264 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
265 .min = 5, .max = 5, /* 3 downstream */
266 },
267 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
268 .min = 5, .max = 5, /* 7 downstream */
269 },
270 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
271 .min = 8, .max = 8,
272 },
273 },
274 [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = {
275 .limits[IPA_RSRC_GROUP_SRC_UL] = {
276 .min = 0, .max = 255,
277 },
278 .limits[IPA_RSRC_GROUP_SRC_DL] = {
279 .min = 0, .max = 255,
280 },
281 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
282 .min = 0, .max = 255,
283 },
284 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
285 .min = 0, .max = 255,
286 },
287 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
288 .min = 0, .max = 255,
289 },
290 },
291 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
292 .limits[IPA_RSRC_GROUP_SRC_UL] = {
293 .min = 0, .max = 255,
294 },
295 .limits[IPA_RSRC_GROUP_SRC_DL] = {
296 .min = 0, .max = 255,
297 },
298 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
299 .min = 0, .max = 255,
300 },
301 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
302 .min = 0, .max = 255,
303 },
304 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
305 .min = 0, .max = 255,
306 },
307 },
308 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
309 .limits[IPA_RSRC_GROUP_SRC_UL] = {
310 .min = 19, .max = 19,
311 },
312 .limits[IPA_RSRC_GROUP_SRC_DL] = {
313 .min = 26, .max = 26,
314 },
315 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
316 .min = 5, .max = 5,
317 },
318 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
319 .min = 5, .max = 5,
320 },
321 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
322 .min = 8, .max = 8,
323 },
324 },
325};
326
327/* Destination resource configuration data for an SoC having IPA v3.1 */
328static const struct ipa_resource ipa_resource_dst[] = {
329 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
330 .limits[IPA_RSRC_GROUP_DST_UL] = {
331 .min = 3, .max = 3, /* 2 downstream */
332 },
333 .limits[IPA_RSRC_GROUP_DST_DL] = {
334 .min = 3, .max = 3,
335 },
336 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
337 .min = 1, .max = 1, /* 0 downstream */
338 },
339 /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */
340 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
341 .min = 3, .max = 3,
342 },
343 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
344 .min = 3, .max = 3,
345 },
346 },
347 [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = {
348 .limits[IPA_RSRC_GROUP_DST_UL] = {
349 .min = 0, .max = 255,
350 },
351 .limits[IPA_RSRC_GROUP_DST_DL] = {
352 .min = 0, .max = 255,
353 },
354 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
355 .min = 0, .max = 255,
356 },
357 .limits[IPA_RSRC_GROUP_DST_DMA] = {
358 .min = 0, .max = 255,
359 },
360 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
361 .min = 0, .max = 255,
362 },
363 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
364 .min = 0, .max = 255,
365 },
366 },
367 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
368 .limits[IPA_RSRC_GROUP_DST_UL] = {
369 .min = 1, .max = 1,
370 },
371 .limits[IPA_RSRC_GROUP_DST_DL] = {
372 .min = 1, .max = 1,
373 },
374 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
375 .min = 1, .max = 1,
376 },
377 .limits[IPA_RSRC_GROUP_DST_DMA] = {
378 .min = 1, .max = 1,
379 },
380 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
381 .min = 1, .max = 1,
382 },
383 },
384};
385
386/* Resource configuration data for an SoC having IPA v3.1 */
387static const struct ipa_resource_data ipa_resource_data = {
388 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
389 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
390 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
391 .resource_src = ipa_resource_src,
392 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
393 .resource_dst = ipa_resource_dst,
394};
395
396/* IPA-resident memory region data for an SoC having IPA v3.1 */
397static const struct ipa_mem ipa_mem_local_data[] = {
398 {
399 .id = IPA_MEM_UC_SHARED,
400 .offset = 0x0000,
401 .size = 0x0080,
402 .canary_count = 0,
403 },
404 {
405 .id = IPA_MEM_UC_INFO,
406 .offset = 0x0080,
407 .size = 0x0200,
408 .canary_count = 0,
409 },
410 {
411 .id = IPA_MEM_V4_FILTER_HASHED,
412 .offset = 0x0288,
413 .size = 0x0078,
414 .canary_count = 2,
415 },
416 {
417 .id = IPA_MEM_V4_FILTER,
418 .offset = 0x0308,
419 .size = 0x0078,
420 .canary_count = 2,
421 },
422 {
423 .id = IPA_MEM_V6_FILTER_HASHED,
424 .offset = 0x0388,
425 .size = 0x0078,
426 .canary_count = 2,
427 },
428 {
429 .id = IPA_MEM_V6_FILTER,
430 .offset = 0x0408,
431 .size = 0x0078,
432 .canary_count = 2,
433 },
434 {
435 .id = IPA_MEM_V4_ROUTE_HASHED,
436 .offset = 0x0488,
437 .size = 0x0078,
438 .canary_count = 2,
439 },
440 {
441 .id = IPA_MEM_V4_ROUTE,
442 .offset = 0x0508,
443 .size = 0x0078,
444 .canary_count = 2,
445 },
446 {
447 .id = IPA_MEM_V6_ROUTE_HASHED,
448 .offset = 0x0588,
449 .size = 0x0078,
450 .canary_count = 2,
451 },
452 {
453 .id = IPA_MEM_V6_ROUTE,
454 .offset = 0x0608,
455 .size = 0x0078,
456 .canary_count = 2,
457 },
458 {
459 .id = IPA_MEM_MODEM_HEADER,
460 .offset = 0x0688,
461 .size = 0x0140,
462 .canary_count = 2,
463 },
464 {
465 .id = IPA_MEM_MODEM_PROC_CTX,
466 .offset = 0x07d0,
467 .size = 0x0200,
468 .canary_count = 2,
469 },
470 {
471 .id = IPA_MEM_AP_PROC_CTX,
472 .offset = 0x09d0,
473 .size = 0x0200,
474 .canary_count = 0,
475 },
476 {
477 .id = IPA_MEM_MODEM,
478 .offset = 0x0bd8,
479 .size = 0x1424,
480 .canary_count = 0,
481 },
482 {
483 .id = IPA_MEM_END_MARKER,
484 .offset = 0x2000,
485 .size = 0,
486 .canary_count = 1,
487 },
488};
489
490/* Memory configuration data for an SoC having IPA v3.1 */
491static const struct ipa_mem_data ipa_mem_data = {
492 .local_count = ARRAY_SIZE(ipa_mem_local_data),
493 .local = ipa_mem_local_data,
494 .imem_addr = 0x146bd000,
495 .imem_size = 0x00002000,
496 .smem_size = 0x00002000,
497};
498
499/* Interconnect bandwidths are in 1000 byte/second units */
500static const struct ipa_interconnect_data ipa_interconnect_data[] = {
501 {
502 .name = "memory",
503 .peak_bandwidth = 640000, /* 640 MBps */
504 .average_bandwidth = 80000, /* 80 MBps */
505 },
506 {
507 .name = "imem",
508 .peak_bandwidth = 640000, /* 640 MBps */
509 .average_bandwidth = 80000, /* 80 MBps */
510 },
511 /* Average bandwidth is unused for the next interconnect */
512 {
513 .name = "config",
514 .peak_bandwidth = 80000, /* 80 MBps */
515 .average_bandwidth = 0, /* unused */
516 },
517};
518
519/* Clock and interconnect configuration data for an SoC having IPA v3.1 */
520static const struct ipa_power_data ipa_power_data = {
521 .core_clock_rate = 16 * 1000 * 1000, /* Hz */
522 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
523 .interconnect_data = ipa_interconnect_data,
524};
525
526/* Configuration data for an SoC having IPA v3.1 */
527const struct ipa_data ipa_data_v3_1 = {
528 .version = IPA_VERSION_3_1,
529 .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY),
530 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
531 .qsb_data = ipa_qsb_data,
532 .modem_route_count = 8,
533 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
534 .endpoint_data = ipa_gsi_endpoint_data,
535 .resource_data = &ipa_resource_data,
536 .mem_data = &ipa_mem_data,
537 .power_data = &ipa_power_data,
538};