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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Analog Devices Industrial Ethernet PHYs
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/bitfield.h>
9#include <linux/delay.h>
10#include <linux/errno.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/mii.h>
15#include <linux/phy.h>
16#include <linux/property.h>
17
18#define PHY_ID_ADIN1200 0x0283bc20
19#define PHY_ID_ADIN1300 0x0283bc30
20
21#define ADIN1300_MII_EXT_REG_PTR 0x0010
22#define ADIN1300_MII_EXT_REG_DATA 0x0011
23
24#define ADIN1300_PHY_CTRL1 0x0012
25#define ADIN1300_AUTO_MDI_EN BIT(10)
26#define ADIN1300_MAN_MDIX_EN BIT(9)
27#define ADIN1300_DIAG_CLK_EN BIT(2)
28
29#define ADIN1300_RX_ERR_CNT 0x0014
30
31#define ADIN1300_PHY_CTRL_STATUS2 0x0015
32#define ADIN1300_NRG_PD_EN BIT(3)
33#define ADIN1300_NRG_PD_TX_EN BIT(2)
34#define ADIN1300_NRG_PD_STATUS BIT(1)
35
36#define ADIN1300_PHY_CTRL2 0x0016
37#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
38#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
39#define ADIN1300_GROUP_MDIO_EN BIT(6)
40#define ADIN1300_DOWNSPEEDS_EN \
41 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
42
43#define ADIN1300_PHY_CTRL3 0x0017
44#define ADIN1300_LINKING_EN BIT(13)
45#define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
46
47#define ADIN1300_INT_MASK_REG 0x0018
48#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
49#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
50#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
51#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
52#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
53#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
54#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
55#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
56#define ADIN1300_INT_HW_IRQ_EN BIT(0)
57#define ADIN1300_INT_MASK_EN \
58 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
59#define ADIN1300_INT_STATUS_REG 0x0019
60
61#define ADIN1300_PHY_STATUS1 0x001a
62#define ADIN1300_PAIR_01_SWAP BIT(11)
63
64/* EEE register addresses, accessible via Clause 22 access using
65 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
66 * The bit-fields are the same as specified by IEEE for EEE.
67 */
68#define ADIN1300_EEE_CAP_REG 0x8000
69#define ADIN1300_EEE_ADV_REG 0x8001
70#define ADIN1300_EEE_LPABLE_REG 0x8002
71
72#define ADIN1300_FLD_EN_REG 0x8E27
73#define ADIN1300_FLD_PCS_ERR_100_EN BIT(7)
74#define ADIN1300_FLD_PCS_ERR_1000_EN BIT(6)
75#define ADIN1300_FLD_SLCR_OUT_STUCK_100_EN BIT(5)
76#define ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN BIT(4)
77#define ADIN1300_FLD_SLCR_IN_ZDET_100_EN BIT(3)
78#define ADIN1300_FLD_SLCR_IN_ZDET_1000_EN BIT(2)
79#define ADIN1300_FLD_SLCR_IN_INVLD_100_EN BIT(1)
80#define ADIN1300_FLD_SLCR_IN_INVLD_1000_EN BIT(0)
81/* These bits are the ones which are enabled by default. */
82#define ADIN1300_FLD_EN_ON \
83 (ADIN1300_FLD_SLCR_OUT_STUCK_100_EN | \
84 ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN | \
85 ADIN1300_FLD_SLCR_IN_ZDET_100_EN | \
86 ADIN1300_FLD_SLCR_IN_ZDET_1000_EN | \
87 ADIN1300_FLD_SLCR_IN_INVLD_1000_EN)
88
89#define ADIN1300_CLOCK_STOP_REG 0x9400
90#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
91
92#define ADIN1300_B_100_ZPTM_DIMRX 0xB685
93#define ADIN1300_B_100_ZPTM_EN_DIMRX BIT(0)
94
95#define ADIN1300_CDIAG_RUN 0xba1b
96#define ADIN1300_CDIAG_RUN_EN BIT(0)
97
98/*
99 * The XSIM3/2/1 and XSHRT3/2/1 are actually relative.
100 * For CDIAG_DTLD_RSLTS(0) it's ADIN1300_CDIAG_RSLT_XSIM3/2/1
101 * For CDIAG_DTLD_RSLTS(1) it's ADIN1300_CDIAG_RSLT_XSIM3/2/0
102 * For CDIAG_DTLD_RSLTS(2) it's ADIN1300_CDIAG_RSLT_XSIM3/1/0
103 * For CDIAG_DTLD_RSLTS(3) it's ADIN1300_CDIAG_RSLT_XSIM2/1/0
104 */
105#define ADIN1300_CDIAG_DTLD_RSLTS(x) (0xba1d + (x))
106#define ADIN1300_CDIAG_RSLT_BUSY BIT(10)
107#define ADIN1300_CDIAG_RSLT_XSIM3 BIT(9)
108#define ADIN1300_CDIAG_RSLT_XSIM2 BIT(8)
109#define ADIN1300_CDIAG_RSLT_XSIM1 BIT(7)
110#define ADIN1300_CDIAG_RSLT_SIM BIT(6)
111#define ADIN1300_CDIAG_RSLT_XSHRT3 BIT(5)
112#define ADIN1300_CDIAG_RSLT_XSHRT2 BIT(4)
113#define ADIN1300_CDIAG_RSLT_XSHRT1 BIT(3)
114#define ADIN1300_CDIAG_RSLT_SHRT BIT(2)
115#define ADIN1300_CDIAG_RSLT_OPEN BIT(1)
116#define ADIN1300_CDIAG_RSLT_GOOD BIT(0)
117
118#define ADIN1300_CDIAG_FLT_DIST(x) (0xba21 + (x))
119
120#define ADIN1300_GE_SOFT_RESET_REG 0xff0c
121#define ADIN1300_GE_SOFT_RESET BIT(0)
122
123#define ADIN1300_GE_CLK_CFG_REG 0xff1f
124#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)
125#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5)
126#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4)
127#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3)
128#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2)
129#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1)
130#define ADIN1300_GE_CLK_CFG_25 BIT(0)
131
132#define ADIN1300_GE_RGMII_CFG_REG 0xff23
133#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
134#define ADIN1300_GE_RGMII_RX_SEL(x) \
135 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
136#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
137#define ADIN1300_GE_RGMII_GTX_SEL(x) \
138 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
139#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
140#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
141#define ADIN1300_GE_RGMII_EN BIT(0)
142
143/* RGMII internal delay settings for rx and tx for ADIN1300 */
144#define ADIN1300_RGMII_1_60_NS 0x0001
145#define ADIN1300_RGMII_1_80_NS 0x0002
146#define ADIN1300_RGMII_2_00_NS 0x0000
147#define ADIN1300_RGMII_2_20_NS 0x0006
148#define ADIN1300_RGMII_2_40_NS 0x0007
149
150#define ADIN1300_GE_RMII_CFG_REG 0xff24
151#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
152#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
153 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
154#define ADIN1300_GE_RMII_EN BIT(0)
155
156/* RMII fifo depth values */
157#define ADIN1300_RMII_4_BITS 0x0000
158#define ADIN1300_RMII_8_BITS 0x0001
159#define ADIN1300_RMII_12_BITS 0x0002
160#define ADIN1300_RMII_16_BITS 0x0003
161#define ADIN1300_RMII_20_BITS 0x0004
162#define ADIN1300_RMII_24_BITS 0x0005
163
164/**
165 * struct adin_cfg_reg_map - map a config value to aregister value
166 * @cfg: value in device configuration
167 * @reg: value in the register
168 */
169struct adin_cfg_reg_map {
170 int cfg;
171 int reg;
172};
173
174static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
175 { 1600, ADIN1300_RGMII_1_60_NS },
176 { 1800, ADIN1300_RGMII_1_80_NS },
177 { 2000, ADIN1300_RGMII_2_00_NS },
178 { 2200, ADIN1300_RGMII_2_20_NS },
179 { 2400, ADIN1300_RGMII_2_40_NS },
180 { },
181};
182
183static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
184 { 4, ADIN1300_RMII_4_BITS },
185 { 8, ADIN1300_RMII_8_BITS },
186 { 12, ADIN1300_RMII_12_BITS },
187 { 16, ADIN1300_RMII_16_BITS },
188 { 20, ADIN1300_RMII_20_BITS },
189 { 24, ADIN1300_RMII_24_BITS },
190 { },
191};
192
193/**
194 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
195 * @devad: device address used in Clause 45 access
196 * @cl45_regnum: register address defined by Clause 45
197 * @adin_regnum: equivalent register address accessible via Clause 22
198 */
199struct adin_clause45_mmd_map {
200 int devad;
201 u16 cl45_regnum;
202 u16 adin_regnum;
203};
204
205static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
206 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
207 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
208 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
209 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
210 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
211};
212
213struct adin_hw_stat {
214 const char *string;
215 u16 reg1;
216 u16 reg2;
217};
218
219static const struct adin_hw_stat adin_hw_stats[] = {
220 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
221 { "length_error_frames_count", 0x940C },
222 { "alignment_error_frames_count", 0x940D },
223 { "symbol_error_count", 0x940E },
224 { "oversized_frames_count", 0x940F },
225 { "undersized_frames_count", 0x9410 },
226 { "odd_nibble_frames_count", 0x9411 },
227 { "odd_preamble_packet_count", 0x9412 },
228 { "dribble_bits_frames_count", 0x9413 },
229 { "false_carrier_events_count", 0x9414 },
230};
231
232/**
233 * struct adin_priv - ADIN PHY driver private data
234 * @stats: statistic counters for the PHY
235 */
236struct adin_priv {
237 u64 stats[ARRAY_SIZE(adin_hw_stats)];
238};
239
240static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
241{
242 size_t i;
243
244 for (i = 0; tbl[i].cfg; i++) {
245 if (tbl[i].cfg == cfg)
246 return tbl[i].reg;
247 }
248
249 return -EINVAL;
250}
251
252static u32 adin_get_reg_value(struct phy_device *phydev,
253 const char *prop_name,
254 const struct adin_cfg_reg_map *tbl,
255 u32 dflt)
256{
257 struct device *dev = &phydev->mdio.dev;
258 u32 val;
259 int rc;
260
261 if (device_property_read_u32(dev, prop_name, &val))
262 return dflt;
263
264 rc = adin_lookup_reg_value(tbl, val);
265 if (rc < 0) {
266 phydev_warn(phydev,
267 "Unsupported value %u for %s using default (%u)\n",
268 val, prop_name, dflt);
269 return dflt;
270 }
271
272 return rc;
273}
274
275static int adin_config_rgmii_mode(struct phy_device *phydev)
276{
277 u32 val;
278 int reg;
279
280 if (!phy_interface_is_rgmii(phydev))
281 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
282 ADIN1300_GE_RGMII_CFG_REG,
283 ADIN1300_GE_RGMII_EN);
284
285 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
286 if (reg < 0)
287 return reg;
288
289 reg |= ADIN1300_GE_RGMII_EN;
290
291 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
292 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
293 reg |= ADIN1300_GE_RGMII_RXID_EN;
294
295 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
296 adin_rgmii_delays,
297 ADIN1300_RGMII_2_00_NS);
298 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
299 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
300 } else {
301 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
302 }
303
304 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
305 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
306 reg |= ADIN1300_GE_RGMII_TXID_EN;
307
308 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
309 adin_rgmii_delays,
310 ADIN1300_RGMII_2_00_NS);
311 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
312 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
313 } else {
314 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
315 }
316
317 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
318 ADIN1300_GE_RGMII_CFG_REG, reg);
319}
320
321static int adin_config_rmii_mode(struct phy_device *phydev)
322{
323 u32 val;
324 int reg;
325
326 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
327 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
328 ADIN1300_GE_RMII_CFG_REG,
329 ADIN1300_GE_RMII_EN);
330
331 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
332 if (reg < 0)
333 return reg;
334
335 reg |= ADIN1300_GE_RMII_EN;
336
337 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
338 adin_rmii_fifo_depths,
339 ADIN1300_RMII_8_BITS);
340
341 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
342 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
343
344 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
345 ADIN1300_GE_RMII_CFG_REG, reg);
346}
347
348static int adin_get_downshift(struct phy_device *phydev, u8 *data)
349{
350 int val, cnt, enable;
351
352 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
353 if (val < 0)
354 return val;
355
356 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
357 if (cnt < 0)
358 return cnt;
359
360 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
361 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
362
363 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
364
365 return 0;
366}
367
368static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
369{
370 u16 val;
371 int rc;
372
373 if (cnt == DOWNSHIFT_DEV_DISABLE)
374 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
375 ADIN1300_DOWNSPEEDS_EN);
376
377 if (cnt > 7)
378 return -E2BIG;
379
380 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
381
382 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
383 ADIN1300_DOWNSPEED_RETRIES_MSK,
384 val);
385 if (rc < 0)
386 return rc;
387
388 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
389 ADIN1300_DOWNSPEEDS_EN);
390}
391
392static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
393{
394 int val;
395
396 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
397 if (val < 0)
398 return val;
399
400 if (ADIN1300_NRG_PD_EN & val) {
401 if (val & ADIN1300_NRG_PD_TX_EN)
402 /* default is 1 second */
403 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
404 else
405 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
406 } else {
407 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
408 }
409
410 return 0;
411}
412
413static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
414{
415 u16 val;
416
417 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
418 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
419 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
420
421 val = ADIN1300_NRG_PD_EN;
422
423 switch (tx_interval) {
424 case 1000: /* 1 second */
425 fallthrough;
426 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
427 val |= ADIN1300_NRG_PD_TX_EN;
428 fallthrough;
429 case ETHTOOL_PHY_EDPD_NO_TX:
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
436 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
437 val);
438}
439
440static int adin_get_fast_down(struct phy_device *phydev, u8 *msecs)
441{
442 int reg;
443
444 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);
445 if (reg < 0)
446 return reg;
447
448 if (reg & ADIN1300_FLD_EN_ON)
449 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_ON;
450 else
451 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
452
453 return 0;
454}
455
456static int adin_set_fast_down(struct phy_device *phydev, const u8 *msecs)
457{
458 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_ON)
459 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
460 ADIN1300_FLD_EN_REG,
461 ADIN1300_FLD_EN_ON);
462
463 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
464 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
465 ADIN1300_FLD_EN_REG,
466 ADIN1300_FLD_EN_ON);
467
468 return -EINVAL;
469}
470
471static int adin_get_tunable(struct phy_device *phydev,
472 struct ethtool_tunable *tuna, void *data)
473{
474 switch (tuna->id) {
475 case ETHTOOL_PHY_DOWNSHIFT:
476 return adin_get_downshift(phydev, data);
477 case ETHTOOL_PHY_EDPD:
478 return adin_get_edpd(phydev, data);
479 case ETHTOOL_PHY_FAST_LINK_DOWN:
480 return adin_get_fast_down(phydev, data);
481 default:
482 return -EOPNOTSUPP;
483 }
484}
485
486static int adin_set_tunable(struct phy_device *phydev,
487 struct ethtool_tunable *tuna, const void *data)
488{
489 switch (tuna->id) {
490 case ETHTOOL_PHY_DOWNSHIFT:
491 return adin_set_downshift(phydev, *(const u8 *)data);
492 case ETHTOOL_PHY_EDPD:
493 return adin_set_edpd(phydev, *(const u16 *)data);
494 case ETHTOOL_PHY_FAST_LINK_DOWN:
495 return adin_set_fast_down(phydev, data);
496 default:
497 return -EOPNOTSUPP;
498 }
499}
500
501static int adin_config_clk_out(struct phy_device *phydev)
502{
503 struct device *dev = &phydev->mdio.dev;
504 const char *val = NULL;
505 u8 sel = 0;
506
507 device_property_read_string(dev, "adi,phy-output-clock", &val);
508 if (!val) {
509 /* property not present, do not enable GP_CLK pin */
510 } else if (strcmp(val, "25mhz-reference") == 0) {
511 sel |= ADIN1300_GE_CLK_CFG_25;
512 } else if (strcmp(val, "125mhz-free-running") == 0) {
513 sel |= ADIN1300_GE_CLK_CFG_FREE_125;
514 } else if (strcmp(val, "adaptive-free-running") == 0) {
515 sel |= ADIN1300_GE_CLK_CFG_HRT_FREE;
516 } else {
517 phydev_err(phydev, "invalid adi,phy-output-clock\n");
518 return -EINVAL;
519 }
520
521 if (device_property_read_bool(dev, "adi,phy-output-reference-clock"))
522 sel |= ADIN1300_GE_CLK_CFG_REF_EN;
523
524 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
525 ADIN1300_GE_CLK_CFG_MASK, sel);
526}
527
528static int adin_config_zptm100(struct phy_device *phydev)
529{
530 struct device *dev = &phydev->mdio.dev;
531
532 if (!(device_property_read_bool(dev, "adi,low-cmode-impedance")))
533 return 0;
534
535 /* clear bit 0 to configure for lowest common-mode impedance */
536 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
537 ADIN1300_B_100_ZPTM_DIMRX,
538 ADIN1300_B_100_ZPTM_EN_DIMRX);
539}
540
541static int adin_config_init(struct phy_device *phydev)
542{
543 int rc;
544
545 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
546
547 rc = adin_config_rgmii_mode(phydev);
548 if (rc < 0)
549 return rc;
550
551 rc = adin_config_rmii_mode(phydev);
552 if (rc < 0)
553 return rc;
554
555 rc = adin_set_downshift(phydev, 4);
556 if (rc < 0)
557 return rc;
558
559 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
560 if (rc < 0)
561 return rc;
562
563 rc = adin_config_clk_out(phydev);
564 if (rc < 0)
565 return rc;
566
567 rc = adin_config_zptm100(phydev);
568 if (rc < 0)
569 return rc;
570
571 phydev_dbg(phydev, "PHY is using mode '%s'\n",
572 phy_modes(phydev->interface));
573
574 return 0;
575}
576
577static int adin_phy_ack_intr(struct phy_device *phydev)
578{
579 /* Clear pending interrupts */
580 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
581
582 return rc < 0 ? rc : 0;
583}
584
585static int adin_phy_config_intr(struct phy_device *phydev)
586{
587 int err;
588
589 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
590 err = adin_phy_ack_intr(phydev);
591 if (err)
592 return err;
593
594 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
595 ADIN1300_INT_MASK_EN);
596 } else {
597 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
598 ADIN1300_INT_MASK_EN);
599 if (err)
600 return err;
601
602 err = adin_phy_ack_intr(phydev);
603 }
604
605 return err;
606}
607
608static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
609{
610 int irq_status;
611
612 irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG);
613 if (irq_status < 0) {
614 phy_error(phydev);
615 return IRQ_NONE;
616 }
617
618 if (!(irq_status & ADIN1300_INT_LINK_STAT_CHNG_EN))
619 return IRQ_NONE;
620
621 phy_trigger_machine(phydev);
622
623 return IRQ_HANDLED;
624}
625
626static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
627 u16 cl45_regnum)
628{
629 const struct adin_clause45_mmd_map *m;
630 int i;
631
632 if (devad == MDIO_MMD_VEND1)
633 return cl45_regnum;
634
635 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
636 m = &adin_clause45_mmd_map[i];
637 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
638 return m->adin_regnum;
639 }
640
641 phydev_err(phydev,
642 "No translation available for devad: %d reg: %04x\n",
643 devad, cl45_regnum);
644
645 return -EINVAL;
646}
647
648static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
649{
650 struct mii_bus *bus = phydev->mdio.bus;
651 int phy_addr = phydev->mdio.addr;
652 int adin_regnum;
653 int err;
654
655 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
656 if (adin_regnum < 0)
657 return adin_regnum;
658
659 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
660 adin_regnum);
661 if (err)
662 return err;
663
664 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
665}
666
667static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
668 u16 val)
669{
670 struct mii_bus *bus = phydev->mdio.bus;
671 int phy_addr = phydev->mdio.addr;
672 int adin_regnum;
673 int err;
674
675 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
676 if (adin_regnum < 0)
677 return adin_regnum;
678
679 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
680 adin_regnum);
681 if (err)
682 return err;
683
684 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
685}
686
687static int adin_config_mdix(struct phy_device *phydev)
688{
689 bool auto_en, mdix_en;
690 int reg;
691
692 mdix_en = false;
693 auto_en = false;
694 switch (phydev->mdix_ctrl) {
695 case ETH_TP_MDI:
696 break;
697 case ETH_TP_MDI_X:
698 mdix_en = true;
699 break;
700 case ETH_TP_MDI_AUTO:
701 auto_en = true;
702 break;
703 default:
704 return -EINVAL;
705 }
706
707 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
708 if (reg < 0)
709 return reg;
710
711 if (mdix_en)
712 reg |= ADIN1300_MAN_MDIX_EN;
713 else
714 reg &= ~ADIN1300_MAN_MDIX_EN;
715
716 if (auto_en)
717 reg |= ADIN1300_AUTO_MDI_EN;
718 else
719 reg &= ~ADIN1300_AUTO_MDI_EN;
720
721 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
722}
723
724static int adin_config_aneg(struct phy_device *phydev)
725{
726 int ret;
727
728 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
729 if (ret < 0)
730 return ret;
731
732 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
733 if (ret < 0)
734 return ret;
735
736 ret = adin_config_mdix(phydev);
737 if (ret)
738 return ret;
739
740 return genphy_config_aneg(phydev);
741}
742
743static int adin_mdix_update(struct phy_device *phydev)
744{
745 bool auto_en, mdix_en;
746 bool swapped;
747 int reg;
748
749 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
750 if (reg < 0)
751 return reg;
752
753 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
754 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
755
756 /* If MDI/MDIX is forced, just read it from the control reg */
757 if (!auto_en) {
758 if (mdix_en)
759 phydev->mdix = ETH_TP_MDI_X;
760 else
761 phydev->mdix = ETH_TP_MDI;
762 return 0;
763 }
764
765 /**
766 * Otherwise, we need to deduce it from the PHY status2 reg.
767 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
768 * a preference for MDIX when it is set.
769 */
770 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
771 if (reg < 0)
772 return reg;
773
774 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
775
776 if (mdix_en != swapped)
777 phydev->mdix = ETH_TP_MDI_X;
778 else
779 phydev->mdix = ETH_TP_MDI;
780
781 return 0;
782}
783
784static int adin_read_status(struct phy_device *phydev)
785{
786 int ret;
787
788 ret = adin_mdix_update(phydev);
789 if (ret < 0)
790 return ret;
791
792 return genphy_read_status(phydev);
793}
794
795static int adin_soft_reset(struct phy_device *phydev)
796{
797 int rc;
798
799 /* The reset bit is self-clearing, set it and wait */
800 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
801 ADIN1300_GE_SOFT_RESET_REG,
802 ADIN1300_GE_SOFT_RESET);
803 if (rc < 0)
804 return rc;
805
806 msleep(20);
807
808 /* If we get a read error something may be wrong */
809 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
810 ADIN1300_GE_SOFT_RESET_REG);
811
812 return rc < 0 ? rc : 0;
813}
814
815static int adin_get_sset_count(struct phy_device *phydev)
816{
817 return ARRAY_SIZE(adin_hw_stats);
818}
819
820static void adin_get_strings(struct phy_device *phydev, u8 *data)
821{
822 int i;
823
824 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
825 ethtool_puts(&data, adin_hw_stats[i].string);
826}
827
828static int adin_read_mmd_stat_regs(struct phy_device *phydev,
829 const struct adin_hw_stat *stat,
830 u32 *val)
831{
832 int ret;
833
834 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
835 if (ret < 0)
836 return ret;
837
838 *val = (ret & 0xffff);
839
840 if (stat->reg2 == 0)
841 return 0;
842
843 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
844 if (ret < 0)
845 return ret;
846
847 *val <<= 16;
848 *val |= (ret & 0xffff);
849
850 return 0;
851}
852
853static u64 adin_get_stat(struct phy_device *phydev, int i)
854{
855 const struct adin_hw_stat *stat = &adin_hw_stats[i];
856 struct adin_priv *priv = phydev->priv;
857 u32 val;
858 int ret;
859
860 if (stat->reg1 > 0x1f) {
861 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
862 if (ret < 0)
863 return (u64)(~0);
864 } else {
865 ret = phy_read(phydev, stat->reg1);
866 if (ret < 0)
867 return (u64)(~0);
868 val = (ret & 0xffff);
869 }
870
871 priv->stats[i] += val;
872
873 return priv->stats[i];
874}
875
876static void adin_get_stats(struct phy_device *phydev,
877 struct ethtool_stats *stats, u64 *data)
878{
879 int i, rc;
880
881 /* latch copies of all the frame-checker counters */
882 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
883 if (rc < 0)
884 return;
885
886 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
887 data[i] = adin_get_stat(phydev, i);
888}
889
890static int adin_probe(struct phy_device *phydev)
891{
892 struct device *dev = &phydev->mdio.dev;
893 struct adin_priv *priv;
894
895 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
896 if (!priv)
897 return -ENOMEM;
898
899 phydev->priv = priv;
900
901 return 0;
902}
903
904static int adin_cable_test_start(struct phy_device *phydev)
905{
906 int ret;
907
908 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
909 if (ret < 0)
910 return ret;
911
912 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
913 if (ret < 0)
914 return ret;
915
916 /* wait a bit for the clock to stabilize */
917 msleep(50);
918
919 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
920 ADIN1300_CDIAG_RUN_EN);
921}
922
923static int adin_cable_test_report_trans(int result)
924{
925 int mask;
926
927 if (result & ADIN1300_CDIAG_RSLT_GOOD)
928 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
929 if (result & ADIN1300_CDIAG_RSLT_OPEN)
930 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
931
932 /* short with other pairs */
933 mask = ADIN1300_CDIAG_RSLT_XSHRT3 |
934 ADIN1300_CDIAG_RSLT_XSHRT2 |
935 ADIN1300_CDIAG_RSLT_XSHRT1;
936 if (result & mask)
937 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
938
939 if (result & ADIN1300_CDIAG_RSLT_SHRT)
940 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
941
942 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
943}
944
945static int adin_cable_test_report_pair(struct phy_device *phydev,
946 unsigned int pair)
947{
948 int fault_rslt;
949 int ret;
950
951 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
952 ADIN1300_CDIAG_DTLD_RSLTS(pair));
953 if (ret < 0)
954 return ret;
955
956 fault_rslt = adin_cable_test_report_trans(ret);
957
958 ret = ethnl_cable_test_result(phydev, pair, fault_rslt);
959 if (ret < 0)
960 return ret;
961
962 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
963 ADIN1300_CDIAG_FLT_DIST(pair));
964 if (ret < 0)
965 return ret;
966
967 switch (fault_rslt) {
968 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
969 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
970 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
971 return ethnl_cable_test_fault_length(phydev, pair, ret * 100);
972 default:
973 return 0;
974 }
975}
976
977static int adin_cable_test_report(struct phy_device *phydev)
978{
979 unsigned int pair;
980 int ret;
981
982 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) {
983 ret = adin_cable_test_report_pair(phydev, pair);
984 if (ret < 0)
985 return ret;
986 }
987
988 return 0;
989}
990
991static int adin_cable_test_get_status(struct phy_device *phydev,
992 bool *finished)
993{
994 int ret;
995
996 *finished = false;
997
998 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN);
999 if (ret < 0)
1000 return ret;
1001
1002 if (ret & ADIN1300_CDIAG_RUN_EN)
1003 return 0;
1004
1005 *finished = true;
1006
1007 return adin_cable_test_report(phydev);
1008}
1009
1010static struct phy_driver adin_driver[] = {
1011 {
1012 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
1013 .name = "ADIN1200",
1014 .flags = PHY_POLL_CABLE_TEST,
1015 .probe = adin_probe,
1016 .config_init = adin_config_init,
1017 .soft_reset = adin_soft_reset,
1018 .config_aneg = adin_config_aneg,
1019 .read_status = adin_read_status,
1020 .get_tunable = adin_get_tunable,
1021 .set_tunable = adin_set_tunable,
1022 .config_intr = adin_phy_config_intr,
1023 .handle_interrupt = adin_phy_handle_interrupt,
1024 .get_sset_count = adin_get_sset_count,
1025 .get_strings = adin_get_strings,
1026 .get_stats = adin_get_stats,
1027 .resume = genphy_resume,
1028 .suspend = genphy_suspend,
1029 .read_mmd = adin_read_mmd,
1030 .write_mmd = adin_write_mmd,
1031 .cable_test_start = adin_cable_test_start,
1032 .cable_test_get_status = adin_cable_test_get_status,
1033 },
1034 {
1035 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
1036 .name = "ADIN1300",
1037 .flags = PHY_POLL_CABLE_TEST,
1038 .probe = adin_probe,
1039 .config_init = adin_config_init,
1040 .soft_reset = adin_soft_reset,
1041 .config_aneg = adin_config_aneg,
1042 .read_status = adin_read_status,
1043 .get_tunable = adin_get_tunable,
1044 .set_tunable = adin_set_tunable,
1045 .config_intr = adin_phy_config_intr,
1046 .handle_interrupt = adin_phy_handle_interrupt,
1047 .get_sset_count = adin_get_sset_count,
1048 .get_strings = adin_get_strings,
1049 .get_stats = adin_get_stats,
1050 .resume = genphy_resume,
1051 .suspend = genphy_suspend,
1052 .read_mmd = adin_read_mmd,
1053 .write_mmd = adin_write_mmd,
1054 .cable_test_start = adin_cable_test_start,
1055 .cable_test_get_status = adin_cable_test_get_status,
1056 },
1057};
1058
1059module_phy_driver(adin_driver);
1060
1061static const struct mdio_device_id __maybe_unused adin_tbl[] = {
1062 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
1063 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
1064 { }
1065};
1066
1067MODULE_DEVICE_TABLE(mdio, adin_tbl);
1068MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
1069MODULE_LICENSE("GPL");