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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015 Microchip Technology
4 */
5#include <linux/bitfield.h>
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/mii.h>
9#include <linux/ethtool.h>
10#include <linux/phy.h>
11#include <linux/microchipphy.h>
12#include <linux/delay.h>
13#include <linux/of.h>
14#include <dt-bindings/net/microchip-lan78xx.h>
15
16#define PHY_ID_LAN937X_TX 0x0007c190
17
18#define LAN937X_MODE_CTRL_STATUS_REG 0x11
19#define LAN937X_AUTOMDIX_EN BIT(7)
20#define LAN937X_MDI_MODE BIT(6)
21
22#define DRIVER_AUTHOR "WOOJUNG HUH <[email protected]>"
23#define DRIVER_DESC "Microchip LAN88XX/LAN937X TX PHY driver"
24
25struct lan88xx_priv {
26 int chip_id;
27 int chip_rev;
28 __u32 wolopts;
29 u8 downshift_cnt;
30};
31
32static int lan88xx_read_page(struct phy_device *phydev)
33{
34 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
35}
36
37static int lan88xx_write_page(struct phy_device *phydev, int page)
38{
39 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
40}
41
42static int lan88xx_suspend(struct phy_device *phydev)
43{
44 struct lan88xx_priv *priv = phydev->priv;
45
46 /* do not power down PHY when WOL is enabled */
47 if (!priv->wolopts)
48 genphy_suspend(phydev);
49
50 return 0;
51}
52
53static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
54 u32 data)
55{
56 int val, save_page, ret = 0;
57 u16 buf;
58
59 /* Save current page */
60 save_page = phy_save_page(phydev);
61 if (save_page < 0) {
62 phydev_warn(phydev, "Failed to get current page\n");
63 goto err;
64 }
65
66 /* Switch to TR page */
67 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
68
69 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
70 (data & 0xFFFF));
71 if (ret < 0) {
72 phydev_warn(phydev, "Failed to write TR low data\n");
73 goto err;
74 }
75
76 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
77 (data & 0x00FF0000) >> 16);
78 if (ret < 0) {
79 phydev_warn(phydev, "Failed to write TR high data\n");
80 goto err;
81 }
82
83 /* Config control bits [15:13] of register */
84 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
85 buf |= 0x8000; /* Set [15] to Packet transmit */
86
87 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
88 if (ret < 0) {
89 phydev_warn(phydev, "Failed to write data in reg\n");
90 goto err;
91 }
92
93 usleep_range(1000, 2000);/* Wait for Data to be written */
94 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
95 if (!(val & 0x8000))
96 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
97 regaddr);
98err:
99 return phy_restore_page(phydev, save_page, ret);
100}
101
102static void lan88xx_config_TR_regs(struct phy_device *phydev)
103{
104 int err;
105
106 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
107 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
108 * MrvlTrFix1000Kp, MasterEnableTR bits.
109 */
110 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
111 if (err < 0)
112 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
113
114 /* Get access to Channel b'10, Node b'1101, Register 0x06.
115 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
116 * SSTrKp1000Mas bits.
117 */
118 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
119 if (err < 0)
120 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
121
122 /* Get access to Channel b'10, Node b'1111, Register 0x11.
123 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
124 * bits
125 */
126 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
127 if (err < 0)
128 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
129
130 /* Get access to Channel b'10, Node b'1101, Register 0x10.
131 * Write 24-bit value 0xEEFFDD to register. Setting
132 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
133 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
134 */
135 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
136 if (err < 0)
137 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
138
139 /* Get access to Channel b'10, Node b'1101, Register 0x13.
140 * Write 24-bit value 0x071448 to register. Setting
141 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
142 */
143 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
144 if (err < 0)
145 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
146
147 /* Get access to Channel b'10, Node b'1101, Register 0x12.
148 * Write 24-bit value 0x13132F to register. Setting
149 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
150 */
151 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
152 if (err < 0)
153 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
154
155 /* Get access to Channel b'10, Node b'1101, Register 0x14.
156 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
157 * eee_TrKf_freeze_delay bits.
158 */
159 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
160 if (err < 0)
161 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
162
163 /* Get access to Channel b'01, Node b'1111, Register 0x34.
164 * Write 24-bit value 0x91B06C to register. Setting
165 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
166 * FastMseSearchUpdGain1000 bits.
167 */
168 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
169 if (err < 0)
170 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
171
172 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
173 * Write 24-bit value 0xC0A028 to register. Setting
174 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
175 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
176 */
177 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
178 if (err < 0)
179 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
180
181 /* Get access to Channel b'01, Node b'1111, Register 0x35.
182 * Write 24-bit value 0x041600 to register. Setting
183 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
184 * FastMsePhChangeDelay1000 bits.
185 */
186 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
187 if (err < 0)
188 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
189
190 /* Get access to Channel b'10, Node b'1101, Register 0x03.
191 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
192 */
193 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
194 if (err < 0)
195 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
196}
197
198static int lan88xx_get_downshift(struct phy_device *phydev, u8 *data)
199{
200 int val;
201
202 val = phy_read_paged(phydev, 1, LAN78XX_PHY_CTRL3);
203 if (val < 0)
204 return val;
205
206 if (!(val & LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT)) {
207 *data = DOWNSHIFT_DEV_DISABLE;
208 return 0;
209 }
210
211 *data = FIELD_GET(LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK, val) + 2;
212
213 return 0;
214}
215
216static int lan88xx_set_downshift(struct phy_device *phydev, u8 cnt)
217{
218 u32 mask = LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK |
219 LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
220
221 if (cnt == DOWNSHIFT_DEV_DISABLE)
222 return phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3,
223 LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT, 0);
224
225 if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
226 cnt = 2;
227
228 if (cnt < 2 || cnt > 5)
229 return -EINVAL;
230
231 return phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3, mask,
232 FIELD_PREP(LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK,
233 cnt - 2) |
234 LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT);
235}
236
237static int lan88xx_get_tunable(struct phy_device *phydev,
238 struct ethtool_tunable *tuna, void *data)
239{
240 switch (tuna->id) {
241 case ETHTOOL_PHY_DOWNSHIFT:
242 return lan88xx_get_downshift(phydev, data);
243 default:
244 return -EOPNOTSUPP;
245 }
246}
247
248static int lan88xx_set_tunable(struct phy_device *phydev,
249 struct ethtool_tunable *tuna, const void *data)
250{
251 struct lan88xx_priv *priv = phydev->priv;
252 int ret;
253
254 switch (tuna->id) {
255 case ETHTOOL_PHY_DOWNSHIFT:
256 ret = lan88xx_set_downshift(phydev, *(const u8 *)data);
257 if (!ret)
258 priv->downshift_cnt = *(const u8 *)data;
259 return ret;
260 default:
261 return -EOPNOTSUPP;
262 }
263}
264
265static int lan88xx_probe(struct phy_device *phydev)
266{
267 struct device *dev = &phydev->mdio.dev;
268 struct lan88xx_priv *priv;
269 u32 led_modes[4];
270 int len;
271
272 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
273 if (!priv)
274 return -ENOMEM;
275
276 priv->wolopts = 0;
277 priv->downshift_cnt = 2;
278
279 len = of_property_read_variable_u32_array(dev->of_node,
280 "microchip,led-modes",
281 led_modes,
282 0,
283 ARRAY_SIZE(led_modes));
284 if (len >= 0) {
285 u32 reg = 0;
286 int i;
287
288 for (i = 0; i < len; i++) {
289 if (led_modes[i] > 15)
290 return -EINVAL;
291 reg |= led_modes[i] << (i * 4);
292 }
293 for (; i < ARRAY_SIZE(led_modes); i++)
294 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
295 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
296 } else if (len == -EOVERFLOW) {
297 return -EINVAL;
298 }
299
300 /* these values can be used to identify internal PHY */
301 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
302 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
303
304 phydev->priv = priv;
305
306 return 0;
307}
308
309static void lan88xx_remove(struct phy_device *phydev)
310{
311 struct device *dev = &phydev->mdio.dev;
312 struct lan88xx_priv *priv = phydev->priv;
313
314 if (priv)
315 devm_kfree(dev, priv);
316}
317
318static int lan88xx_set_wol(struct phy_device *phydev,
319 struct ethtool_wolinfo *wol)
320{
321 struct lan88xx_priv *priv = phydev->priv;
322
323 priv->wolopts = wol->wolopts;
324
325 return 0;
326}
327
328static void lan88xx_set_mdix(struct phy_device *phydev)
329{
330 int buf;
331 int val;
332
333 switch (phydev->mdix_ctrl) {
334 case ETH_TP_MDI:
335 val = LAN88XX_EXT_MODE_CTRL_MDI_;
336 break;
337 case ETH_TP_MDI_X:
338 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
339 break;
340 case ETH_TP_MDI_AUTO:
341 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
342 break;
343 default:
344 return;
345 }
346
347 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
348 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
349 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
350 buf |= val;
351 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
352 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
353}
354
355static int lan88xx_config_init(struct phy_device *phydev)
356{
357 struct lan88xx_priv *priv = phydev->priv;
358 int val, err;
359
360 /*Zerodetect delay enable */
361 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
362 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
363 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
364
365 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
366 val);
367
368 /* Config DSP registers */
369 lan88xx_config_TR_regs(phydev);
370
371 err = lan88xx_set_downshift(phydev, priv->downshift_cnt);
372 if (err < 0)
373 return err;
374
375 return 0;
376}
377
378static int lan88xx_config_aneg(struct phy_device *phydev)
379{
380 lan88xx_set_mdix(phydev);
381
382 return genphy_config_aneg(phydev);
383}
384
385static void lan88xx_link_change_notify(struct phy_device *phydev)
386{
387 int temp;
388 int ret;
389
390 /* Reset PHY to ensure MII_LPA provides up-to-date information. This
391 * issue is reproducible only after parallel detection, as described
392 * in IEEE 802.3-2022, Section 28.2.3.1 ("Parallel detection function"),
393 * where the link partner does not support auto-negotiation.
394 */
395 if (phydev->state == PHY_NOLINK) {
396 ret = phy_init_hw(phydev);
397 if (ret < 0)
398 goto link_change_notify_failed;
399
400 ret = _phy_start_aneg(phydev);
401 if (ret < 0)
402 goto link_change_notify_failed;
403 }
404
405 /* At forced 100 F/H mode, chip may fail to set mode correctly
406 * when cable is switched between long(~50+m) and short one.
407 * As workaround, set to 10 before setting to 100
408 * at forced 100 F/H mode.
409 */
410 if (phydev->state == PHY_NOLINK && !phydev->autoneg && phydev->speed == 100) {
411 /* disable phy interrupt */
412 temp = phy_read(phydev, LAN88XX_INT_MASK);
413 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
414 phy_write(phydev, LAN88XX_INT_MASK, temp);
415
416 temp = phy_read(phydev, MII_BMCR);
417 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
418 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
419 temp |= BMCR_SPEED100;
420 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
421
422 /* clear pending interrupt generated while workaround */
423 temp = phy_read(phydev, LAN88XX_INT_STS);
424
425 /* enable phy interrupt back */
426 temp = phy_read(phydev, LAN88XX_INT_MASK);
427 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
428 phy_write(phydev, LAN88XX_INT_MASK, temp);
429 }
430
431 return;
432
433link_change_notify_failed:
434 phydev_err(phydev, "Link change process failed %pe\n", ERR_PTR(ret));
435}
436
437/**
438 * lan937x_tx_read_mdix_status - Read the MDIX status for the LAN937x TX PHY.
439 * @phydev: Pointer to the phy_device structure.
440 *
441 * This function reads the MDIX status of the LAN937x TX PHY and sets the
442 * mdix_ctrl and mdix fields of the phy_device structure accordingly.
443 * Note that MDIX status is not supported in AUTO mode, and will be set
444 * to invalid in such cases.
445 *
446 * Return: 0 on success, a negative error code on failure.
447 */
448static int lan937x_tx_read_mdix_status(struct phy_device *phydev)
449{
450 int ret;
451
452 ret = phy_read(phydev, LAN937X_MODE_CTRL_STATUS_REG);
453 if (ret < 0)
454 return ret;
455
456 if (ret & LAN937X_AUTOMDIX_EN) {
457 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
458 /* MDI/MDIX status is unknown */
459 phydev->mdix = ETH_TP_MDI_INVALID;
460 } else if (ret & LAN937X_MDI_MODE) {
461 phydev->mdix_ctrl = ETH_TP_MDI_X;
462 phydev->mdix = ETH_TP_MDI_X;
463 } else {
464 phydev->mdix_ctrl = ETH_TP_MDI;
465 phydev->mdix = ETH_TP_MDI;
466 }
467
468 return 0;
469}
470
471/**
472 * lan937x_tx_read_status - Read the status for the LAN937x TX PHY.
473 * @phydev: Pointer to the phy_device structure.
474 *
475 * This function reads the status of the LAN937x TX PHY and updates the
476 * phy_device structure accordingly.
477 *
478 * Return: 0 on success, a negative error code on failure.
479 */
480static int lan937x_tx_read_status(struct phy_device *phydev)
481{
482 int ret;
483
484 ret = genphy_read_status(phydev);
485 if (ret < 0)
486 return ret;
487
488 return lan937x_tx_read_mdix_status(phydev);
489}
490
491/**
492 * lan937x_tx_set_mdix - Set the MDIX mode for the LAN937x TX PHY.
493 * @phydev: Pointer to the phy_device structure.
494 *
495 * This function configures the MDIX mode of the LAN937x TX PHY based on the
496 * mdix_ctrl field of the phy_device structure. The MDIX mode can be set to
497 * MDI (straight-through), MDIX (crossover), or AUTO (auto-MDIX). If the mode
498 * is not recognized, it returns 0 without making any changes.
499 *
500 * Return: 0 on success, a negative error code on failure.
501 */
502static int lan937x_tx_set_mdix(struct phy_device *phydev)
503{
504 u16 val;
505
506 switch (phydev->mdix_ctrl) {
507 case ETH_TP_MDI:
508 val = 0;
509 break;
510 case ETH_TP_MDI_X:
511 val = LAN937X_MDI_MODE;
512 break;
513 case ETH_TP_MDI_AUTO:
514 val = LAN937X_AUTOMDIX_EN;
515 break;
516 default:
517 return 0;
518 }
519
520 return phy_modify(phydev, LAN937X_MODE_CTRL_STATUS_REG,
521 LAN937X_AUTOMDIX_EN | LAN937X_MDI_MODE, val);
522}
523
524/**
525 * lan937x_tx_config_aneg - Configure auto-negotiation and fixed modes for the
526 * LAN937x TX PHY.
527 * @phydev: Pointer to the phy_device structure.
528 *
529 * This function configures the MDIX mode for the LAN937x TX PHY and then
530 * proceeds to configure the auto-negotiation or fixed mode settings
531 * based on the phy_device structure.
532 *
533 * Return: 0 on success, a negative error code on failure.
534 */
535static int lan937x_tx_config_aneg(struct phy_device *phydev)
536{
537 int ret;
538
539 ret = lan937x_tx_set_mdix(phydev);
540 if (ret < 0)
541 return ret;
542
543 return genphy_config_aneg(phydev);
544}
545
546static struct phy_driver microchip_phy_driver[] = {
547{
548 .phy_id = 0x0007c132,
549 /* This mask (0xfffffff2) is to differentiate from
550 * LAN8742 (phy_id 0x0007c130 and 0x0007c131)
551 * and allows future phy_id revisions.
552 * These PHYs are integrated in LAN7800 and LAN7850 USB/Ethernet
553 * controllers.
554 */
555 .phy_id_mask = 0xfffffff2,
556 .name = "Microchip LAN88xx",
557
558 /* PHY_GBIT_FEATURES */
559
560 .probe = lan88xx_probe,
561 .remove = lan88xx_remove,
562
563 .config_init = lan88xx_config_init,
564 .config_aneg = lan88xx_config_aneg,
565 .link_change_notify = lan88xx_link_change_notify,
566 .soft_reset = genphy_soft_reset,
567
568 /* Interrupt handling is broken, do not define related
569 * functions to force polling.
570 */
571
572 .suspend = lan88xx_suspend,
573 .resume = genphy_resume,
574 .set_wol = lan88xx_set_wol,
575 .read_page = lan88xx_read_page,
576 .write_page = lan88xx_write_page,
577 .get_tunable = lan88xx_get_tunable,
578 .set_tunable = lan88xx_set_tunable,
579},
580{
581 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX),
582 .name = "Microchip LAN937x TX",
583 .suspend = genphy_suspend,
584 .resume = genphy_resume,
585 .config_aneg = lan937x_tx_config_aneg,
586 .read_status = lan937x_tx_read_status,
587} };
588
589module_phy_driver(microchip_phy_driver);
590
591static const struct mdio_device_id __maybe_unused microchip_tbl[] = {
592 { 0x0007c132, 0xfffffff2 },
593 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX) },
594 { }
595};
596
597MODULE_DEVICE_TABLE(mdio, microchip_tbl);
598
599MODULE_AUTHOR(DRIVER_AUTHOR);
600MODULE_DESCRIPTION(DRIVER_DESC);
601MODULE_LICENSE("GPL");