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| 2 | |
| 3 | * Driver for Microsemi VSC85xx PHYs
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| 4 | *
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| 5 | * Copyright (C) 2020 Microsemi Corporation
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| 6 |
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| 7 |
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| 8 | #ifndef _MSCC_PHY_FC_BUFFER_H_
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| 9 | #define _MSCC_PHY_FC_BUFFER_H_
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| 10 |
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| 11 | #define MSCC_FCBUF_ENA_CFG 0x00
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| 12 | #define MSCC_FCBUF_MODE_CFG 0x01
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| 13 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG 0x02
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| 14 | #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG 0x03
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| 15 | #define MSCC_FCBUF_TX_DATA_QUEUE_CFG 0x04
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| 16 | #define MSCC_FCBUF_RX_DATA_QUEUE_CFG 0x05
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| 17 | #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG 0x06
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| 18 | #define MSCC_FCBUF_FC_READ_THRESH_CFG 0x07
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| 19 | #define MSCC_FCBUF_TX_FRM_GAP_COMP 0x08
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| 20 |
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| 21 | #define MSCC_FCBUF_ENA_CFG_TX_ENA BIT(0)
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| 22 | #define MSCC_FCBUF_ENA_CFG_RX_ENA BIT(4)
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| 23 |
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| 24 | #define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR BIT(4)
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| 25 | #define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA BIT(8)
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| 26 | #define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA BIT(12)
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| 27 | #define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA BIT(16)
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| 28 | #define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA BIT(20)
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| 29 | #define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA BIT(24)
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| 30 | #define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN BIT(28)
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| 31 |
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| 32 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x) (x)
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| 33 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)
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| 34 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x) ((x) << 16)
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| 35 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M GENMASK(19, 16)
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| 36 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x) ((x) << 20)
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| 37 | #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M GENMASK(31, 20)
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| 38 |
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| 39 | #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x) (x)
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| 40 | #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M GENMASK(15, 0)
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| 41 | #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x) ((x) << 16)
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| 42 | #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M GENMASK(31, 16)
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| 43 |
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| 44 | #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x) (x)
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| 45 | #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)
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| 46 | #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x) ((x) << 16)
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| 47 | #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)
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| 48 |
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| 49 | #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x) (x)
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| 50 | #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)
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| 51 | #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x) ((x) << 16)
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| 52 | #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)
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| 53 |
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| 54 | #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x) (x)
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| 55 | #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M GENMASK(15, 0)
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| 56 | #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x) ((x) << 16)
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| 57 | #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16)
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| 58 |
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| 59 | #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x) (x)
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| 60 | #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)
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| 61 | #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x) ((x) << 16)
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| 62 | #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16)
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| 63 |
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| 64 | #endif
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