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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Clause 45 PHY support
4 */
5#include <linux/ethtool.h>
6#include <linux/export.h>
7#include <linux/mdio.h>
8#include <linux/mii.h>
9#include <linux/phy.h>
10#include <linux/ethtool_netlink.h>
11
12#include "mdio-open-alliance.h"
13#include "phylib-internal.h"
14
15/**
16 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
17 * @phydev: target phy_device struct
18 */
19static bool genphy_c45_baset1_able(struct phy_device *phydev)
20{
21 int val;
22
23 if (phydev->pma_extable == -ENODATA) {
24 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
25 if (val < 0)
26 return false;
27
28 phydev->pma_extable = val;
29 }
30
31 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
32}
33
34/**
35 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
36 * @phydev: target phy_device struct
37 */
38static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
39{
40 int stat1;
41
42 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
43 if (stat1 < 0)
44 return false;
45
46 return !!(stat1 & MDIO_STAT1_LPOWERABLE);
47}
48
49/**
50 * genphy_c45_pma_resume - wakes up the PMA module
51 * @phydev: target phy_device struct
52 */
53int genphy_c45_pma_resume(struct phy_device *phydev)
54{
55 if (!genphy_c45_pma_can_sleep(phydev))
56 return -EOPNOTSUPP;
57
58 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
59 MDIO_CTRL1_LPOWER);
60}
61EXPORT_SYMBOL_GPL(genphy_c45_pma_resume);
62
63/**
64 * genphy_c45_pma_suspend - suspends the PMA module
65 * @phydev: target phy_device struct
66 */
67int genphy_c45_pma_suspend(struct phy_device *phydev)
68{
69 if (!genphy_c45_pma_can_sleep(phydev))
70 return -EOPNOTSUPP;
71
72 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
73 MDIO_CTRL1_LPOWER);
74}
75EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend);
76
77/**
78 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
79 * role of BaseT1 devices.
80 * @phydev: target phy_device struct
81 */
82int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev)
83{
84 int ctl = 0;
85
86 switch (phydev->master_slave_set) {
87 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
88 case MASTER_SLAVE_CFG_MASTER_FORCE:
89 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
90 break;
91 case MASTER_SLAVE_CFG_SLAVE_FORCE:
92 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
93 break;
94 case MASTER_SLAVE_CFG_UNKNOWN:
95 case MASTER_SLAVE_CFG_UNSUPPORTED:
96 return 0;
97 default:
98 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
99 return -EOPNOTSUPP;
100 }
101
102 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
103 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);
104}
105EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave);
106
107/**
108 * genphy_c45_pma_setup_forced - configures a forced speed
109 * @phydev: target phy_device struct
110 */
111int genphy_c45_pma_setup_forced(struct phy_device *phydev)
112{
113 int bt1_ctrl, ctrl1, ctrl2, ret;
114
115 /* Half duplex is not supported */
116 if (phydev->duplex != DUPLEX_FULL)
117 return -EINVAL;
118
119 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
120 if (ctrl1 < 0)
121 return ctrl1;
122
123 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
124 if (ctrl2 < 0)
125 return ctrl2;
126
127 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
128 /*
129 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1
130 * in 802.3-2012 and 802.3-2015.
131 */
132 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
133
134 switch (phydev->speed) {
135 case SPEED_10:
136 if (genphy_c45_baset1_able(phydev))
137 ctrl2 |= MDIO_PMA_CTRL2_BASET1;
138 else
139 ctrl2 |= MDIO_PMA_CTRL2_10BT;
140 break;
141 case SPEED_100:
142 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
143 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
144 break;
145 case SPEED_1000:
146 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
147 /* Assume 1000base-T */
148 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
149 break;
150 case SPEED_2500:
151 ctrl1 |= MDIO_PMA_CTRL1_SPEED2_5G;
152 /* Assume 2.5Gbase-T */
153 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
154 break;
155 case SPEED_5000:
156 ctrl1 |= MDIO_PMA_CTRL1_SPEED5G;
157 /* Assume 5Gbase-T */
158 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
159 break;
160 case SPEED_10000:
161 ctrl1 |= MDIO_CTRL1_SPEED10G;
162 /* Assume 10Gbase-T */
163 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
164 break;
165 default:
166 return -EINVAL;
167 }
168
169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
170 if (ret < 0)
171 return ret;
172
173 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
174 if (ret < 0)
175 return ret;
176
177 if (genphy_c45_baset1_able(phydev)) {
178 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
179 if (ret < 0)
180 return ret;
181
182 bt1_ctrl = 0;
183 if (phydev->speed == SPEED_1000)
184 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000;
185
186 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
187 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl);
188 if (ret < 0)
189 return ret;
190 }
191
192 return genphy_c45_an_disable_aneg(phydev);
193}
194EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
195
196/* Sets master/slave preference and supported technologies.
197 * The preference is set in the BIT(4) of BASE-T1 AN
198 * advertisement register 7.515 and whether the status
199 * is forced or not, it is set in the BIT(12) of BASE-T1
200 * AN advertisement register 7.514.
201 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
202 * advertisement register [31:16] if supported.
203 */
204static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
205{
206 u16 adv_l_mask, adv_l = 0;
207 u16 adv_m_mask, adv_m = 0;
208 int changed = 0;
209 int ret;
210
211 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP |
212 MDIO_AN_T1_ADV_L_PAUSE_ASYM;
213 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 |
214 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L;
215
216 switch (phydev->master_slave_set) {
217 case MASTER_SLAVE_CFG_MASTER_FORCE:
218 adv_m |= MDIO_AN_T1_ADV_M_MST;
219 fallthrough;
220 case MASTER_SLAVE_CFG_SLAVE_FORCE:
221 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;
222 break;
223 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
224 adv_m |= MDIO_AN_T1_ADV_M_MST;
225 fallthrough;
226 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
227 break;
228 case MASTER_SLAVE_CFG_UNKNOWN:
229 case MASTER_SLAVE_CFG_UNSUPPORTED:
230 /* if master/slave role is not specified, do not overwrite it */
231 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS;
232 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST;
233 break;
234 default:
235 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
236 return -EOPNOTSUPP;
237 }
238
239 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
240
241 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
242 adv_l_mask, adv_l);
243 if (ret < 0)
244 return ret;
245 if (ret > 0)
246 changed = 1;
247
248 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
249
250 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
251 adv_m_mask, adv_m);
252 if (ret < 0)
253 return ret;
254 if (ret > 0)
255 changed = 1;
256
257 return changed;
258}
259
260/**
261 * genphy_c45_an_config_aneg - configure advertisement registers
262 * @phydev: target phy_device struct
263 *
264 * Configure advertisement registers based on modes set in phydev->advertising
265 *
266 * Returns negative errno code on failure, 0 if advertisement didn't change,
267 * or 1 if advertised modes changed.
268 */
269int genphy_c45_an_config_aneg(struct phy_device *phydev)
270{
271 int changed = 0, ret;
272 u32 adv;
273
274 linkmode_and(phydev->advertising, phydev->advertising,
275 phydev->supported);
276
277 ret = genphy_c45_an_config_eee_aneg(phydev);
278 if (ret < 0)
279 return ret;
280 else if (ret)
281 changed = true;
282
283 if (genphy_c45_baset1_able(phydev))
284 return genphy_c45_baset1_an_config_aneg(phydev);
285
286 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
287
288 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
289 ADVERTISE_ALL | ADVERTISE_100BASE4 |
290 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
291 adv);
292 if (ret < 0)
293 return ret;
294 if (ret > 0)
295 changed = 1;
296
297 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
298
299 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
300 MDIO_AN_10GBT_CTRL_ADV10G |
301 MDIO_AN_10GBT_CTRL_ADV5G |
302 MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
303 if (ret < 0)
304 return ret;
305 if (ret > 0)
306 changed = 1;
307
308 return changed;
309}
310EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
311
312/**
313 * genphy_c45_an_disable_aneg - disable auto-negotiation
314 * @phydev: target phy_device struct
315 *
316 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
317 * are controlled through the PMA/PMD MMD registers.
318 *
319 * Returns zero on success, negative errno code on failure.
320 */
321int genphy_c45_an_disable_aneg(struct phy_device *phydev)
322{
323 u16 reg = MDIO_CTRL1;
324
325 if (genphy_c45_baset1_able(phydev))
326 reg = MDIO_AN_T1_CTRL;
327
328 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
329 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
330}
331EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
332
333/**
334 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
335 * @phydev: target phy_device struct
336 *
337 * This assumes that the auto-negotiation MMD is present.
338 *
339 * Enable and restart auto-negotiation.
340 */
341int genphy_c45_restart_aneg(struct phy_device *phydev)
342{
343 u16 reg = MDIO_CTRL1;
344
345 if (genphy_c45_baset1_able(phydev))
346 reg = MDIO_AN_T1_CTRL;
347
348 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
349 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
350}
351EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
352
353/**
354 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
355 * @phydev: target phy_device struct
356 * @restart: whether aneg restart is requested
357 *
358 * This assumes that the auto-negotiation MMD is present.
359 *
360 * Check, and restart auto-negotiation if needed.
361 */
362int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
363{
364 u16 reg = MDIO_CTRL1;
365 int ret;
366
367 if (genphy_c45_baset1_able(phydev))
368 reg = MDIO_AN_T1_CTRL;
369
370 if (!restart) {
371 /* Configure and restart aneg if it wasn't set before */
372 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
373 if (ret < 0)
374 return ret;
375
376 if (!(ret & MDIO_AN_CTRL1_ENABLE))
377 restart = true;
378 }
379
380 if (restart)
381 return genphy_c45_restart_aneg(phydev);
382
383 return 0;
384}
385EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
386
387/**
388 * genphy_c45_pma_soft_reset - software reset the PHY via Clause 45 PMA/PMD control register
389 * @phydev: target phy_device struct
390 *
391 * Return: 0 on success, negative errno on failure.
392 */
393int genphy_c45_pma_soft_reset(struct phy_device *phydev)
394{
395 int ret, val;
396
397 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
398 MDIO_CTRL1_RESET);
399 if (ret < 0)
400 return ret;
401
402 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
403 MDIO_CTRL1, val,
404 !(val & MDIO_CTRL1_RESET),
405 5000, 600000, true);
406}
407EXPORT_SYMBOL_GPL(genphy_c45_pma_soft_reset);
408
409/**
410 * genphy_c45_an_setup_master_slave - Configure Master/Slave setting for C45 PHYs
411 * @phydev: target phy_device struct
412 *
413 * Description: Configure the forced or preferred Master/Slave role
414 * 10GBASE-T control register (MMD 7, Register 0x0020) according to
415 * IEEE 802.3 standards.
416 *
417 * Return: negative errno code on failure, 0 if Master/Slave didn't change,
418 * or 1 if Master/Slave modes changed.
419 */
420static int genphy_c45_an_setup_master_slave(struct phy_device *phydev)
421{
422 u16 ctl = 0;
423
424 switch (phydev->master_slave_set) {
425 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
426 ctl = MDIO_AN_10GBT_CTRL_MS_PORT_TYPE;
427 break;
428 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
429 break;
430 case MASTER_SLAVE_CFG_MASTER_FORCE:
431 ctl = MDIO_AN_10GBT_CTRL_MS_ENABLE | MDIO_AN_10GBT_CTRL_MS_VALUE;
432 break;
433 case MASTER_SLAVE_CFG_SLAVE_FORCE:
434 ctl = MDIO_AN_10GBT_CTRL_MS_ENABLE;
435 break;
436 case MASTER_SLAVE_CFG_UNKNOWN:
437 case MASTER_SLAVE_CFG_UNSUPPORTED:
438 return 0;
439 default:
440 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
441 return -EOPNOTSUPP;
442 }
443
444 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
445 MDIO_AN_10GBT_CTRL_MS_ENABLE |
446 MDIO_AN_10GBT_CTRL_MS_VALUE |
447 MDIO_AN_10GBT_CTRL_MS_PORT_TYPE, ctl);
448}
449
450/**
451 * genphy_c45_read_master_slave - read master/slave status
452 * @phydev: target phy_device struct
453 *
454 * Description: Read the Master/Slave configuration and status
455 * from 10GBASE-T control/status registers (MMD 7, Reg 0x0020 and 0x0021).
456 *
457 * Return: 0 on success, or a negative error code on failure.
458 */
459static int genphy_c45_read_master_slave(struct phy_device *phydev)
460{
461 int val;
462
463 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
464 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
465
466 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
467 if (val < 0)
468 return val;
469
470 if (val & MDIO_AN_10GBT_CTRL_MS_ENABLE) {
471 if (val & MDIO_AN_10GBT_CTRL_MS_VALUE)
472 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
473 else
474 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
475 } else {
476 if (val & MDIO_AN_10GBT_CTRL_MS_PORT_TYPE)
477 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
478 else
479 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
480 }
481
482 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
483 if (val < 0)
484 return val;
485
486 if (val & MDIO_AN_10GBT_STAT_MS_FAULT) {
487 phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;
488 } else if (phydev->link) {
489 if (val & MDIO_AN_10GBT_STAT_MS_RES)
490 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
491 else
492 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
493 } else {
494 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
495 }
496
497 return 0;
498}
499
500/**
501 * genphy_c45_aneg_done - return auto-negotiation complete status
502 * @phydev: target phy_device struct
503 *
504 * This assumes that the auto-negotiation MMD is present.
505 *
506 * Reads the status register from the auto-negotiation MMD, returning:
507 * - positive if auto-negotiation is complete
508 * - negative errno code on error
509 * - zero otherwise
510 */
511int genphy_c45_aneg_done(struct phy_device *phydev)
512{
513 int reg = MDIO_STAT1;
514 int val;
515
516 if (genphy_c45_baset1_able(phydev))
517 reg = MDIO_AN_T1_STAT;
518
519 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
520
521 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
522}
523EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
524
525/**
526 * genphy_c45_read_link - read the overall link status from the MMDs
527 * @phydev: target phy_device struct
528 *
529 * Read the link status from the specified MMDs, and if they all indicate
530 * that the link is up, set phydev->link to 1. If an error is encountered,
531 * a negative errno will be returned, otherwise zero.
532 */
533int genphy_c45_read_link(struct phy_device *phydev)
534{
535 u32 mmd_mask = MDIO_DEVS_PMAPMD;
536 int val, devad;
537 bool link = true;
538
539 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
540 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
541 if (val < 0)
542 return val;
543
544 /* Autoneg is being started, therefore disregard current
545 * link status and report link as down.
546 */
547 if (val & MDIO_AN_CTRL1_RESTART) {
548 phydev->link = 0;
549 return 0;
550 }
551 }
552
553 while (mmd_mask && link) {
554 devad = __ffs(mmd_mask);
555 mmd_mask &= ~BIT(devad);
556
557 /* The link state is latched low so that momentary link
558 * drops can be detected. Do not double-read the status
559 * in polling mode to detect such short link drops except
560 * the link was already down.
561 */
562 if (!phy_polling_mode(phydev) || !phydev->link) {
563 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
564 if (val < 0)
565 return val;
566 else if (val & MDIO_STAT1_LSTATUS)
567 continue;
568 }
569
570 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
571 if (val < 0)
572 return val;
573
574 if (!(val & MDIO_STAT1_LSTATUS))
575 link = false;
576 }
577
578 phydev->link = link;
579
580 return 0;
581}
582EXPORT_SYMBOL_GPL(genphy_c45_read_link);
583
584/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
585 * if autoneg is complete. If so read the BASE-T1 Autonegotiation
586 * Advertisement registers filling in the link partner advertisement,
587 * pause and asym_pause members in phydev.
588 */
589static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
590{
591 int val;
592
593 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
594 if (val < 0)
595 return val;
596
597 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
598 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
599 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
600 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
601
602 phydev->pause = false;
603 phydev->asym_pause = false;
604
605 return 0;
606 }
607
608 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
609
610 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
611 if (val < 0)
612 return val;
613
614 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
615 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP;
616 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM;
617
618 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
619 if (val < 0)
620 return val;
621
622 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
623
624 return 0;
625}
626
627/**
628 * genphy_c45_read_lpa - read the link partner advertisement and pause
629 * @phydev: target phy_device struct
630 *
631 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
632 * filling in the link partner advertisement, pause and asym_pause members
633 * in @phydev. This assumes that the auto-negotiation MMD is present, and
634 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
635 * to fill in the remainder of the link partner advert from vendor registers.
636 */
637int genphy_c45_read_lpa(struct phy_device *phydev)
638{
639 int val;
640
641 if (genphy_c45_baset1_able(phydev))
642 return genphy_c45_baset1_read_lpa(phydev);
643
644 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
645 if (val < 0)
646 return val;
647
648 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
649 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
650 phydev->lp_advertising);
651 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
652 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
653 phydev->pause = false;
654 phydev->asym_pause = false;
655
656 return 0;
657 }
658
659 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
660 val & MDIO_AN_STAT1_LPABLE);
661
662 /* Read the link partner's base page advertisement */
663 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
664 if (val < 0)
665 return val;
666
667 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
668 phydev->pause = val & LPA_PAUSE_CAP;
669 phydev->asym_pause = val & LPA_PAUSE_ASYM;
670
671 /* Read the link partner's 10G advertisement */
672 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
673 if (val < 0)
674 return val;
675
676 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
677
678 return 0;
679}
680EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
681
682/**
683 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
684 * configuration
685 * @phydev: target phy_device struct
686 */
687int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev)
688{
689 int val;
690
691 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
692 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
693
694 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
695 if (val < 0)
696 return val;
697
698 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) {
699 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
700 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
701 } else {
702 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
703 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
704 }
705
706 return 0;
707}
708EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave);
709
710/**
711 * genphy_c45_read_pma - read link speed etc from PMA
712 * @phydev: target phy_device struct
713 */
714int genphy_c45_read_pma(struct phy_device *phydev)
715{
716 int val;
717
718 linkmode_zero(phydev->lp_advertising);
719
720 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
721 if (val < 0)
722 return val;
723
724 switch (val & MDIO_CTRL1_SPEEDSEL) {
725 case 0:
726 phydev->speed = SPEED_10;
727 break;
728 case MDIO_PMA_CTRL1_SPEED100:
729 phydev->speed = SPEED_100;
730 break;
731 case MDIO_PMA_CTRL1_SPEED1000:
732 phydev->speed = SPEED_1000;
733 break;
734 case MDIO_PMA_CTRL1_SPEED2_5G:
735 phydev->speed = SPEED_2500;
736 break;
737 case MDIO_PMA_CTRL1_SPEED5G:
738 phydev->speed = SPEED_5000;
739 break;
740 case MDIO_CTRL1_SPEED10G:
741 phydev->speed = SPEED_10000;
742 break;
743 default:
744 phydev->speed = SPEED_UNKNOWN;
745 break;
746 }
747
748 phydev->duplex = DUPLEX_FULL;
749
750 if (genphy_c45_baset1_able(phydev)) {
751 val = genphy_c45_pma_baset1_read_master_slave(phydev);
752 if (val < 0)
753 return val;
754 }
755
756 return 0;
757}
758EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
759
760/**
761 * genphy_c45_read_mdix - read mdix status from PMA
762 * @phydev: target phy_device struct
763 */
764int genphy_c45_read_mdix(struct phy_device *phydev)
765{
766 int val;
767
768 if (phydev->speed == SPEED_10000) {
769 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
770 MDIO_PMA_10GBT_SWAPPOL);
771 if (val < 0)
772 return val;
773
774 switch (val) {
775 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
776 phydev->mdix = ETH_TP_MDI;
777 break;
778
779 case 0:
780 phydev->mdix = ETH_TP_MDI_X;
781 break;
782
783 default:
784 phydev->mdix = ETH_TP_MDI_INVALID;
785 break;
786 }
787 }
788
789 return 0;
790}
791EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
792
793/**
794 * genphy_c45_write_eee_adv - write advertised EEE link modes
795 * @phydev: target phy_device struct
796 * @adv: the linkmode advertisement settings
797 */
798static int genphy_c45_write_eee_adv(struct phy_device *phydev,
799 unsigned long *adv)
800{
801 int val, changed = 0;
802
803 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
804 val = linkmode_to_mii_eee_cap1_t(adv);
805
806 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
807 * (Register 7.60)
808 */
809 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
810 MDIO_AN_EEE_ADV,
811 MDIO_EEE_100TX | MDIO_EEE_1000T |
812 MDIO_EEE_10GT | MDIO_EEE_1000KX |
813 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR,
814 val);
815 if (val < 0)
816 return val;
817 if (val > 0)
818 changed = 1;
819 }
820
821 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
822 val = linkmode_to_mii_eee_cap2_t(adv);
823
824 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2
825 * (Register 7.62)
826 */
827 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
828 MDIO_AN_EEE_ADV2,
829 MDIO_EEE_2_5GT | MDIO_EEE_5GT,
830 val);
831 if (val < 0)
832 return val;
833 if (val > 0)
834 changed = 1;
835 }
836
837 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
838 phydev->supported_eee)) {
839 val = linkmode_adv_to_mii_10base_t1_t(adv);
840 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
841 * (Register 7.526)
842 */
843 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
844 MDIO_AN_10BT1_AN_CTRL,
845 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L,
846 val);
847 if (val < 0)
848 return val;
849 if (val > 0)
850 changed = 1;
851 }
852
853 return changed;
854}
855
856/**
857 * genphy_c45_read_eee_adv - read advertised EEE link modes
858 * @phydev: target phy_device struct
859 * @adv: the linkmode advertisement status
860 */
861int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv)
862{
863 int val;
864
865 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
866 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
867 * (Register 7.60)
868 */
869 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
870 if (val < 0)
871 return val;
872
873 mii_eee_cap1_mod_linkmode_t(adv, val);
874 }
875
876 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
877 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2
878 * (Register 7.62)
879 */
880 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
881 if (val < 0)
882 return val;
883
884 mii_eee_cap2_mod_linkmode_adv_t(adv, val);
885 }
886
887 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
888 phydev->supported_eee)) {
889 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
890 * (Register 7.526)
891 */
892 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
893 if (val < 0)
894 return val;
895
896 mii_10base_t1_adv_mod_linkmode_t(adv, val);
897 }
898
899 return 0;
900}
901
902/**
903 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes
904 * @phydev: target phy_device struct
905 * @lpa: the linkmode LP advertisement status
906 */
907static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
908 unsigned long *lpa)
909{
910 int val;
911
912 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
913 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1
914 * (Register 7.61)
915 */
916 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
917 if (val < 0)
918 return val;
919
920 mii_eee_cap1_mod_linkmode_t(lpa, val);
921 }
922
923 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
924 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2
925 * (Register 7.63)
926 */
927 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2);
928 if (val < 0)
929 return val;
930
931 mii_eee_cap2_mod_linkmode_adv_t(lpa, val);
932 }
933
934 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
935 phydev->supported_eee)) {
936 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register
937 * (Register 7.527)
938 */
939 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
940 if (val < 0)
941 return val;
942
943 mii_10base_t1_adv_mod_linkmode_t(lpa, val);
944 }
945
946 return 0;
947}
948
949/**
950 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
951 * @phydev: target phy_device struct
952 */
953static int genphy_c45_read_eee_cap1(struct phy_device *phydev)
954{
955 int val;
956
957 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1
958 * (Register 3.20)
959 */
960 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
961 if (val < 0)
962 return val;
963
964 /* The 802.3 2018 standard says the top 2 bits are reserved and should
965 * read as 0. Also, it seems unlikely anybody will build a PHY which
966 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE.
967 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported.
968 */
969 if (val == 0xffff)
970 return 0;
971
972 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val);
973
974 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE
975 * which they don't support as indicated by BMSR, ESTATUS etc.
976 */
977 linkmode_and(phydev->supported_eee, phydev->supported_eee,
978 phydev->supported);
979
980 return 0;
981}
982
983/**
984 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21
985 * @phydev: target phy_device struct
986 */
987static int genphy_c45_read_eee_cap2(struct phy_device *phydev)
988{
989 int val;
990
991 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2
992 * (Register 3.21)
993 */
994 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2);
995 if (val < 0)
996 return val;
997
998 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */
999 if (val == 0xffff)
1000 return 0;
1001
1002 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val);
1003
1004 return 0;
1005}
1006
1007/**
1008 * genphy_c45_read_eee_abilities - read supported EEE link modes
1009 * @phydev: target phy_device struct
1010 */
1011int genphy_c45_read_eee_abilities(struct phy_device *phydev)
1012{
1013 int val;
1014
1015 /* There is not indicator whether optional register
1016 * "EEE control and capability 1" (3.20) is supported. Read it only
1017 * on devices with appropriate linkmodes.
1018 */
1019 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
1020 val = genphy_c45_read_eee_cap1(phydev);
1021 if (val)
1022 return val;
1023 }
1024
1025 /* Same for cap2 (3.21) */
1026 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) {
1027 val = genphy_c45_read_eee_cap2(phydev);
1028 if (val)
1029 return val;
1030 }
1031
1032 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
1033 phydev->supported)) {
1034 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register
1035 * (Register 1.2295)
1036 */
1037 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
1038 if (val < 0)
1039 return val;
1040
1041 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
1042 phydev->supported_eee,
1043 val & MDIO_PMA_10T1L_STAT_EEE);
1044 }
1045
1046 return 0;
1047}
1048EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities);
1049
1050/**
1051 * genphy_c45_an_config_eee_aneg - configure EEE advertisement
1052 * @phydev: target phy_device struct
1053 */
1054int genphy_c45_an_config_eee_aneg(struct phy_device *phydev)
1055{
1056 /* Writing MMD AN advertisements while autoneg is disabled has no
1057 * effect on link-partner negotiation, but on some PHYs (e.g. the
1058 * Broadcom BCM54213PE) the write itself disturbs the receive
1059 * datapath. Skip it.
1060 */
1061 if (phydev->autoneg == AUTONEG_DISABLE)
1062 return 0;
1063
1064 if (!phydev->eee_cfg.eee_enabled) {
1065 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
1066
1067 return genphy_c45_write_eee_adv(phydev, adv);
1068 }
1069
1070 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee);
1071}
1072EXPORT_SYMBOL_GPL(genphy_c45_an_config_eee_aneg);
1073
1074/**
1075 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA
1076 * @phydev: target phy_device struct
1077 *
1078 * Read the supported link modes from the extended BASE-T1 ability register
1079 */
1080int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)
1081{
1082 int val;
1083
1084 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
1085 if (val < 0)
1086 return val;
1087
1088 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
1089 phydev->supported,
1090 val & MDIO_PMA_PMD_BT1_B10L_ABLE);
1091
1092 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
1093 phydev->supported,
1094 val & MDIO_PMA_PMD_BT1_B100_ABLE);
1095
1096 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT,
1097 phydev->supported,
1098 val & MDIO_PMA_PMD_BT1_B1000_ABLE);
1099
1100 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
1101 if (val < 0)
1102 return val;
1103
1104 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1105 phydev->supported,
1106 val & MDIO_AN_STAT1_ABLE);
1107
1108 return 0;
1109}
1110EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities);
1111
1112/**
1113 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA
1114 * @phydev: target phy_device struct
1115 *
1116 * Read the supported link modes from the PMA/PMD extended ability register
1117 * (Register 1.11).
1118 */
1119int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev)
1120{
1121 int val;
1122
1123 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
1124 if (val < 0)
1125 return val;
1126
1127 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
1128 phydev->supported,
1129 val & MDIO_PMA_EXTABLE_10GBLRM);
1130 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1131 phydev->supported,
1132 val & MDIO_PMA_EXTABLE_10GBT);
1133 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1134 phydev->supported,
1135 val & MDIO_PMA_EXTABLE_10GBKX4);
1136 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1137 phydev->supported,
1138 val & MDIO_PMA_EXTABLE_10GBKR);
1139 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1140 phydev->supported,
1141 val & MDIO_PMA_EXTABLE_1000BT);
1142 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1143 phydev->supported,
1144 val & MDIO_PMA_EXTABLE_1000BKX);
1145
1146 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1147 phydev->supported,
1148 val & MDIO_PMA_EXTABLE_100BTX);
1149 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1150 phydev->supported,
1151 val & MDIO_PMA_EXTABLE_100BTX);
1152
1153 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
1154 phydev->supported,
1155 val & MDIO_PMA_EXTABLE_10BT);
1156 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
1157 phydev->supported,
1158 val & MDIO_PMA_EXTABLE_10BT);
1159
1160 if (val & MDIO_PMA_EXTABLE_NBT) {
1161 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
1162 MDIO_PMA_NG_EXTABLE);
1163 if (val < 0)
1164 return val;
1165
1166 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1167 phydev->supported,
1168 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
1169
1170 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1171 phydev->supported,
1172 val & MDIO_PMA_NG_EXTABLE_5GBT);
1173 }
1174
1175 if (val & MDIO_PMA_EXTABLE_BT1) {
1176 val = genphy_c45_pma_baset1_read_abilities(phydev);
1177 if (val < 0)
1178 return val;
1179 }
1180
1181 return 0;
1182}
1183EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities);
1184
1185/**
1186 * genphy_c45_pma_read_abilities - read supported link modes from PMA
1187 * @phydev: target phy_device struct
1188 *
1189 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
1190 * 1.8.9 is set, the list of supported modes is build using the values in the
1191 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
1192 * modes. If bit 1.11.14 is set, then the list is also extended with the modes
1193 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
1194 * 5GBASET are supported.
1195 */
1196int genphy_c45_pma_read_abilities(struct phy_device *phydev)
1197{
1198 int val;
1199
1200 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1201 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
1202 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1203 if (val < 0)
1204 return val;
1205
1206 if (val & MDIO_AN_STAT1_ABLE)
1207 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1208 phydev->supported);
1209 }
1210
1211 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
1212 if (val < 0)
1213 return val;
1214
1215 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1216 phydev->supported,
1217 val & MDIO_PMA_STAT2_10GBSR);
1218
1219 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1220 phydev->supported,
1221 val & MDIO_PMA_STAT2_10GBLR);
1222
1223 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
1224 phydev->supported,
1225 val & MDIO_PMA_STAT2_10GBER);
1226
1227 if (val & MDIO_PMA_STAT2_EXTABLE) {
1228 val = genphy_c45_pma_read_ext_abilities(phydev);
1229 if (val < 0)
1230 return val;
1231 }
1232
1233 /* This is optional functionality. If not supported, we may get an error
1234 * which should be ignored.
1235 */
1236 genphy_c45_read_eee_abilities(phydev);
1237
1238 return 0;
1239}
1240EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
1241
1242/* Read master/slave preference from registers.
1243 * The preference is read from the BIT(4) of BASE-T1 AN
1244 * advertisement register 7.515 and whether the preference
1245 * is forced or not, it is read from BASE-T1 AN advertisement
1246 * register 7.514.
1247 */
1248int genphy_c45_baset1_read_status(struct phy_device *phydev)
1249{
1250 int ret;
1251 int cfg;
1252
1253 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1254 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1255
1256 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
1257 if (ret < 0)
1258 return ret;
1259
1260 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
1261 if (cfg < 0)
1262 return cfg;
1263
1264 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
1265 if (cfg & MDIO_AN_T1_ADV_M_MST)
1266 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1267 else
1268 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1269 } else {
1270 if (cfg & MDIO_AN_T1_ADV_M_MST)
1271 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
1272 else
1273 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
1274 }
1275
1276 return 0;
1277}
1278EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status);
1279
1280/**
1281 * genphy_c45_read_status - read PHY status
1282 * @phydev: target phy_device struct
1283 *
1284 * Reads status from PHY and sets phy_device members accordingly.
1285 */
1286int genphy_c45_read_status(struct phy_device *phydev)
1287{
1288 int ret;
1289
1290 ret = genphy_c45_read_link(phydev);
1291 if (ret)
1292 return ret;
1293
1294 phydev->speed = SPEED_UNKNOWN;
1295 phydev->duplex = DUPLEX_UNKNOWN;
1296 phydev->pause = false;
1297 phydev->asym_pause = false;
1298
1299 if (phydev->autoneg == AUTONEG_ENABLE) {
1300 ret = genphy_c45_read_lpa(phydev);
1301 if (ret)
1302 return ret;
1303
1304 if (genphy_c45_baset1_able(phydev)) {
1305 ret = genphy_c45_baset1_read_status(phydev);
1306 if (ret < 0)
1307 return ret;
1308 } else {
1309 ret = genphy_c45_read_master_slave(phydev);
1310 if (ret < 0)
1311 return ret;
1312 }
1313
1314 phy_resolve_aneg_linkmode(phydev);
1315 } else {
1316 ret = genphy_c45_read_pma(phydev);
1317 }
1318
1319 return ret;
1320}
1321EXPORT_SYMBOL_GPL(genphy_c45_read_status);
1322
1323/**
1324 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
1325 * @phydev: target phy_device struct
1326 *
1327 * Description: If auto-negotiation is enabled, we configure the
1328 * advertising, and then restart auto-negotiation. If it is not
1329 * enabled, then we force a configuration.
1330 */
1331int genphy_c45_config_aneg(struct phy_device *phydev)
1332{
1333 bool changed = false;
1334 int ret;
1335
1336 if (phydev->autoneg == AUTONEG_DISABLE)
1337 return genphy_c45_pma_setup_forced(phydev);
1338
1339 ret = genphy_c45_an_config_aneg(phydev);
1340 if (ret < 0)
1341 return ret;
1342 if (ret > 0)
1343 changed = true;
1344
1345 if (!genphy_c45_baset1_able(phydev)) {
1346 ret = genphy_c45_an_setup_master_slave(phydev);
1347 if (ret < 0)
1348 return ret;
1349 if (ret > 0)
1350 changed = true;
1351 }
1352
1353 return genphy_c45_check_and_restart_aneg(phydev, changed);
1354}
1355EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
1356
1357/* The gen10g_* functions are the old Clause 45 stub */
1358
1359int gen10g_config_aneg(struct phy_device *phydev)
1360{
1361 return 0;
1362}
1363EXPORT_SYMBOL_GPL(gen10g_config_aneg);
1364
1365int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed)
1366{
1367 if (enable && speed)
1368 return -EOPNOTSUPP;
1369
1370 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
1371 MDIO_PCS_CTRL1_LOOPBACK,
1372 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0);
1373}
1374EXPORT_SYMBOL_GPL(genphy_c45_loopback);
1375
1376/**
1377 * genphy_c45_fast_retrain - configure fast retrain registers
1378 * @phydev: target phy_device struct
1379 * @enable: enable fast retrain or not
1380 *
1381 * Description: If fast-retrain is enabled, we configure PHY as
1382 * advertising fast retrain capable and THP Bypass Request, then
1383 * enable fast retrain. If it is not enabled, we configure fast
1384 * retrain disabled.
1385 */
1386int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
1387{
1388 int ret;
1389
1390 if (!enable)
1391 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1392 MDIO_PMA_10GBR_FSRT_ENABLE);
1393
1394 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
1395 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1396 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G);
1397 if (ret)
1398 return ret;
1399
1400 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
1401 MDIO_AN_THP_BP2_5GT);
1402 if (ret)
1403 return ret;
1404 }
1405
1406 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1407 MDIO_PMA_10GBR_FSRT_ENABLE);
1408}
1409EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);
1410
1411/**
1412 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers
1413 * @phydev: target phy_device struct
1414 * @plca_cfg: output structure to store the PLCA configuration
1415 *
1416 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1417 * Management Registers specifications, this function can be used to retrieve
1418 * the current PLCA configuration from the standard registers in MMD 31.
1419 */
1420int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1421 struct phy_plca_cfg *plca_cfg)
1422{
1423 int ret;
1424
1425 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER);
1426 if (ret < 0)
1427 return ret;
1428
1429 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM)
1430 return -ENODEV;
1431
1432 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM;
1433
1434 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0);
1435 if (ret < 0)
1436 return ret;
1437
1438 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN);
1439
1440 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1);
1441 if (ret < 0)
1442 return ret;
1443
1444 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8;
1445 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID);
1446
1447 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR);
1448 if (ret < 0)
1449 return ret;
1450
1451 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT;
1452
1453 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST);
1454 if (ret < 0)
1455 return ret;
1456
1457 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8;
1458 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR);
1459
1460 return 0;
1461}
1462EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg);
1463
1464/**
1465 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers
1466 * @phydev: target phy_device struct
1467 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are
1468 * not to be changed.
1469 *
1470 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1471 * Management Registers specifications, this function can be used to modify
1472 * the PLCA configuration using the standard registers in MMD 31.
1473 */
1474int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1475 const struct phy_plca_cfg *plca_cfg)
1476{
1477 u16 val = 0;
1478 int ret;
1479
1480 // PLCA IDVER is read-only
1481 if (plca_cfg->version >= 0)
1482 return -EINVAL;
1483
1484 // first of all, disable PLCA if required
1485 if (plca_cfg->enabled == 0) {
1486 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1487 MDIO_OATC14_PLCA_CTRL0,
1488 MDIO_OATC14_PLCA_EN);
1489
1490 if (ret < 0)
1491 return ret;
1492 }
1493
1494 // check if we need to set the PLCA node count, node ID, or both
1495 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) {
1496 /* if one between node count and node ID is -not- to be
1497 * changed, read the register to later perform merge/purge of
1498 * the configuration as appropriate
1499 */
1500 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) {
1501 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1502 MDIO_OATC14_PLCA_CTRL1);
1503
1504 if (ret < 0)
1505 return ret;
1506
1507 val = ret;
1508 }
1509
1510 if (plca_cfg->node_cnt >= 0)
1511 val = (val & ~MDIO_OATC14_PLCA_NCNT) |
1512 (plca_cfg->node_cnt << 8);
1513
1514 if (plca_cfg->node_id >= 0)
1515 val = (val & ~MDIO_OATC14_PLCA_ID) |
1516 (plca_cfg->node_id);
1517
1518 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1519 MDIO_OATC14_PLCA_CTRL1, val);
1520
1521 if (ret < 0)
1522 return ret;
1523 }
1524
1525 if (plca_cfg->to_tmr >= 0) {
1526 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1527 MDIO_OATC14_PLCA_TOTMR,
1528 plca_cfg->to_tmr);
1529
1530 if (ret < 0)
1531 return ret;
1532 }
1533
1534 // check if we need to set the PLCA burst count, burst timer, or both
1535 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) {
1536 /* if one between burst count and burst timer is -not- to be
1537 * changed, read the register to later perform merge/purge of
1538 * the configuration as appropriate
1539 */
1540 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) {
1541 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1542 MDIO_OATC14_PLCA_BURST);
1543
1544 if (ret < 0)
1545 return ret;
1546
1547 val = ret;
1548 }
1549
1550 if (plca_cfg->burst_cnt >= 0)
1551 val = (val & ~MDIO_OATC14_PLCA_MAXBC) |
1552 (plca_cfg->burst_cnt << 8);
1553
1554 if (plca_cfg->burst_tmr >= 0)
1555 val = (val & ~MDIO_OATC14_PLCA_BTMR) |
1556 (plca_cfg->burst_tmr);
1557
1558 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1559 MDIO_OATC14_PLCA_BURST, val);
1560
1561 if (ret < 0)
1562 return ret;
1563 }
1564
1565 // if we need to enable PLCA, do it at the end
1566 if (plca_cfg->enabled > 0) {
1567 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1568 MDIO_OATC14_PLCA_CTRL0,
1569 MDIO_OATC14_PLCA_EN);
1570
1571 if (ret < 0)
1572 return ret;
1573 }
1574
1575 return 0;
1576}
1577EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg);
1578
1579/**
1580 * genphy_c45_plca_get_status - get PLCA status from standard registers
1581 * @phydev: target phy_device struct
1582 * @plca_st: output structure to store the PLCA status
1583 *
1584 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1585 * Management Registers specifications, this function can be used to retrieve
1586 * the current PLCA status information from the standard registers in MMD 31.
1587 */
1588int genphy_c45_plca_get_status(struct phy_device *phydev,
1589 struct phy_plca_status *plca_st)
1590{
1591 int ret;
1592
1593 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS);
1594 if (ret < 0)
1595 return ret;
1596
1597 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST);
1598 return 0;
1599}
1600EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status);
1601
1602/**
1603 * genphy_c45_eee_is_active - get EEE status
1604 * @phydev: target phy_device struct
1605 * @lp: variable to store LP advertised linkmodes
1606 *
1607 * Description: this function will read link partner PHY advertisement
1608 * and compare it to local advertisement to return current EEE state.
1609 */
1610int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp)
1611{
1612 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {};
1613 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
1614 int ret;
1615
1616 if (!phydev->eee_cfg.eee_enabled)
1617 return 0;
1618
1619 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
1620 if (ret)
1621 return ret;
1622
1623 if (lp)
1624 linkmode_copy(lp, tmp_lp);
1625
1626 linkmode_and(common, phydev->advertising_eee, tmp_lp);
1627 if (linkmode_empty(common))
1628 return 0;
1629
1630 return phy_check_valid(phydev->speed, phydev->duplex, common);
1631}
1632EXPORT_SYMBOL(genphy_c45_eee_is_active);
1633
1634/**
1635 * genphy_c45_ethtool_get_eee - get EEE supported and status
1636 * @phydev: target phy_device struct
1637 * @data: ethtool_keee data
1638 *
1639 * Description: it reports the Supported/Advertisement/LP Advertisement
1640 * capabilities.
1641 */
1642int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
1643 struct ethtool_keee *data)
1644{
1645 int ret;
1646
1647 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised);
1648 if (ret < 0)
1649 return ret;
1650
1651 data->eee_active = phydev->eee_active;
1652 linkmode_andnot(data->supported, phydev->supported_eee,
1653 phydev->eee_disabled_modes);
1654 linkmode_copy(data->advertised, phydev->advertising_eee);
1655 return 0;
1656}
1657EXPORT_SYMBOL(genphy_c45_ethtool_get_eee);
1658
1659/**
1660 * genphy_c45_ethtool_set_eee - set EEE supported and status
1661 * @phydev: target phy_device struct
1662 * @data: ethtool_keee data
1663 *
1664 * Description: sets the Supported/Advertisement/LP Advertisement
1665 * capabilities. If eee_enabled is false, no links modes are
1666 * advertised, but the previously advertised link modes are
1667 * retained. This allows EEE to be enabled/disabled in a
1668 * non-destructive way.
1669 * Returns either error code, 0 if there was no change, or positive
1670 * value if there was a change which triggered auto-neg.
1671 */
1672int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
1673 struct ethtool_keee *data)
1674{
1675 int ret;
1676
1677 if (data->eee_enabled) {
1678 unsigned long *adv = data->advertised;
1679
1680 if (!linkmode_empty(adv)) {
1681 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp);
1682
1683 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) {
1684 phydev_warn(phydev, "At least some EEE link modes are not supported.\n");
1685 return -EINVAL;
1686 }
1687
1688 linkmode_andnot(phydev->advertising_eee, adv,
1689 phydev->eee_disabled_modes);
1690 } else if (linkmode_empty(phydev->advertising_eee)) {
1691 phy_advertise_eee_all(phydev);
1692 }
1693 }
1694
1695 ret = genphy_c45_an_config_eee_aneg(phydev);
1696 if (ret > 0) {
1697 ret = phy_restart_aneg(phydev);
1698 if (ret < 0)
1699 return ret;
1700
1701 /* explicitly return 1, otherwise (ret > 0) value will be
1702 * overwritten by phy_restart_aneg().
1703 */
1704 return 1;
1705 }
1706
1707 return ret;
1708}
1709EXPORT_SYMBOL(genphy_c45_ethtool_set_eee);
1710
1711/**
1712 * oatc14_cable_test_get_result_code - Convert hardware cable test status to
1713 * ethtool result code.
1714 * @status: The hardware-reported cable test status
1715 *
1716 * This helper function maps the OATC14 HDD cable test status to the
1717 * corresponding ethtool cable test result code. It provides a translation
1718 * between the device-specific status values and the standardized ethtool
1719 * result codes.
1720 *
1721 * Return:
1722 * * ETHTOOL_A_CABLE_RESULT_CODE_OK - Cable is OK
1723 * * ETHTOOL_A_CABLE_RESULT_CODE_OPEN - Open circuit detected
1724 * * ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT - Short circuit detected
1725 * * ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC - Status not detectable or invalid
1726 */
1727static int oatc14_cable_test_get_result_code(enum oatc14_hdd_status status)
1728{
1729 switch (status) {
1730 case OATC14_HDD_STATUS_CABLE_OK:
1731 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1732 case OATC14_HDD_STATUS_OPEN:
1733 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1734 case OATC14_HDD_STATUS_SHORT:
1735 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1736 case OATC14_HDD_STATUS_NOT_DETECTABLE:
1737 default:
1738 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1739 }
1740}
1741
1742/**
1743 * genphy_c45_oatc14_cable_test_get_status - Get status of OATC14 10Base-T1S
1744 * PHY cable test.
1745 * @phydev: pointer to the PHY device structure
1746 * @finished: pointer to a boolean set true if the test is complete
1747 *
1748 * Retrieves the current status of the OATC14 10Base-T1S PHY cable test.
1749 * This function reads the OATC14 HDD register to determine whether the test
1750 * results are valid and whether the test has finished.
1751 *
1752 * If the test is complete, the function reports the cable test result via
1753 * the ethtool cable test interface using ethnl_cable_test_result(), and then
1754 * clears the test control bit in the PHY register to reset the test state.
1755 *
1756 * Return: 0 on success, or a negative error code on failure (e.g. register
1757 * read/write error).
1758 */
1759int genphy_c45_oatc14_cable_test_get_status(struct phy_device *phydev,
1760 bool *finished)
1761{
1762 int ret;
1763 u8 sts;
1764
1765 *finished = false;
1766
1767 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD);
1768 if (ret < 0)
1769 return ret;
1770
1771 if (!(ret & OATC14_HDD_VALID))
1772 return 0;
1773
1774 *finished = true;
1775
1776 sts = FIELD_GET(OATC14_HDD_SHORT_OPEN_STATUS, ret);
1777
1778 ret = ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1779 oatc14_cable_test_get_result_code(sts));
1780 if (ret)
1781 return ret;
1782
1783 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1784 MDIO_OATC14_HDD, OATC14_HDD_CONTROL);
1785}
1786EXPORT_SYMBOL(genphy_c45_oatc14_cable_test_get_status);
1787
1788/**
1789 * genphy_c45_oatc14_cable_test_start - Start a cable test on an OATC14
1790 * 10Base-T1S PHY.
1791 * @phydev: Pointer to the PHY device structure
1792 *
1793 * This function initiates a cable diagnostic test on a Clause 45 OATC14
1794 * 10Base-T1S capable PHY device. It first reads the PHY’s advanced diagnostic
1795 * capability register to check if High Definition Diagnostics (HDD) mode is
1796 * supported. If the PHY does not report HDD capability, cable testing is not
1797 * supported and the function returns -EOPNOTSUPP.
1798 *
1799 * For PHYs that support HDD, the function sets the appropriate control bits in
1800 * the OATC14_HDD register to enable and start the cable diagnostic test.
1801 *
1802 * Return:
1803 * * 0 on success
1804 * * -EOPNOTSUPP if the PHY does not support HDD capability
1805 * * A negative error code on I/O or register access failures
1806 */
1807int genphy_c45_oatc14_cable_test_start(struct phy_device *phydev)
1808{
1809 int ret;
1810
1811 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_ADFCAP);
1812 if (ret < 0)
1813 return ret;
1814
1815 if (!(ret & OATC14_ADFCAP_HDD_CAPABILITY))
1816 return -EOPNOTSUPP;
1817
1818 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD,
1819 OATC14_HDD_CONTROL);
1820 if (ret)
1821 return ret;
1822
1823 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD);
1824 if (ret < 0)
1825 return ret;
1826
1827 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_HDD,
1828 OATC14_HDD_START_CONTROL);
1829}
1830EXPORT_SYMBOL(genphy_c45_oatc14_cable_test_start);
1831
1832/**
1833 * oatc14_update_sqi_capability - Read and update OATC14 10Base-T1S PHY SQI/SQI+
1834 * capability
1835 * @phydev: Pointer to the PHY device structure
1836 *
1837 * This helper reads the OATC14 ADFCAP capability register to determine whether
1838 * the PHY supports SQI or SQI+ reporting.
1839 *
1840 * SQI+ capability is detected first. The SQI+ field indicates the number of
1841 * valid MSBs (3–8), corresponding to 8–256 SQI+ levels. When present, the
1842 * function stores the number of SQI+ bits and computes the maximum SQI+ value
1843 * as (2^bits - 1).
1844 *
1845 * If SQI+ is not supported, the function checks for basic SQI capability,
1846 * which provides 0–7 SQI levels.
1847 *
1848 * On success, the capability information is stored in
1849 * @phydev->oatc14_sqi_capability and marked as updated.
1850 *
1851 * Return:
1852 * * 0 - capability successfully read and stored
1853 * * -EOPNOTSUPP - SQI/SQI+ not supported by this PHY
1854 * * Negative errno on read failure
1855 */
1856static int oatc14_update_sqi_capability(struct phy_device *phydev)
1857{
1858 u8 bits;
1859 int ret;
1860
1861 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_ADFCAP);
1862 if (ret < 0)
1863 return ret;
1864
1865 /* Check for SQI+ capability
1866 * 0 - SQI+ is not supported
1867 * (3-8) bits for (8-256) SQI+ levels supported
1868 */
1869 bits = FIELD_GET(OATC14_ADFCAP_SQIPLUS_CAPABILITY, ret);
1870 if (bits) {
1871 phydev->oatc14_sqi_capability.sqiplus_bits = bits;
1872 /* Max sqi+ level supported: (2 ^ bits) - 1 */
1873 phydev->oatc14_sqi_capability.sqi_max = BIT(bits) - 1;
1874 goto update_done;
1875 }
1876
1877 /* Check for SQI capability
1878 * 0 - SQI is not supported
1879 * 1 - SQI is supported (0-7 levels)
1880 */
1881 if (ret & OATC14_ADFCAP_SQI_CAPABILITY) {
1882 phydev->oatc14_sqi_capability.sqi_max = OATC14_SQI_MAX_LEVEL;
1883 goto update_done;
1884 }
1885
1886 return -EOPNOTSUPP;
1887
1888update_done:
1889 phydev->oatc14_sqi_capability.updated = true;
1890 return 0;
1891}
1892
1893/**
1894 * genphy_c45_oatc14_get_sqi_max - Get maximum supported SQI or SQI+ level of
1895 * OATC14 10Base-T1S PHY
1896 * @phydev: pointer to the PHY device structure
1897 *
1898 * This function returns the maximum supported Signal Quality Indicator (SQI) or
1899 * SQI+ level. The SQI capability is updated on first invocation if it has not
1900 * already been updated.
1901 *
1902 * Return:
1903 * * Maximum SQI/SQI+ level supported
1904 * * Negative errno on capability read failure
1905 */
1906int genphy_c45_oatc14_get_sqi_max(struct phy_device *phydev)
1907{
1908 int ret;
1909
1910 if (!phydev->oatc14_sqi_capability.updated) {
1911 ret = oatc14_update_sqi_capability(phydev);
1912 if (ret)
1913 return ret;
1914 }
1915
1916 return phydev->oatc14_sqi_capability.sqi_max;
1917}
1918EXPORT_SYMBOL(genphy_c45_oatc14_get_sqi_max);
1919
1920/**
1921 * genphy_c45_oatc14_get_sqi - Get Signal Quality Indicator (SQI) from an OATC14
1922 * 10Base-T1S PHY
1923 * @phydev: pointer to the PHY device structure
1924 *
1925 * This function reads the SQI+ or SQI value from an OATC14-compatible
1926 * 10Base-T1S PHY. If SQI+ capability is supported, the function returns the
1927 * extended SQI+ value; otherwise, it returns the basic SQI value. The SQI
1928 * capability is updated on first invocation if it has not already been updated.
1929 *
1930 * Return:
1931 * * SQI/SQI+ value on success
1932 * * Negative errno on read failure
1933 */
1934int genphy_c45_oatc14_get_sqi(struct phy_device *phydev)
1935{
1936 u8 shift;
1937 int ret;
1938
1939 if (!phydev->oatc14_sqi_capability.updated) {
1940 ret = oatc14_update_sqi_capability(phydev);
1941 if (ret)
1942 return ret;
1943 }
1944
1945 /* Calculate and return SQI+ value if supported */
1946 if (phydev->oatc14_sqi_capability.sqiplus_bits) {
1947 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1948 MDIO_OATC14_DCQ_SQIPLUS);
1949 if (ret < 0)
1950 return ret;
1951
1952 /* SQI+ uses N MSBs out of 8 bits, left-aligned with padding 1's
1953 * Calculate the right-shift needed to isolate the N bits.
1954 */
1955 shift = 8 - phydev->oatc14_sqi_capability.sqiplus_bits;
1956
1957 return (ret & OATC14_DCQ_SQIPLUS_VALUE) >> shift;
1958 }
1959
1960 /* Read and return SQI value if SQI+ capability is not supported */
1961 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_DCQ_SQI);
1962 if (ret < 0)
1963 return ret;
1964
1965 return ret & OATC14_DCQ_SQI_VALUE;
1966}
1967EXPORT_SYMBOL(genphy_c45_oatc14_get_sqi);