linux - drivers/pci/controller/pci-hyperv.c

4224 lines · 116.9 KiB

1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Copyright (c) Microsoft Corporation.
4	*
5	* Author:
6	* Jake Oshins <[email protected]>
7	*
8	* This driver acts as a paravirtual front-end for PCI Express root buses.
9	* When a PCI Express function (either an entire device or an SR-IOV
10	* Virtual Function) is being passed through to the VM, this driver exposes
11	* a new bus to the guest VM. This is modeled as a root PCI bus because
12	* no bridges are being exposed to the VM. In fact, with a "Generation 2"
13	* VM within Hyper-V, there may seem to be no PCI bus at all in the VM
14	* until a device as been exposed using this driver.
15	*
16	* Each root PCI bus has its own PCI domain, which is called "Segment" in
17	* the PCI Firmware Specifications. Thus while each device passed through
18	* to the VM using this front-end will appear at "device 0", the domain will
19	* be unique. Typically, each bus will have one PCI function on it, though
20	* this driver does support more than one.
21	*
22	* In order to map the interrupts from the device through to the guest VM,
23	* this driver also implements an IRQ Domain, which handles interrupts (either
24	* MSI or MSI-X) associated with the functions on the bus. As interrupts are
25	* set up, torn down, or reaffined, this driver communicates with the
26	* underlying hypervisor to adjust the mappings in the I/O MMU so that each
27	* interrupt will be delivered to the correct virtual processor at the right
28	* vector. This driver does not support level-triggered (line-based)
29	* interrupts, and will report that the Interrupt Line register in the
30	* function's configuration space is zero.
31	*
32	* The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
33	* facilities. For instance, the configuration space of a function exposed
34	* by Hyper-V is mapped into a single page of memory space, and the
35	* read and write handlers for config space must be aware of this mechanism.
36	* Similarly, device setup and teardown involves messages sent to and from
37	* the PCI back-end driver in Hyper-V.
38	*/
39
40	#include <linux/kernel.h>
41	#include <linux/module.h>
42	#include <linux/pci.h>
43	#include <linux/pci-ecam.h>
44	#include <linux/delay.h>
45	#include <linux/semaphore.h>
46	#include <linux/irq.h>
47	#include <linux/irqchip/irq-msi-lib.h>
48	#include <linux/msi.h>
49	#include <linux/hyperv.h>
50	#include <linux/refcount.h>
51	#include <linux/irqdomain.h>
52	#include <linux/acpi.h>
53	#include <linux/sizes.h>
54	#include <linux/of_irq.h>
55	#include <asm/mshyperv.h>
56
57	/*
58	* Protocol versions. The low word is the minor version, the high word the
59	* major version.
60	*/
61
62	#define PCI_MAKE_VERSION(major, minor) ((u32)(((major) << 16) \| (minor)))
63	#define PCI_MAJOR_VERSION(version) ((u32)(version) >> 16)
64	#define PCI_MINOR_VERSION(version) ((u32)(version) & 0xff)
65
66	enum pci_protocol_version_t {
67	PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1), /* Win10 */
68	PCI_PROTOCOL_VERSION_1_2 = PCI_MAKE_VERSION(1, 2), /* RS1 */
69	PCI_PROTOCOL_VERSION_1_3 = PCI_MAKE_VERSION(1, 3), /* Vibranium */
70	PCI_PROTOCOL_VERSION_1_4 = PCI_MAKE_VERSION(1, 4), /* WS2022 */
71	};
72
73	#define CPU_AFFINITY_ALL -1ULL
74
75	/*
76	* Supported protocol versions in the order of probing - highest go
77	* first.
78	*/
79	static enum pci_protocol_version_t pci_protocol_versions[] = {
80	PCI_PROTOCOL_VERSION_1_4,
81	PCI_PROTOCOL_VERSION_1_3,
82	PCI_PROTOCOL_VERSION_1_2,
83	PCI_PROTOCOL_VERSION_1_1,
84	};
85
86	#define PCI_CONFIG_MMIO_LENGTH 0x2000
87	#define CFG_PAGE_OFFSET 0x1000
88	#define CFG_PAGE_SIZE (PCI_CONFIG_MMIO_LENGTH - CFG_PAGE_OFFSET)
89
90	#define MAX_SUPPORTED_MSI_MESSAGES 0x400
91
92	#define STATUS_REVISION_MISMATCH 0xC0000059
93
94	/* space for 32bit serial number as string */
95	#define SLOT_NAME_SIZE 11
96
97	/*
98	* Size of requestor for VMbus; the value is based on the observation
99	* that having more than one request outstanding is 'rare', and so 64
100	* should be generous in ensuring that we don't ever run out.
101	*/
102	#define HV_PCI_RQSTOR_SIZE 64
103
104	/*
105	* Message Types
106	*/
107
108	enum pci_message_type {
109	/*
110	* Version 1.1
111	*/
112	PCI_MESSAGE_BASE = 0x42490000,
113	PCI_BUS_RELATIONS = PCI_MESSAGE_BASE + 0,
114	PCI_QUERY_BUS_RELATIONS = PCI_MESSAGE_BASE + 1,
115	PCI_POWER_STATE_CHANGE = PCI_MESSAGE_BASE + 4,
116	PCI_QUERY_RESOURCE_REQUIREMENTS = PCI_MESSAGE_BASE + 5,
117	PCI_QUERY_RESOURCE_RESOURCES = PCI_MESSAGE_BASE + 6,
118	PCI_BUS_D0ENTRY = PCI_MESSAGE_BASE + 7,
119	PCI_BUS_D0EXIT = PCI_MESSAGE_BASE + 8,
120	PCI_READ_BLOCK = PCI_MESSAGE_BASE + 9,
121	PCI_WRITE_BLOCK = PCI_MESSAGE_BASE + 0xA,
122	PCI_EJECT = PCI_MESSAGE_BASE + 0xB,
123	PCI_QUERY_STOP = PCI_MESSAGE_BASE + 0xC,
124	PCI_REENABLE = PCI_MESSAGE_BASE + 0xD,
125	PCI_QUERY_STOP_FAILED = PCI_MESSAGE_BASE + 0xE,
126	PCI_EJECTION_COMPLETE = PCI_MESSAGE_BASE + 0xF,
127	PCI_RESOURCES_ASSIGNED = PCI_MESSAGE_BASE + 0x10,
128	PCI_RESOURCES_RELEASED = PCI_MESSAGE_BASE + 0x11,
129	PCI_INVALIDATE_BLOCK = PCI_MESSAGE_BASE + 0x12,
130	PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
131	PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
132	PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
133	PCI_RESOURCES_ASSIGNED2 = PCI_MESSAGE_BASE + 0x16,
134	PCI_CREATE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x17,
135	PCI_DELETE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x18, /* unused */
136	PCI_BUS_RELATIONS2 = PCI_MESSAGE_BASE + 0x19,
137	PCI_RESOURCES_ASSIGNED3 = PCI_MESSAGE_BASE + 0x1A,
138	PCI_CREATE_INTERRUPT_MESSAGE3 = PCI_MESSAGE_BASE + 0x1B,
139	PCI_MESSAGE_MAXIMUM
140	};
141
142	/*
143	* Structures defining the virtual PCI Express protocol.
144	*/
145
146	union pci_version {
147	struct {
148	u16 minor_version;
149	u16 major_version;
150	} parts;
151	u32 version;
152	} __packed;
153
154	/*
155	* Function numbers are 8-bits wide on Express, as interpreted through ARI,
156	* which is all this driver does. This representation is the one used in
157	* Windows, which is what is expected when sending this back and forth with
158	* the Hyper-V parent partition.
159	*/
160	union win_slot_encoding {
161	struct {
162	u32 dev:5;
163	u32 func:3;
164	u32 reserved:24;
165	} bits;
166	u32 slot;
167	} __packed;
168
169	/*
170	* Pretty much as defined in the PCI Specifications.
171	*/
172	struct pci_function_description {
173	u16 v_id; /* vendor ID */
174	u16 d_id; /* device ID */
175	u8 rev;
176	u8 prog_intf;
177	u8 subclass;
178	u8 base_class;
179	u32 subsystem_id;
180	union win_slot_encoding win_slot;
181	u32 ser; /* serial number */
182	} __packed;
183
184	enum pci_device_description_flags {
185	HV_PCI_DEVICE_FLAG_NONE = 0x0,
186	HV_PCI_DEVICE_FLAG_NUMA_AFFINITY = 0x1,
187	};
188
189	struct pci_function_description2 {
190	u16 v_id; /* vendor ID */
191	u16 d_id; /* device ID */
192	u8 rev;
193	u8 prog_intf;
194	u8 subclass;
195	u8 base_class;
196	u32 subsystem_id;
197	union win_slot_encoding win_slot;
198	u32 ser; /* serial number */
199	u32 flags;
200	u16 virtual_numa_node;
201	u16 reserved;
202	} __packed;
203
204	/**
205	* struct hv_msi_desc
206	* @vector: IDT entry
207	* @delivery_mode: As defined in Intel's Programmer's
208	* Reference Manual, Volume 3, Chapter 8.
209	* @vector_count: Number of contiguous entries in the
210	* Interrupt Descriptor Table that are
211	* occupied by this Message-Signaled
212	* Interrupt. For "MSI", as first defined
213	* in PCI 2.2, this can be between 1 and
214	* 32. For "MSI-X," as first defined in PCI
215	* 3.0, this must be 1, as each MSI-X table
216	* entry would have its own descriptor.
217	* @reserved: Empty space
218	* @cpu_mask: All the target virtual processors.
219	*/
220	struct hv_msi_desc {
221	u8 vector;
222	u8 delivery_mode;
223	u16 vector_count;
224	u32 reserved;
225	u64 cpu_mask;
226	} __packed;
227
228	/**
229	* struct hv_msi_desc2 - 1.2 version of hv_msi_desc
230	* @vector: IDT entry
231	* @delivery_mode: As defined in Intel's Programmer's
232	* Reference Manual, Volume 3, Chapter 8.
233	* @vector_count: Number of contiguous entries in the
234	* Interrupt Descriptor Table that are
235	* occupied by this Message-Signaled
236	* Interrupt. For "MSI", as first defined
237	* in PCI 2.2, this can be between 1 and
238	* 32. For "MSI-X," as first defined in PCI
239	* 3.0, this must be 1, as each MSI-X table
240	* entry would have its own descriptor.
241	* @processor_count: number of bits enabled in array.
242	* @processor_array: All the target virtual processors.
243	*/
244	struct hv_msi_desc2 {
245	u8 vector;
246	u8 delivery_mode;
247	u16 vector_count;
248	u16 processor_count;
249	u16 processor_array[32];
250	} __packed;
251
252	/*
253	* struct hv_msi_desc3 - 1.3 version of hv_msi_desc
254	* Everything is the same as in 'hv_msi_desc2' except that the size of the
255	* 'vector' field is larger to support bigger vector values. For ex: LPI
256	* vectors on ARM.
257	*/
258	struct hv_msi_desc3 {
259	u32 vector;
260	u8 delivery_mode;
261	u8 reserved;
262	u16 vector_count;
263	u16 processor_count;
264	u16 processor_array[32];
265	} __packed;
266
267	/**
268	* struct tran_int_desc
269	* @reserved: unused, padding
270	* @vector_count: same as in hv_msi_desc
271	* @data: This is the "data payload" value that is
272	* written by the device when it generates
273	* a message-signaled interrupt, either MSI
274	* or MSI-X.
275	* @address: This is the address to which the data
276	* payload is written on interrupt
277	* generation.
278	*/
279	struct tran_int_desc {
280	u16 reserved;
281	u16 vector_count;
282	u32 data;
283	u64 address;
284	} __packed;
285
286	/*
287	* A generic message format for virtual PCI.
288	* Specific message formats are defined later in the file.
289	*/
290
291	struct pci_message {
292	u32 type;
293	} __packed;
294
295	struct pci_child_message {
296	struct pci_message message_type;
297	union win_slot_encoding wslot;
298	} __packed;
299
300	struct pci_incoming_message {
301	struct vmpacket_descriptor hdr;
302	struct pci_message message_type;
303	} __packed;
304
305	struct pci_response {
306	struct vmpacket_descriptor hdr;
307	s32 status; /* negative values are failures */
308	} __packed;
309
310	struct pci_packet {
311	void (completion_func)(void context, struct pci_response *resp,
312	int resp_packet_size);
313	void *compl_ctxt;
314	};
315
316	/*
317	* Specific message types supporting the PCI protocol.
318	*/
319
320	/*
321	* Version negotiation message. Sent from the guest to the host.
322	* The guest is free to try different versions until the host
323	* accepts the version.
324	*
325	* pci_version: The protocol version requested.
326	* is_last_attempt: If TRUE, this is the last version guest will request.
327	* reservedz: Reserved field, set to zero.
328	*/
329
330	struct pci_version_request {
331	struct pci_message message_type;
332	u32 protocol_version;
333	} __packed;
334
335	/*
336	* Bus D0 Entry. This is sent from the guest to the host when the virtual
337	* bus (PCI Express port) is ready for action.
338	*/
339
340	struct pci_bus_d0_entry {
341	struct pci_message message_type;
342	u32 reserved;
343	u64 mmio_base;
344	} __packed;
345
346	struct pci_bus_relations {
347	struct pci_incoming_message incoming;
348	u32 device_count;
349	struct pci_function_description func[];
350	} __packed;
351
352	struct pci_bus_relations2 {
353	struct pci_incoming_message incoming;
354	u32 device_count;
355	struct pci_function_description2 func[];
356	} __packed;
357
358	struct pci_q_res_req_response {
359	struct vmpacket_descriptor hdr;
360	s32 status; /* negative values are failures */
361	u32 probed_bar[PCI_STD_NUM_BARS];
362	} __packed;
363
364	struct pci_set_power {
365	struct pci_message message_type;
366	union win_slot_encoding wslot;
367	u32 power_state; /* In Windows terms */
368	u32 reserved;
369	} __packed;
370
371	struct pci_set_power_response {
372	struct vmpacket_descriptor hdr;
373	s32 status; /* negative values are failures */
374	union win_slot_encoding wslot;
375	u32 resultant_state; /* In Windows terms */
376	u32 reserved;
377	} __packed;
378
379	struct pci_resources_assigned {
380	struct pci_message message_type;
381	union win_slot_encoding wslot;
382	u8 memory_range[0x14][6]; /* not used here */
383	u32 msi_descriptors;
384	u32 reserved[4];
385	} __packed;
386
387	struct pci_resources_assigned2 {
388	struct pci_message message_type;
389	union win_slot_encoding wslot;
390	u8 memory_range[0x14][6]; /* not used here */
391	u32 msi_descriptor_count;
392	u8 reserved[70];
393	} __packed;
394
395	struct pci_create_interrupt {
396	struct pci_message message_type;
397	union win_slot_encoding wslot;
398	struct hv_msi_desc int_desc;
399	} __packed;
400
401	struct pci_create_int_response {
402	struct pci_response response;
403	u32 reserved;
404	struct tran_int_desc int_desc;
405	} __packed;
406
407	struct pci_create_interrupt2 {
408	struct pci_message message_type;
409	union win_slot_encoding wslot;
410	struct hv_msi_desc2 int_desc;
411	} __packed;
412
413	struct pci_create_interrupt3 {
414	struct pci_message message_type;
415	union win_slot_encoding wslot;
416	struct hv_msi_desc3 int_desc;
417	} __packed;
418
419	struct pci_delete_interrupt {
420	struct pci_message message_type;
421	union win_slot_encoding wslot;
422	struct tran_int_desc int_desc;
423	} __packed;
424
425	/*
426	* Note: the VM must pass a valid block id, wslot and bytes_requested.
427	*/
428	struct pci_read_block {
429	struct pci_message message_type;
430	u32 block_id;
431	union win_slot_encoding wslot;
432	u32 bytes_requested;
433	} __packed;
434
435	struct pci_read_block_response {
436	struct vmpacket_descriptor hdr;
437	u32 status;
438	u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
439	} __packed;
440
441	/*
442	* Note: the VM must pass a valid block id, wslot and byte_count.
443	*/
444	struct pci_write_block {
445	struct pci_message message_type;
446	u32 block_id;
447	union win_slot_encoding wslot;
448	u32 byte_count;
449	u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
450	} __packed;
451
452	struct pci_dev_inval_block {
453	struct pci_incoming_message incoming;
454	union win_slot_encoding wslot;
455	u64 block_mask;
456	} __packed;
457
458	struct pci_dev_incoming {
459	struct pci_incoming_message incoming;
460	union win_slot_encoding wslot;
461	} __packed;
462
463	struct pci_eject_response {
464	struct pci_message message_type;
465	union win_slot_encoding wslot;
466	u32 status;
467	} __packed;
468
469	static int pci_ring_size = VMBUS_RING_SIZE(SZ_16K);
470
471	/*
472	* Driver specific state.
473	*/
474
475	enum hv_pcibus_state {
476	hv_pcibus_init = 0,
477	hv_pcibus_probed,
478	hv_pcibus_installed,
479	hv_pcibus_removing,
480	hv_pcibus_maximum
481	};
482
483	struct hv_pcibus_device {
484	#ifdef CONFIG_X86
485	struct pci_sysdata sysdata;
486	#elif defined(CONFIG_ARM64)
487	struct pci_config_window sysdata;
488	#endif
489	struct pci_host_bridge *bridge;
490	struct fwnode_handle *fwnode;
491	/* Protocol version negotiated with the host */
492	enum pci_protocol_version_t protocol_version;
493
494	struct mutex state_lock;
495	enum hv_pcibus_state state;
496
497	struct hv_device *hdev;
498	resource_size_t low_mmio_space;
499	resource_size_t high_mmio_space;
500	struct resource *mem_config;
501	struct resource *low_mmio_res;
502	struct resource *high_mmio_res;
503	struct completion *survey_event;
504	spinlock_t config_lock; /* Avoid two threads writing index page */
505	spinlock_t device_list_lock; /* Protect lists below */
506	void __iomem *cfg_addr;
507
508	struct list_head children;
509	struct list_head dr_list;
510
511	struct irq_domain *irq_domain;
512
513	struct workqueue_struct *wq;
514
515	/* Highest slot of child device with resources allocated */
516	int wslot_res_allocated;
517	bool use_calls; /* Use hypercalls to access mmio cfg space */
518	};
519
520	/*
521	* Tracks "Device Relations" messages from the host, which must be both
522	* processed in order and deferred so that they don't run in the context
523	* of the incoming packet callback.
524	*/
525	struct hv_dr_work {
526	struct work_struct wrk;
527	struct hv_pcibus_device *bus;
528	};
529
530	struct hv_pcidev_description {
531	u16 v_id; /* vendor ID */
532	u16 d_id; /* device ID */
533	u8 rev;
534	u8 prog_intf;
535	u8 subclass;
536	u8 base_class;
537	u32 subsystem_id;
538	union win_slot_encoding win_slot;
539	u32 ser; /* serial number */
540	u32 flags;
541	u16 virtual_numa_node;
542	};
543
544	struct hv_dr_state {
545	struct list_head list_entry;
546	u32 device_count;
547	struct hv_pcidev_description func[] __counted_by(device_count);
548	};
549
550	struct hv_pci_dev {
551	/* List protected by pci_rescan_remove_lock */
552	struct list_head list_entry;
553	refcount_t refs;
554	struct pci_slot *pci_slot;
555	struct hv_pcidev_description desc;
556	bool reported_missing;
557	struct hv_pcibus_device *hbus;
558	struct work_struct wrk;
559
560	void (block_invalidate)(void context, u64 block_mask);
561	void *invalidate_context;
562
563	/*
564	* What would be observed if one wrote 0xFFFFFFFF to a BAR and then
565	* read it back, for each of the BAR offsets within config space.
566	*/
567	u32 probed_bar[PCI_STD_NUM_BARS];
568	};
569
570	struct hv_pci_compl {
571	struct completion host_event;
572	s32 completion_status;
573	};
574
575	static void hv_pci_onchannelcallback(void *context);
576
577	#ifdef CONFIG_X86
578	#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED
579	#define HV_MSI_CHIP_FLAGS MSI_CHIP_FLAG_SET_ACK
580
581	static int hv_pci_irqchip_init(void)
582	{
583	return 0;
584	}
585
586	static struct irq_domain *hv_pci_get_root_domain(void)
587	{
588	return x86_vector_domain;
589	}
590
591	static unsigned int hv_msi_get_int_vector(struct irq_data *data)
592	{
593	struct irq_cfg *cfg = irqd_cfg(data);
594
595	return cfg->vector;
596	}
597
598	#define hv_msi_prepare pci_msi_prepare
599
600	/**
601	* hv_irq_retarget_interrupt() - "Unmask" the IRQ by setting its current
602	* affinity.
603	* @data: Describes the IRQ
604	*
605	* Build new a destination for the MSI and make a hypercall to
606	* update the Interrupt Redirection Table. "Device Logical ID"
607	* is built out of this PCI bus's instance GUID and the function
608	* number of the device.
609	*/
610	static void hv_irq_retarget_interrupt(struct irq_data *data)
611	{
612	struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
613	struct hv_retarget_device_interrupt *params;
614	struct tran_int_desc *int_desc;
615	struct hv_pcibus_device *hbus;
616	const struct cpumask *dest;
617	cpumask_var_t tmp;
618	struct pci_bus *pbus;
619	struct pci_dev *pdev;
620	unsigned long flags;
621	u32 var_size = 0;
622	int cpu, nr_bank;
623	u64 res;
624
625	dest = irq_data_get_effective_affinity_mask(data);
626	pdev = msi_desc_to_pci_dev(msi_desc);
627	pbus = pdev->bus;
628	hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
629	int_desc = data->chip_data;
630	if (!int_desc) {
631	dev_warn(&hbus->hdev->device, "%s() can not unmask irq %u\n",
632	__func__, data->irq);
633	return;
634	}
635
636	local_irq_save(flags);
637
638	params = *this_cpu_ptr(hyperv_pcpu_input_arg);
639	memset(params, 0, sizeof(*params));
640	params->partition_id = HV_PARTITION_ID_SELF;
641	params->int_entry.source = HV_INTERRUPT_SOURCE_MSI;
642	params->int_entry.msi_entry.address.as_uint32 = int_desc->address & 0xffffffff;
643	params->int_entry.msi_entry.data.as_uint32 = int_desc->data;
644	params->device_id = (hbus->hdev->dev_instance.b[5] << 24) \|
645	(hbus->hdev->dev_instance.b[4] << 16) \|
646	(hbus->hdev->dev_instance.b[7] << 8) \|
647	(hbus->hdev->dev_instance.b[6] & 0xf8) \|
648	PCI_FUNC(pdev->devfn);
649	params->int_target.vector = hv_msi_get_int_vector(data);
650
651	if (hbus->protocol_version >= PCI_PROTOCOL_VERSION_1_2) {
652	/*
653	* PCI_PROTOCOL_VERSION_1_2 supports the VP_SET version of the
654	* HVCALL_RETARGET_INTERRUPT hypercall, which also coincides
655	* with >64 VP support.
656	* ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED
657	* is not sufficient for this hypercall.
658	*/
659	params->int_target.flags \|=
660	HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET;
661
662	if (!alloc_cpumask_var(&tmp, GFP_ATOMIC)) {
663	res = 1;
664	goto out;
665	}
666
667	cpumask_and(tmp, dest, cpu_online_mask);
668	nr_bank = cpumask_to_vpset(&params->int_target.vp_set, tmp);
669	free_cpumask_var(tmp);
670
671	if (nr_bank <= 0) {
672	res = 1;
673	goto out;
674	}
675
676	/*
677	* var-sized hypercall, var-size starts after vp_mask (thus
678	* vp_set.format does not count, but vp_set.valid_bank_mask
679	* does).
680	*/
681	var_size = 1 + nr_bank;
682	} else {
683	for_each_cpu_and(cpu, dest, cpu_online_mask) {
684	params->int_target.vp_mask \|=
685	(1ULL << hv_cpu_number_to_vp_number(cpu));
686	}
687	}
688
689	res = hv_do_hypercall(HVCALL_RETARGET_INTERRUPT \| (var_size << 17),
690	params, NULL);
691
692	out:
693	local_irq_restore(flags);
694
695	/*
696	* During hibernation, when a CPU is offlined, the kernel tries
697	* to move the interrupt to the remaining CPUs that haven't
698	* been offlined yet. In this case, the below hv_do_hypercall()
699	* always fails since the vmbus channel has been closed:
700	* refer to cpu_disable_common() -> fixup_irqs() ->
701	* irq_migrate_all_off_this_cpu() -> migrate_one_irq().
702	*
703	* Suppress the error message for hibernation because the failure
704	* during hibernation does not matter (at this time all the devices
705	* have been frozen). Note: the correct affinity info is still updated
706	* into the irqdata data structure in migrate_one_irq() ->
707	* irq_do_set_affinity(), so later when the VM resumes,
708	* hv_pci_restore_msi_state() is able to correctly restore the
709	* interrupt with the correct affinity.
710	*/
711	if (!hv_result_success(res) && hbus->state != hv_pcibus_removing)
712	dev_err(&hbus->hdev->device,
713	"%s() failed: %#llx", __func__, res);
714	}
715
716	static void hv_arch_irq_unmask(struct irq_data *data)
717	{
718	if (hv_root_partition())
719	/*
720	* In case of the nested root partition, the nested hypervisor
721	* is taking care of interrupt remapping and thus the
722	* MAP_DEVICE_INTERRUPT hypercall is required instead of
723	* RETARGET_INTERRUPT.
724	*/
725	(void)hv_map_msi_interrupt(data, NULL);
726	else
727	hv_irq_retarget_interrupt(data);
728	}
729	#elif defined(CONFIG_ARM64)
730	/*
731	* SPI vectors to use for vPCI; arch SPIs range is [32, 1019], but leaving a bit
732	* of room at the start to allow for SPIs to be specified through ACPI and
733	* starting with a power of two to satisfy power of 2 multi-MSI requirement.
734	*/
735	#define HV_PCI_MSI_SPI_START 64
736	#define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START)
737	#define DELIVERY_MODE 0
738	#define HV_MSI_CHIP_FLAGS MSI_CHIP_FLAG_SET_EOI
739	#define hv_msi_prepare NULL
740
741	struct hv_pci_chip_data {
742	DECLARE_BITMAP(spi_map, HV_PCI_MSI_SPI_NR);
743	struct mutex map_lock;
744	};
745
746	/* Hyper-V vPCI MSI GIC IRQ domain */
747	static struct irq_domain *hv_msi_gic_irq_domain;
748
749	/* Hyper-V PCI MSI IRQ chip */
750	static struct irq_chip hv_arm64_msi_irq_chip = {
751	.name = "MSI",
752	.irq_set_affinity = irq_chip_set_affinity_parent,
753	.irq_eoi = irq_chip_eoi_parent,
754	.irq_mask = irq_chip_mask_parent,
755	.irq_unmask = irq_chip_unmask_parent
756	};
757
758	static unsigned int hv_msi_get_int_vector(struct irq_data *irqd)
759	{
760	return irqd->parent_data->hwirq;
761	}
762
763	/*
764	* @nr_bm_irqs: Indicates the number of IRQs that were allocated from
765	* the bitmap.
766	* @nr_dom_irqs: Indicates the number of IRQs that were allocated from
767	* the parent domain.
768	*/
769	static void hv_pci_vec_irq_free(struct irq_domain *domain,
770	unsigned int virq,
771	unsigned int nr_bm_irqs,
772	unsigned int nr_dom_irqs)
773	{
774	struct hv_pci_chip_data *chip_data = domain->host_data;
775	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
776	int first = d->hwirq - HV_PCI_MSI_SPI_START;
777	int i;
778
779	mutex_lock(&chip_data->map_lock);
780	bitmap_release_region(chip_data->spi_map,
781	first,
782	get_count_order(nr_bm_irqs));
783	mutex_unlock(&chip_data->map_lock);
784	for (i = 0; i < nr_dom_irqs; i++) {
785	if (i)
786	d = irq_domain_get_irq_data(domain, virq + i);
787	irq_domain_reset_irq_data(d);
788	}
789
790	irq_domain_free_irqs_parent(domain, virq, nr_dom_irqs);
791	}
792
793	static void hv_pci_vec_irq_domain_free(struct irq_domain *domain,
794	unsigned int virq,
795	unsigned int nr_irqs)
796	{
797	hv_pci_vec_irq_free(domain, virq, nr_irqs, nr_irqs);
798	}
799
800	static int hv_pci_vec_alloc_device_irq(struct irq_domain *domain,
801	unsigned int nr_irqs,
802	irq_hw_number_t *hwirq)
803	{
804	struct hv_pci_chip_data *chip_data = domain->host_data;
805	int index;
806
807	/* Find and allocate region from the SPI bitmap */
808	mutex_lock(&chip_data->map_lock);
809	index = bitmap_find_free_region(chip_data->spi_map,
810	HV_PCI_MSI_SPI_NR,
811	get_count_order(nr_irqs));
812	mutex_unlock(&chip_data->map_lock);
813	if (index < 0)
814	return -ENOSPC;
815
816	*hwirq = index + HV_PCI_MSI_SPI_START;
817
818	return 0;
819	}
820
821	static int hv_pci_vec_irq_gic_domain_alloc(struct irq_domain *domain,
822	unsigned int virq,
823	irq_hw_number_t hwirq)
824	{
825	struct irq_fwspec fwspec;
826	struct irq_data *d;
827	int ret;
828
829	fwspec.fwnode = domain->parent->fwnode;
830	if (is_of_node(fwspec.fwnode)) {
831	/* SPI lines for OF translations start at offset 32 */
832	fwspec.param_count = 3;
833	fwspec.param[0] = 0;
834	fwspec.param[1] = hwirq - 32;
835	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
836	} else {
837	fwspec.param_count = 2;
838	fwspec.param[0] = hwirq;
839	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
840	}
841
842	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
843	if (ret)
844	return ret;
845
846	/*
847	* Since the interrupt specifier is not coming from ACPI or DT, the
848	* trigger type will need to be set explicitly. Otherwise, it will be
849	* set to whatever is in the GIC configuration.
850	*/
851	d = irq_domain_get_irq_data(domain->parent, virq);
852
853	return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
854	}
855
856	static int hv_pci_vec_irq_domain_alloc(struct irq_domain *domain,
857	unsigned int virq, unsigned int nr_irqs,
858	void *args)
859	{
860	irq_hw_number_t hwirq;
861	unsigned int i;
862	int ret;
863
864	ret = hv_pci_vec_alloc_device_irq(domain, nr_irqs, &hwirq);
865	if (ret)
866	return ret;
867
868	for (i = 0; i < nr_irqs; i++) {
869	ret = hv_pci_vec_irq_gic_domain_alloc(domain, virq + i,
870	hwirq + i);
871	if (ret) {
872	hv_pci_vec_irq_free(domain, virq, nr_irqs, i);
873	return ret;
874	}
875
876	irq_domain_set_hwirq_and_chip(domain, virq + i,
877	hwirq + i,
878	&hv_arm64_msi_irq_chip,
879	domain->host_data);
880	pr_debug("pID:%d vID:%u\n", (int)(hwirq + i), virq + i);
881	}
882
883	return 0;
884	}
885
886	/*
887	* Pick the first cpu as the irq affinity that can be temporarily used for
888	* composing MSI from the hypervisor. GIC will eventually set the right
889	* affinity for the irq and the 'unmask' will retarget the interrupt to that
890	* cpu.
891	*/
892	static int hv_pci_vec_irq_domain_activate(struct irq_domain *domain,
893	struct irq_data *irqd, bool reserve)
894	{
895	int cpu = cpumask_first(cpu_present_mask);
896
897	irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
898
899	return 0;
900	}
901
902	static const struct irq_domain_ops hv_pci_domain_ops = {
903	.alloc = hv_pci_vec_irq_domain_alloc,
904	.free = hv_pci_vec_irq_domain_free,
905	.activate = hv_pci_vec_irq_domain_activate,
906	};
907
908	#ifdef CONFIG_OF
909
910	static struct irq_domain *hv_pci_of_irq_domain_parent(void)
911	{
912	struct device_node *parent;
913	struct irq_domain *domain;
914
915	parent = of_irq_find_parent(hv_get_vmbus_root_device()->of_node);
916	if (!parent)
917	return NULL;
918	domain = irq_find_host(parent);
919	of_node_put(parent);
920
921	return domain;
922	}
923
924	#endif
925
926	#ifdef CONFIG_ACPI
927
928	static struct irq_domain *hv_pci_acpi_irq_domain_parent(void)
929	{
930	acpi_gsi_domain_disp_fn gsi_domain_disp_fn;
931
932	gsi_domain_disp_fn = acpi_get_gsi_dispatcher();
933	if (!gsi_domain_disp_fn)
934	return NULL;
935	return irq_find_matching_fwnode(gsi_domain_disp_fn(0),
936	DOMAIN_BUS_ANY);
937	}
938
939	#endif
940
941	static int hv_pci_irqchip_init(void)
942	{
943	static struct hv_pci_chip_data *chip_data;
944	struct fwnode_handle *fn = NULL;
945	struct irq_domain *irq_domain_parent = NULL;
946	int ret = -ENOMEM;
947
948	chip_data = kzalloc_obj(*chip_data);
949	if (!chip_data)
950	return ret;
951
952	mutex_init(&chip_data->map_lock);
953	fn = irq_domain_alloc_named_fwnode("hv_vpci_arm64");
954	if (!fn)
955	goto free_chip;
956
957	/*
958	* IRQ domain once enabled, should not be removed since there is no
959	* way to ensure that all the corresponding devices are also gone and
960	* no interrupts will be generated.
961	*/
962	#ifdef CONFIG_ACPI
963	if (!acpi_disabled)
964	irq_domain_parent = hv_pci_acpi_irq_domain_parent();
965	#endif
966	#ifdef CONFIG_OF
967	if (!irq_domain_parent)
968	irq_domain_parent = hv_pci_of_irq_domain_parent();
969	#endif
970	if (!irq_domain_parent) {
971	WARN_ONCE(1, "Invalid firmware configuration for VMBus interrupts\n");
972	ret = -EINVAL;
973	goto free_chip;
974	}
975
976	hv_msi_gic_irq_domain = irq_domain_create_hierarchy(irq_domain_parent, 0,
977	HV_PCI_MSI_SPI_NR,
978	fn, &hv_pci_domain_ops,
979	chip_data);
980
981	if (!hv_msi_gic_irq_domain) {
982	pr_err("Failed to create Hyper-V arm64 vPCI MSI IRQ domain\n");
983	goto free_chip;
984	}
985
986	return 0;
987
988	free_chip:
989	kfree(chip_data);
990	if (fn)
991	irq_domain_free_fwnode(fn);
992
993	return ret;
994	}
995
996	static struct irq_domain *hv_pci_get_root_domain(void)
997	{
998	return hv_msi_gic_irq_domain;
999	}
1000
1001	/*
1002	* SPIs are used for interrupts of PCI devices and SPIs is managed via GICD
1003	* registers which Hyper-V already supports, so no hypercall needed.
1004	*/
1005	static void hv_arch_irq_unmask(struct irq_data *data) { }
1006	#endif /* CONFIG_ARM64 */
1007
1008	/**
1009	* hv_pci_generic_compl() - Invoked for a completion packet
1010	* @context: Set up by the sender of the packet.
1011	* @resp: The response packet
1012	* @resp_packet_size: Size in bytes of the packet
1013	*
1014	* This function is used to trigger an event and report status
1015	* for any message for which the completion packet contains a
1016	* status and nothing else.
1017	*/
1018	static void hv_pci_generic_compl(void context, struct pci_response resp,
1019	int resp_packet_size)
1020	{
1021	struct hv_pci_compl *comp_pkt = context;
1022
1023	comp_pkt->completion_status = resp->status;
1024	complete(&comp_pkt->host_event);
1025	}
1026
1027	static struct hv_pci_dev get_pcichild_wslot(struct hv_pcibus_device hbus,
1028	u32 wslot);
1029
1030	static void get_pcichild(struct hv_pci_dev *hpdev)
1031	{
1032	refcount_inc(&hpdev->refs);
1033	}
1034
1035	static void put_pcichild(struct hv_pci_dev *hpdev)
1036	{
1037	if (refcount_dec_and_test(&hpdev->refs))
1038	kfree(hpdev);
1039	}
1040
1041	/*
1042	* There is no good way to get notified from vmbus_onoffer_rescind(),
1043	* so let's use polling here, since this is not a hot path. If
1044	* wait_for_response() has been polling for 2 minutes
1045	* without either a rescind or completion, add a warning.
1046	*/
1047	#define PCI_RESPONSE_WARN_POLL_COUNT 1200
1048
1049	static int wait_for_response(struct hv_device *hdev,
1050	struct completion *comp,
1051	const char *msg_type)
1052	{
1053	u64 counter = 0;
1054
1055	while (true) {
1056	if (hdev->channel->rescind) {
1057	dev_warn_once(&hdev->device, "The device is gone.\n");
1058	return -ENODEV;
1059	}
1060
1061	counter++;
1062
1063	if (wait_for_completion_timeout(comp, HZ / 10)) {
1064	if (counter > PCI_RESPONSE_WARN_POLL_COUNT)
1065	dev_warn(&hdev->device,
1066	"Late %s completion arrived.\n", msg_type);
1067	break;
1068	}
1069
1070	if (counter == PCI_RESPONSE_WARN_POLL_COUNT) {
1071	dev_err(&hdev->device,
1072	"%s stuck waiting for response, relid = %u\n",
1073	msg_type, hdev->channel->offermsg.child_relid);
1074	}
1075	}
1076
1077	return 0;
1078	}
1079
1080	/**
1081	* devfn_to_wslot() - Convert from Linux PCI slot to Windows
1082	* @devfn: The Linux representation of PCI slot
1083	*
1084	* Windows uses a slightly different representation of PCI slot.
1085	*
1086	* Return: The Windows representation
1087	*/
1088	static u32 devfn_to_wslot(int devfn)
1089	{
1090	union win_slot_encoding wslot;
1091
1092	wslot.slot = 0;
1093	wslot.bits.dev = PCI_SLOT(devfn);
1094	wslot.bits.func = PCI_FUNC(devfn);
1095
1096	return wslot.slot;
1097	}
1098
1099	/**
1100	* wslot_to_devfn() - Convert from Windows PCI slot to Linux
1101	* @wslot: The Windows representation of PCI slot
1102	*
1103	* Windows uses a slightly different representation of PCI slot.
1104	*
1105	* Return: The Linux representation
1106	*/
1107	static int wslot_to_devfn(u32 wslot)
1108	{
1109	union win_slot_encoding slot_no;
1110
1111	slot_no.slot = wslot;
1112	return PCI_DEVFN(slot_no.bits.dev, slot_no.bits.func);
1113	}
1114
1115	static void hv_pci_read_mmio(struct device dev, phys_addr_t gpa, int size, u32 val)
1116	{
1117	struct hv_mmio_read_input *in;
1118	struct hv_mmio_read_output *out;
1119	u64 ret;
1120
1121	/*
1122	* Must be called with interrupts disabled so it is safe
1123	* to use the per-cpu input argument page. Use it for
1124	* both input and output.
1125	*/
1126	in = *this_cpu_ptr(hyperv_pcpu_input_arg);
1127	out = this_cpu_ptr(hyperv_pcpu_input_arg) + sizeof(in);
1128	in->gpa = gpa;
1129	in->size = size;
1130
1131	ret = hv_do_hypercall(HVCALL_MMIO_READ, in, out);
1132	if (hv_result_success(ret)) {
1133	switch (size) {
1134	case 1:
1135	val = (u8 *)(out->data);
1136	break;
1137	case 2:
1138	val = (u16 *)(out->data);
1139	break;
1140	default:
1141	val = (u32 *)(out->data);
1142	break;
1143	}
1144	} else
1145	dev_err(dev, "MMIO read hypercall error %llx addr %llx size %d\n",
1146	ret, gpa, size);
1147	}
1148
1149	static void hv_pci_write_mmio(struct device *dev, phys_addr_t gpa, int size, u32 val)
1150	{
1151	struct hv_mmio_write_input *in;
1152	u64 ret;
1153
1154	/*
1155	* Must be called with interrupts disabled so it is safe
1156	* to use the per-cpu input argument memory.
1157	*/
1158	in = *this_cpu_ptr(hyperv_pcpu_input_arg);
1159	in->gpa = gpa;
1160	in->size = size;
1161	switch (size) {
1162	case 1:
1163	(u8 )(in->data) = val;
1164	break;
1165	case 2:
1166	(u16 )(in->data) = val;
1167	break;
1168	default:
1169	(u32 )(in->data) = val;
1170	break;
1171	}
1172
1173	ret = hv_do_hypercall(HVCALL_MMIO_WRITE, in, NULL);
1174	if (!hv_result_success(ret))
1175	dev_err(dev, "MMIO write hypercall error %llx addr %llx size %d\n",
1176	ret, gpa, size);
1177	}
1178
1179	/*
1180	* PCI Configuration Space for these root PCI buses is implemented as a pair
1181	* of pages in memory-mapped I/O space. Writing to the first page chooses
1182	* the PCI function being written or read. Once the first page has been
1183	* written to, the following page maps in the entire configuration space of
1184	* the function.
1185	*/
1186
1187	/**
1188	* _hv_pcifront_read_config() - Internal PCI config read
1189	* @hpdev: The PCI driver's representation of the device
1190	* @where: Offset within config space
1191	* @size: Size of the transfer
1192	* @val: Pointer to the buffer receiving the data
1193	*/
1194	static void _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where,
1195	int size, u32 *val)
1196	{
1197	struct hv_pcibus_device *hbus = hpdev->hbus;
1198	struct device *dev = &hbus->hdev->device;
1199	int offset = where + CFG_PAGE_OFFSET;
1200	unsigned long flags;
1201
1202	/*
1203	* If the attempt is to read the IDs or the ROM BAR, simulate that.
1204	*/
1205	if (where + size <= PCI_COMMAND) {
1206	memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size);
1207	} else if (where >= PCI_CLASS_REVISION && where + size <=
1208	PCI_CACHE_LINE_SIZE) {
1209	memcpy(val, ((u8 *)&hpdev->desc.rev) + where -
1210	PCI_CLASS_REVISION, size);
1211	} else if (where >= PCI_SUBSYSTEM_VENDOR_ID && where + size <=
1212	PCI_ROM_ADDRESS) {
1213	memcpy(val, (u8 *)&hpdev->desc.subsystem_id + where -
1214	PCI_SUBSYSTEM_VENDOR_ID, size);
1215	} else if (where >= PCI_ROM_ADDRESS && where + size <=
1216	PCI_CAPABILITY_LIST) {
1217	/* ROM BARs are unimplemented */
1218	*val = 0;
1219	} else if ((where >= PCI_INTERRUPT_LINE && where + size <= PCI_INTERRUPT_PIN) \|\|
1220	(where >= PCI_INTERRUPT_PIN && where + size <= PCI_MIN_GNT)) {
1221	/*
1222	* Interrupt Line and Interrupt PIN are hard-wired to zero
1223	* because this front-end only supports message-signaled
1224	* interrupts.
1225	*/
1226	*val = 0;
1227	} else if (where + size <= CFG_PAGE_SIZE) {
1228
1229	spin_lock_irqsave(&hbus->config_lock, flags);
1230	if (hbus->use_calls) {
1231	phys_addr_t addr = hbus->mem_config->start + offset;
1232
1233	hv_pci_write_mmio(dev, hbus->mem_config->start, 4,
1234	hpdev->desc.win_slot.slot);
1235	hv_pci_read_mmio(dev, addr, size, val);
1236	} else {
1237	void __iomem *addr = hbus->cfg_addr + offset;
1238
1239	/* Choose the function to be read. (See comment above) */
1240	writel(hpdev->desc.win_slot.slot, hbus->cfg_addr);
1241	/* Make sure the function was chosen before reading. */
1242	mb();
1243	/* Read from that function's config space. */
1244	switch (size) {
1245	case 1:
1246	*val = readb(addr);
1247	break;
1248	case 2:
1249	*val = readw(addr);
1250	break;
1251	default:
1252	*val = readl(addr);
1253	break;
1254	}
1255	/*
1256	* Make sure the read was done before we release the
1257	* spinlock allowing consecutive reads/writes.
1258	*/
1259	mb();
1260	}
1261	spin_unlock_irqrestore(&hbus->config_lock, flags);
1262	} else {
1263	dev_err(dev, "Attempt to read beyond a function's config space.\n");
1264	}
1265	}
1266
1267	static u16 hv_pcifront_get_vendor_id(struct hv_pci_dev *hpdev)
1268	{
1269	struct hv_pcibus_device *hbus = hpdev->hbus;
1270	struct device *dev = &hbus->hdev->device;
1271	u32 val;
1272	u16 ret;
1273	unsigned long flags;
1274
1275	spin_lock_irqsave(&hbus->config_lock, flags);
1276
1277	if (hbus->use_calls) {
1278	phys_addr_t addr = hbus->mem_config->start +
1279	CFG_PAGE_OFFSET + PCI_VENDOR_ID;
1280
1281	hv_pci_write_mmio(dev, hbus->mem_config->start, 4,
1282	hpdev->desc.win_slot.slot);
1283	hv_pci_read_mmio(dev, addr, 2, &val);
1284	ret = val; /* Truncates to 16 bits */
1285	} else {
1286	void __iomem *addr = hbus->cfg_addr + CFG_PAGE_OFFSET +
1287	PCI_VENDOR_ID;
1288	/* Choose the function to be read. (See comment above) */
1289	writel(hpdev->desc.win_slot.slot, hbus->cfg_addr);
1290	/* Make sure the function was chosen before we start reading. */
1291	mb();
1292	/* Read from that function's config space. */
1293	ret = readw(addr);
1294	/*
1295	* mb() is not required here, because the
1296	* spin_unlock_irqrestore() is a barrier.
1297	*/
1298	}
1299
1300	spin_unlock_irqrestore(&hbus->config_lock, flags);
1301
1302	return ret;
1303	}
1304
1305	/**
1306	* _hv_pcifront_write_config() - Internal PCI config write
1307	* @hpdev: The PCI driver's representation of the device
1308	* @where: Offset within config space
1309	* @size: Size of the transfer
1310	* @val: The data being transferred
1311	*/
1312	static void _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where,
1313	int size, u32 val)
1314	{
1315	struct hv_pcibus_device *hbus = hpdev->hbus;
1316	struct device *dev = &hbus->hdev->device;
1317	int offset = where + CFG_PAGE_OFFSET;
1318	unsigned long flags;
1319
1320	if (where >= PCI_SUBSYSTEM_VENDOR_ID &&
1321	where + size <= PCI_CAPABILITY_LIST) {
1322	/* SSIDs and ROM BARs are read-only */
1323	} else if (where >= PCI_COMMAND && where + size <= CFG_PAGE_SIZE) {
1324	spin_lock_irqsave(&hbus->config_lock, flags);
1325
1326	if (hbus->use_calls) {
1327	phys_addr_t addr = hbus->mem_config->start + offset;
1328
1329	hv_pci_write_mmio(dev, hbus->mem_config->start, 4,
1330	hpdev->desc.win_slot.slot);
1331	hv_pci_write_mmio(dev, addr, size, val);
1332	} else {
1333	void __iomem *addr = hbus->cfg_addr + offset;
1334
1335	/* Choose the function to write. (See comment above) */
1336	writel(hpdev->desc.win_slot.slot, hbus->cfg_addr);
1337	/* Make sure the function was chosen before writing. */
1338	wmb();
1339	/* Write to that function's config space. */
1340	switch (size) {
1341	case 1:
1342	writeb(val, addr);
1343	break;
1344	case 2:
1345	writew(val, addr);
1346	break;
1347	default:
1348	writel(val, addr);
1349	break;
1350	}
1351	/*
1352	* Make sure the write was done before we release the
1353	* spinlock allowing consecutive reads/writes.
1354	*/
1355	mb();
1356	}
1357	spin_unlock_irqrestore(&hbus->config_lock, flags);
1358	} else {
1359	dev_err(dev, "Attempt to write beyond a function's config space.\n");
1360	}
1361	}
1362
1363	/**
1364	* hv_pcifront_read_config() - Read configuration space
1365	* @bus: PCI Bus structure
1366	* @devfn: Device/function
1367	* @where: Offset from base
1368	* @size: Byte/word/dword
1369	* @val: Value to be read
1370	*
1371	* Return: PCIBIOS_SUCCESSFUL on success
1372	* PCIBIOS_DEVICE_NOT_FOUND on failure
1373	*/
1374	static int hv_pcifront_read_config(struct pci_bus *bus, unsigned int devfn,
1375	int where, int size, u32 *val)
1376	{
1377	struct hv_pcibus_device *hbus =
1378	container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
1379	struct hv_pci_dev *hpdev;
1380
1381	hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
1382	if (!hpdev)
1383	return PCIBIOS_DEVICE_NOT_FOUND;
1384
1385	_hv_pcifront_read_config(hpdev, where, size, val);
1386
1387	put_pcichild(hpdev);
1388	return PCIBIOS_SUCCESSFUL;
1389	}
1390
1391	/**
1392	* hv_pcifront_write_config() - Write configuration space
1393	* @bus: PCI Bus structure
1394	* @devfn: Device/function
1395	* @where: Offset from base
1396	* @size: Byte/word/dword
1397	* @val: Value to be written to device
1398	*
1399	* Return: PCIBIOS_SUCCESSFUL on success
1400	* PCIBIOS_DEVICE_NOT_FOUND on failure
1401	*/
1402	static int hv_pcifront_write_config(struct pci_bus *bus, unsigned int devfn,
1403	int where, int size, u32 val)
1404	{
1405	struct hv_pcibus_device *hbus =
1406	container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
1407	struct hv_pci_dev *hpdev;
1408
1409	hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
1410	if (!hpdev)
1411	return PCIBIOS_DEVICE_NOT_FOUND;
1412
1413	_hv_pcifront_write_config(hpdev, where, size, val);
1414
1415	put_pcichild(hpdev);
1416	return PCIBIOS_SUCCESSFUL;
1417	}
1418
1419	/* PCIe operations */
1420	static struct pci_ops hv_pcifront_ops = {
1421	.read = hv_pcifront_read_config,
1422	.write = hv_pcifront_write_config,
1423	};
1424
1425	/*
1426	* Paravirtual backchannel
1427	*
1428	* Hyper-V SR-IOV provides a backchannel mechanism in software for
1429	* communication between a VF driver and a PF driver. These
1430	* "configuration blocks" are similar in concept to PCI configuration space,
1431	* but instead of doing reads and writes in 32-bit chunks through a very slow
1432	* path, packets of up to 128 bytes can be sent or received asynchronously.
1433	*
1434	* Nearly every SR-IOV device contains just such a communications channel in
1435	* hardware, so using this one in software is usually optional. Using the
1436	* software channel, however, allows driver implementers to leverage software
1437	* tools that fuzz the communications channel looking for vulnerabilities.
1438	*
1439	* The usage model for these packets puts the responsibility for reading or
1440	* writing on the VF driver. The VF driver sends a read or a write packet,
1441	* indicating which "block" is being referred to by number.
1442	*
1443	* If the PF driver wishes to initiate communication, it can "invalidate" one or
1444	* more of the first 64 blocks. This invalidation is delivered via a callback
1445	* supplied to the VF driver by this driver.
1446	*
1447	* No protocol is implied, except that supplied by the PF and VF drivers.
1448	*/
1449
1450	struct hv_read_config_compl {
1451	struct hv_pci_compl comp_pkt;
1452	void *buf;
1453	unsigned int len;
1454	unsigned int bytes_returned;
1455	};
1456
1457	/**
1458	* hv_pci_read_config_compl() - Invoked when a response packet
1459	* for a read config block operation arrives.
1460	* @context: Identifies the read config operation
1461	* @resp: The response packet itself
1462	* @resp_packet_size: Size in bytes of the response packet
1463	*/
1464	static void hv_pci_read_config_compl(void context, struct pci_response resp,
1465	int resp_packet_size)
1466	{
1467	struct hv_read_config_compl *comp = context;
1468	struct pci_read_block_response *read_resp =
1469	(struct pci_read_block_response *)resp;
1470	unsigned int data_len, hdr_len;
1471
1472	hdr_len = offsetof(struct pci_read_block_response, bytes);
1473	if (resp_packet_size < hdr_len) {
1474	comp->comp_pkt.completion_status = -1;
1475	goto out;
1476	}
1477
1478	data_len = resp_packet_size - hdr_len;
1479	if (data_len > 0 && read_resp->status == 0) {
1480	comp->bytes_returned = min(comp->len, data_len);
1481	memcpy(comp->buf, read_resp->bytes, comp->bytes_returned);
1482	} else {
1483	comp->bytes_returned = 0;
1484	}
1485
1486	comp->comp_pkt.completion_status = read_resp->status;
1487	out:
1488	complete(&comp->comp_pkt.host_event);
1489	}
1490
1491	/**
1492	* hv_read_config_block() - Sends a read config block request to
1493	* the back-end driver running in the Hyper-V parent partition.
1494	* @pdev: The PCI driver's representation for this device.
1495	* @buf: Buffer into which the config block will be copied.
1496	* @len: Size in bytes of buf.
1497	* @block_id: Identifies the config block which has been requested.
1498	* @bytes_returned: Size which came back from the back-end driver.
1499	*
1500	* Return: 0 on success, -errno on failure
1501	*/
1502	static int hv_read_config_block(struct pci_dev pdev, void buf,
1503	unsigned int len, unsigned int block_id,
1504	unsigned int *bytes_returned)
1505	{
1506	struct hv_pcibus_device *hbus =
1507	container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1508	sysdata);
1509	struct {
1510	struct pci_packet pkt;
1511	char buf[sizeof(struct pci_read_block)];
1512	} pkt;
1513	struct hv_read_config_compl comp_pkt;
1514	struct pci_read_block *read_blk;
1515	int ret;
1516
1517	if (len == 0 \|\| len > HV_CONFIG_BLOCK_SIZE_MAX)
1518	return -EINVAL;
1519
1520	init_completion(&comp_pkt.comp_pkt.host_event);
1521	comp_pkt.buf = buf;
1522	comp_pkt.len = len;
1523
1524	memset(&pkt, 0, sizeof(pkt));
1525	pkt.pkt.completion_func = hv_pci_read_config_compl;
1526	pkt.pkt.compl_ctxt = &comp_pkt;
1527	read_blk = (struct pci_read_block *)pkt.buf;
1528	read_blk->message_type.type = PCI_READ_BLOCK;
1529	read_blk->wslot.slot = devfn_to_wslot(pdev->devfn);
1530	read_blk->block_id = block_id;
1531	read_blk->bytes_requested = len;
1532
1533	ret = vmbus_sendpacket(hbus->hdev->channel, read_blk,
1534	sizeof(*read_blk), (unsigned long)&pkt.pkt,
1535	VM_PKT_DATA_INBAND,
1536	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1537	if (ret)
1538	return ret;
1539
1540	ret = wait_for_response(hbus->hdev, &comp_pkt.comp_pkt.host_event,
1541	"PCI_READ_BLOCK");
1542	if (ret)
1543	return ret;
1544
1545	if (comp_pkt.comp_pkt.completion_status != 0 \|\|
1546	comp_pkt.bytes_returned == 0) {
1547	dev_err(&hbus->hdev->device,
1548	"Read Config Block failed: 0x%x, bytes_returned=%d\n",
1549	comp_pkt.comp_pkt.completion_status,
1550	comp_pkt.bytes_returned);
1551	return -EIO;
1552	}
1553
1554	*bytes_returned = comp_pkt.bytes_returned;
1555	return 0;
1556	}
1557
1558	/**
1559	* hv_pci_write_config_compl() - Invoked when a response packet for a write
1560	* config block operation arrives.
1561	* @context: Identifies the write config operation
1562	* @resp: The response packet itself
1563	* @resp_packet_size: Size in bytes of the response packet
1564	*/
1565	static void hv_pci_write_config_compl(void context, struct pci_response resp,
1566	int resp_packet_size)
1567	{
1568	struct hv_pci_compl *comp_pkt = context;
1569
1570	comp_pkt->completion_status = resp->status;
1571	complete(&comp_pkt->host_event);
1572	}
1573
1574	/**
1575	* hv_write_config_block() - Sends a write config block request to the
1576	* back-end driver running in the Hyper-V parent partition.
1577	* @pdev: The PCI driver's representation for this device.
1578	* @buf: Buffer from which the config block will be copied.
1579	* @len: Size in bytes of buf.
1580	* @block_id: Identifies the config block which is being written.
1581	*
1582	* Return: 0 on success, -errno on failure
1583	*/
1584	static int hv_write_config_block(struct pci_dev pdev, void buf,
1585	unsigned int len, unsigned int block_id)
1586	{
1587	struct hv_pcibus_device *hbus =
1588	container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1589	sysdata);
1590	struct {
1591	struct pci_packet pkt;
1592	char buf[sizeof(struct pci_write_block)];
1593	u32 reserved;
1594	} pkt;
1595	struct hv_pci_compl comp_pkt;
1596	struct pci_write_block *write_blk;
1597	u32 pkt_size;
1598	int ret;
1599
1600	if (len == 0 \|\| len > HV_CONFIG_BLOCK_SIZE_MAX)
1601	return -EINVAL;
1602
1603	init_completion(&comp_pkt.host_event);
1604
1605	memset(&pkt, 0, sizeof(pkt));
1606	pkt.pkt.completion_func = hv_pci_write_config_compl;
1607	pkt.pkt.compl_ctxt = &comp_pkt;
1608	write_blk = (struct pci_write_block *)pkt.buf;
1609	write_blk->message_type.type = PCI_WRITE_BLOCK;
1610	write_blk->wslot.slot = devfn_to_wslot(pdev->devfn);
1611	write_blk->block_id = block_id;
1612	write_blk->byte_count = len;
1613	memcpy(write_blk->bytes, buf, len);
1614	pkt_size = offsetof(struct pci_write_block, bytes) + len;
1615	/*
1616	* This quirk is required on some hosts shipped around 2018, because
1617	* these hosts don't check the pkt_size correctly (new hosts have been
1618	* fixed since early 2019). The quirk is also safe on very old hosts
1619	* and new hosts, because, on them, what really matters is the length
1620	* specified in write_blk->byte_count.
1621	*/
1622	pkt_size += sizeof(pkt.reserved);
1623
1624	ret = vmbus_sendpacket(hbus->hdev->channel, write_blk, pkt_size,
1625	(unsigned long)&pkt.pkt, VM_PKT_DATA_INBAND,
1626	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1627	if (ret)
1628	return ret;
1629
1630	ret = wait_for_response(hbus->hdev, &comp_pkt.host_event,
1631	"PCI_WRITE_BLOCK");
1632	if (ret)
1633	return ret;
1634
1635	if (comp_pkt.completion_status != 0) {
1636	dev_err(&hbus->hdev->device,
1637	"Write Config Block failed: 0x%x\n",
1638	comp_pkt.completion_status);
1639	return -EIO;
1640	}
1641
1642	return 0;
1643	}
1644
1645	/**
1646	* hv_register_block_invalidate() - Invoked when a config block invalidation
1647	* arrives from the back-end driver.
1648	* @pdev: The PCI driver's representation for this device.
1649	* @context: Identifies the device.
1650	* @block_invalidate: Identifies all of the blocks being invalidated.
1651	*
1652	* Return: 0 on success, -errno on failure
1653	*/
1654	static int hv_register_block_invalidate(struct pci_dev pdev, void context,
1655	void (block_invalidate)(void context,
1656	u64 block_mask))
1657	{
1658	struct hv_pcibus_device *hbus =
1659	container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1660	sysdata);
1661	struct hv_pci_dev *hpdev;
1662
1663	hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1664	if (!hpdev)
1665	return -ENODEV;
1666
1667	hpdev->block_invalidate = block_invalidate;
1668	hpdev->invalidate_context = context;
1669
1670	put_pcichild(hpdev);
1671	return 0;
1672
1673	}
1674
1675	/* Interrupt management hooks */
1676	static void hv_int_desc_free(struct hv_pci_dev *hpdev,
1677	struct tran_int_desc *int_desc)
1678	{
1679	struct pci_delete_interrupt *int_pkt;
1680	struct {
1681	struct pci_packet pkt;
1682	u8 buffer[sizeof(struct pci_delete_interrupt)];
1683	} ctxt;
1684
1685	if (!int_desc->vector_count) {
1686	kfree(int_desc);
1687	return;
1688	}
1689	memset(&ctxt, 0, sizeof(ctxt));
1690	int_pkt = (struct pci_delete_interrupt *)ctxt.buffer;
1691	int_pkt->message_type.type =
1692	PCI_DELETE_INTERRUPT_MESSAGE;
1693	int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
1694	int_pkt->int_desc = *int_desc;
1695	vmbus_sendpacket(hpdev->hbus->hdev->channel, int_pkt, sizeof(*int_pkt),
1696	0, VM_PKT_DATA_INBAND, 0);
1697	kfree(int_desc);
1698	}
1699
1700	/**
1701	* hv_msi_free() - Free the MSI.
1702	* @domain: The interrupt domain pointer
1703	* @irq: Identifies the IRQ.
1704	*
1705	* The Hyper-V parent partition and hypervisor are tracking the
1706	* messages that are in use, keeping the interrupt redirection
1707	* table up to date. This callback sends a message that frees
1708	* the IRT entry and related tracking nonsense.
1709	*/
1710	static void hv_msi_free(struct irq_domain *domain, unsigned int irq)
1711	{
1712	struct hv_pcibus_device *hbus;
1713	struct hv_pci_dev *hpdev;
1714	struct pci_dev *pdev;
1715	struct tran_int_desc *int_desc;
1716	struct irq_data *irq_data = irq_domain_get_irq_data(domain, irq);
1717	struct msi_desc *msi = irq_data_get_msi_desc(irq_data);
1718
1719	pdev = msi_desc_to_pci_dev(msi);
1720	hbus = domain->host_data;
1721	int_desc = irq_data_get_irq_chip_data(irq_data);
1722	if (!int_desc)
1723	return;
1724
1725	irq_data->chip_data = NULL;
1726	hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1727	if (!hpdev) {
1728	kfree(int_desc);
1729	return;
1730	}
1731
1732	hv_int_desc_free(hpdev, int_desc);
1733	put_pcichild(hpdev);
1734	}
1735
1736	static void hv_irq_mask(struct irq_data *data)
1737	{
1738	if (data->parent_data->chip->irq_mask)
1739	irq_chip_mask_parent(data);
1740	}
1741
1742	static void hv_irq_unmask(struct irq_data *data)
1743	{
1744	hv_arch_irq_unmask(data);
1745
1746	if (data->parent_data->chip->irq_unmask)
1747	irq_chip_unmask_parent(data);
1748	}
1749
1750	struct compose_comp_ctxt {
1751	struct hv_pci_compl comp_pkt;
1752	struct tran_int_desc int_desc;
1753	};
1754
1755	static void hv_pci_compose_compl(void context, struct pci_response resp,
1756	int resp_packet_size)
1757	{
1758	struct compose_comp_ctxt *comp_pkt = context;
1759	struct pci_create_int_response *int_resp =
1760	(struct pci_create_int_response *)resp;
1761
1762	if (resp_packet_size < sizeof(*int_resp)) {
1763	comp_pkt->comp_pkt.completion_status = -1;
1764	goto out;
1765	}
1766	comp_pkt->comp_pkt.completion_status = resp->status;
1767	comp_pkt->int_desc = int_resp->int_desc;
1768	out:
1769	complete(&comp_pkt->comp_pkt.host_event);
1770	}
1771
1772	static u32 hv_compose_msi_req_v1(
1773	struct pci_create_interrupt *int_pkt,
1774	u32 slot, u8 vector, u16 vector_count)
1775	{
1776	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
1777	int_pkt->wslot.slot = slot;
1778	int_pkt->int_desc.vector = vector;
1779	int_pkt->int_desc.vector_count = vector_count;
1780	int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
1781
1782	/*
1783	* Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
1784	* hv_irq_unmask().
1785	*/
1786	int_pkt->int_desc.cpu_mask = CPU_AFFINITY_ALL;
1787
1788	return sizeof(*int_pkt);
1789	}
1790
1791	/*
1792	* The vCPU selected by hv_compose_multi_msi_req_get_cpu() and
1793	* hv_compose_msi_req_get_cpu() is a "dummy" vCPU because the final vCPU to be
1794	* interrupted is specified later in hv_irq_unmask() and communicated to Hyper-V
1795	* via the HVCALL_RETARGET_INTERRUPT hypercall. But the choice of dummy vCPU is
1796	* not irrelevant because Hyper-V chooses the physical CPU to handle the
1797	* interrupts based on the vCPU specified in message sent to the vPCI VSP in
1798	* hv_compose_msi_msg(). Hyper-V's choice of pCPU is not visible to the guest,
1799	* but assigning too many vPCI device interrupts to the same pCPU can cause a
1800	* performance bottleneck. So we spread out the dummy vCPUs to influence Hyper-V
1801	* to spread out the pCPUs that it selects.
1802	*
1803	* For the single-MSI and MSI-X cases, it's OK for hv_compose_msi_req_get_cpu()
1804	* to always return the same dummy vCPU, because a second call to
1805	* hv_compose_msi_msg() contains the "real" vCPU, causing Hyper-V to choose a
1806	* new pCPU for the interrupt. But for the multi-MSI case, the second call to
1807	* hv_compose_msi_msg() exits without sending a message to the vPCI VSP, so the
1808	* original dummy vCPU is used. This dummy vCPU must be round-robin'ed so that
1809	* the pCPUs are spread out. All interrupts for a multi-MSI device end up using
1810	* the same pCPU, even though the vCPUs will be spread out by later calls
1811	* to hv_irq_unmask(), but that is the best we can do now.
1812	*
1813	* With Hyper-V in Nov 2022, the HVCALL_RETARGET_INTERRUPT hypercall does not
1814	* cause Hyper-V to reselect the pCPU based on the specified vCPU. Such an
1815	* enhancement is planned for a future version. With that enhancement, the
1816	* dummy vCPU selection won't matter, and interrupts for the same multi-MSI
1817	* device will be spread across multiple pCPUs.
1818	*/
1819
1820	/*
1821	* Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten
1822	* by subsequent retarget in hv_irq_unmask().
1823	*/
1824	static int hv_compose_msi_req_get_cpu(const struct cpumask *affinity)
1825	{
1826	return cpumask_first_and(affinity, cpu_online_mask);
1827	}
1828
1829	/*
1830	* Make sure the dummy vCPU values for multi-MSI don't all point to vCPU0.
1831	*/
1832	static int hv_compose_multi_msi_req_get_cpu(void)
1833	{
1834	static DEFINE_SPINLOCK(multi_msi_cpu_lock);
1835
1836	/* -1 means starting with CPU 0 */
1837	static int cpu_next = -1;
1838
1839	unsigned long flags;
1840	int cpu;
1841
1842	spin_lock_irqsave(&multi_msi_cpu_lock, flags);
1843
1844	cpu_next = cpumask_next_wrap(cpu_next, cpu_online_mask);
1845	cpu = cpu_next;
1846
1847	spin_unlock_irqrestore(&multi_msi_cpu_lock, flags);
1848
1849	return cpu;
1850	}
1851
1852	static u32 hv_compose_msi_req_v2(
1853	struct pci_create_interrupt2 *int_pkt, int cpu,
1854	u32 slot, u8 vector, u16 vector_count)
1855	{
1856	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE2;
1857	int_pkt->wslot.slot = slot;
1858	int_pkt->int_desc.vector = vector;
1859	int_pkt->int_desc.vector_count = vector_count;
1860	int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
1861	int_pkt->int_desc.processor_array[0] =
1862	hv_cpu_number_to_vp_number(cpu);
1863	int_pkt->int_desc.processor_count = 1;
1864
1865	return sizeof(*int_pkt);
1866	}
1867
1868	static u32 hv_compose_msi_req_v3(
1869	struct pci_create_interrupt3 *int_pkt, int cpu,
1870	u32 slot, u32 vector, u16 vector_count)
1871	{
1872	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE3;
1873	int_pkt->wslot.slot = slot;
1874	int_pkt->int_desc.vector = vector;
1875	int_pkt->int_desc.reserved = 0;
1876	int_pkt->int_desc.vector_count = vector_count;
1877	int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
1878	int_pkt->int_desc.processor_array[0] =
1879	hv_cpu_number_to_vp_number(cpu);
1880	int_pkt->int_desc.processor_count = 1;
1881
1882	return sizeof(*int_pkt);
1883	}
1884
1885	/**
1886	* hv_compose_msi_msg() - Supplies a valid MSI address/data
1887	* @data: Everything about this MSI
1888	* @msg: Buffer that is filled in by this function
1889	*
1890	* This function unpacks the IRQ looking for target CPU set, IDT
1891	* vector and mode and sends a message to the parent partition
1892	* asking for a mapping for that tuple in this partition. The
1893	* response supplies a data value and address to which that data
1894	* should be written to trigger that interrupt.
1895	*/
1896	static void hv_compose_msi_msg(struct irq_data data, struct msi_msg msg)
1897	{
1898	struct hv_pcibus_device *hbus;
1899	struct vmbus_channel *channel;
1900	struct hv_pci_dev *hpdev;
1901	struct pci_bus *pbus;
1902	struct pci_dev *pdev;
1903	const struct cpumask *dest;
1904	struct compose_comp_ctxt comp;
1905	struct tran_int_desc *int_desc;
1906	struct msi_desc *msi_desc;
1907	/*
1908	* vector_count should be u16: see hv_msi_desc, hv_msi_desc2
1909	* and hv_msi_desc3. vector must be u32: see hv_msi_desc3.
1910	*/
1911	u16 vector_count;
1912	u32 vector;
1913	struct {
1914	struct pci_packet pci_pkt;
1915	union {
1916	struct pci_create_interrupt v1;
1917	struct pci_create_interrupt2 v2;
1918	struct pci_create_interrupt3 v3;
1919	} int_pkts;
1920	} __packed ctxt;
1921	bool multi_msi;
1922	u64 trans_id;
1923	u32 size;
1924	int ret;
1925	int cpu;
1926
1927	msi_desc = irq_data_get_msi_desc(data);
1928	multi_msi = !msi_desc->pci.msi_attrib.is_msix &&
1929	msi_desc->nvec_used > 1;
1930
1931	/* Reuse the previous allocation */
1932	if (data->chip_data && multi_msi) {
1933	int_desc = data->chip_data;
1934	msg->address_hi = int_desc->address >> 32;
1935	msg->address_lo = int_desc->address & 0xffffffff;
1936	msg->data = int_desc->data;
1937	return;
1938	}
1939
1940	pdev = msi_desc_to_pci_dev(msi_desc);
1941	dest = irq_data_get_effective_affinity_mask(data);
1942	pbus = pdev->bus;
1943	hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
1944	channel = hbus->hdev->channel;
1945	hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
1946	if (!hpdev)
1947	goto return_null_message;
1948
1949	/* Free any previous message that might have already been composed. */
1950	if (data->chip_data && !multi_msi) {
1951	int_desc = data->chip_data;
1952	data->chip_data = NULL;
1953	hv_int_desc_free(hpdev, int_desc);
1954	}
1955
1956	int_desc = kzalloc_obj(*int_desc, GFP_ATOMIC);
1957	if (!int_desc)
1958	goto drop_reference;
1959
1960	if (multi_msi) {
1961	/*
1962	* If this is not the first MSI of Multi MSI, we already have
1963	* a mapping. Can exit early.
1964	*/
1965	if (msi_desc->irq != data->irq) {
1966	data->chip_data = int_desc;
1967	int_desc->address = msi_desc->msg.address_lo \|
1968	(u64)msi_desc->msg.address_hi << 32;
1969	int_desc->data = msi_desc->msg.data +
1970	(data->irq - msi_desc->irq);
1971	msg->address_hi = msi_desc->msg.address_hi;
1972	msg->address_lo = msi_desc->msg.address_lo;
1973	msg->data = int_desc->data;
1974	put_pcichild(hpdev);
1975	return;
1976	}
1977	/*
1978	* The vector we select here is a dummy value. The correct
1979	* value gets sent to the hypervisor in unmask(). This needs
1980	* to be aligned with the count, and also not zero. Multi-msi
1981	* is powers of 2 up to 32, so 32 will always work here.
1982	*/
1983	vector = 32;
1984	vector_count = msi_desc->nvec_used;
1985	cpu = hv_compose_multi_msi_req_get_cpu();
1986	} else {
1987	vector = hv_msi_get_int_vector(data);
1988	vector_count = 1;
1989	cpu = hv_compose_msi_req_get_cpu(dest);
1990	}
1991
1992	/*
1993	* hv_compose_msi_req_v1 and v2 are for x86 only, meaning 'vector'
1994	* can't exceed u8. Cast 'vector' down to u8 for v1/v2 explicitly
1995	* for better readability.
1996	*/
1997	memset(&ctxt, 0, sizeof(ctxt));
1998	init_completion(&comp.comp_pkt.host_event);
1999	ctxt.pci_pkt.completion_func = hv_pci_compose_compl;
2000	ctxt.pci_pkt.compl_ctxt = &comp;
2001
2002	switch (hbus->protocol_version) {
2003	case PCI_PROTOCOL_VERSION_1_1:
2004	size = hv_compose_msi_req_v1(&ctxt.int_pkts.v1,
2005	hpdev->desc.win_slot.slot,
2006	(u8)vector,
2007	vector_count);
2008	break;
2009
2010	case PCI_PROTOCOL_VERSION_1_2:
2011	case PCI_PROTOCOL_VERSION_1_3:
2012	size = hv_compose_msi_req_v2(&ctxt.int_pkts.v2,
2013	cpu,
2014	hpdev->desc.win_slot.slot,
2015	(u8)vector,
2016	vector_count);
2017	break;
2018
2019	case PCI_PROTOCOL_VERSION_1_4:
2020	size = hv_compose_msi_req_v3(&ctxt.int_pkts.v3,
2021	cpu,
2022	hpdev->desc.win_slot.slot,
2023	vector,
2024	vector_count);
2025	break;
2026
2027	default:
2028	/* As we only negotiate protocol versions known to this driver,
2029	* this path should never hit. However, this is it not a hot
2030	* path so we print a message to aid future updates.
2031	*/
2032	dev_err(&hbus->hdev->device,
2033	"Unexpected vPCI protocol, update driver.");
2034	goto free_int_desc;
2035	}
2036
2037	ret = vmbus_sendpacket_getid(hpdev->hbus->hdev->channel, &ctxt.int_pkts,
2038	size, (unsigned long)&ctxt.pci_pkt,
2039	&trans_id, VM_PKT_DATA_INBAND,
2040	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2041	if (ret) {
2042	dev_err(&hbus->hdev->device,
2043	"Sending request for interrupt failed: 0x%x",
2044	comp.comp_pkt.completion_status);
2045	goto free_int_desc;
2046	}
2047
2048	/*
2049	* Prevents hv_pci_onchannelcallback() from running concurrently
2050	* in the tasklet.
2051	*/
2052	tasklet_disable_in_atomic(&channel->callback_event);
2053
2054	/*
2055	* Since this function is called with IRQ locks held, can't
2056	* do normal wait for completion; instead poll.
2057	*/
2058	while (!try_wait_for_completion(&comp.comp_pkt.host_event)) {
2059	unsigned long flags;
2060
2061	/* 0xFFFF means an invalid PCI VENDOR ID. */
2062	if (hv_pcifront_get_vendor_id(hpdev) == 0xFFFF) {
2063	dev_err_once(&hbus->hdev->device,
2064	"the device has gone\n");
2065	goto enable_tasklet;
2066	}
2067
2068	/*
2069	* Make sure that the ring buffer data structure doesn't get
2070	* freed while we dereference the ring buffer pointer. Test
2071	* for the channel's onchannel_callback being NULL within a
2072	* sched_lock critical section. See also the inline comments
2073	* in vmbus_reset_channel_cb().
2074	*/
2075	spin_lock_irqsave(&channel->sched_lock, flags);
2076	if (unlikely(channel->onchannel_callback == NULL)) {
2077	spin_unlock_irqrestore(&channel->sched_lock, flags);
2078	goto enable_tasklet;
2079	}
2080	hv_pci_onchannelcallback(hbus);
2081	spin_unlock_irqrestore(&channel->sched_lock, flags);
2082
2083	udelay(100);
2084	}
2085
2086	tasklet_enable(&channel->callback_event);
2087
2088	if (comp.comp_pkt.completion_status < 0) {
2089	dev_err(&hbus->hdev->device,
2090	"Request for interrupt failed: 0x%x",
2091	comp.comp_pkt.completion_status);
2092	goto free_int_desc;
2093	}
2094
2095	/*
2096	* Record the assignment so that this can be unwound later. Using
2097	* irq_set_chip_data() here would be appropriate, but the lock it takes
2098	* is already held.
2099	*/
2100	*int_desc = comp.int_desc;
2101	data->chip_data = int_desc;
2102
2103	/* Pass up the result. */
2104	msg->address_hi = comp.int_desc.address >> 32;
2105	msg->address_lo = comp.int_desc.address & 0xffffffff;
2106	msg->data = comp.int_desc.data;
2107
2108	put_pcichild(hpdev);
2109	return;
2110
2111	enable_tasklet:
2112	tasklet_enable(&channel->callback_event);
2113	/*
2114	* The completion packet on the stack becomes invalid after 'return';
2115	* remove the ID from the VMbus requestor if the identifier is still
2116	* mapped to/associated with the packet. (The identifier could have
2117	* been 're-used', i.e., already removed and (re-)mapped.)
2118	*
2119	* Cf. hv_pci_onchannelcallback().
2120	*/
2121	vmbus_request_addr_match(channel, trans_id, (unsigned long)&ctxt.pci_pkt);
2122	free_int_desc:
2123	kfree(int_desc);
2124	drop_reference:
2125	put_pcichild(hpdev);
2126	return_null_message:
2127	msg->address_hi = 0;
2128	msg->address_lo = 0;
2129	msg->data = 0;
2130	}
2131
2132	static bool hv_pcie_init_dev_msi_info(struct device dev, struct irq_domain domain,
2133	struct irq_domain real_parent, struct msi_domain_info info)
2134	{
2135	struct irq_chip *chip = info->chip;
2136
2137	if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
2138	return false;
2139
2140	info->ops->msi_prepare = hv_msi_prepare;
2141
2142	chip->irq_set_affinity = irq_chip_set_affinity_parent;
2143	chip->irq_retrigger = irq_chip_retrigger_hierarchy;
2144
2145	if (IS_ENABLED(CONFIG_X86))
2146	chip->flags \|= IRQCHIP_MOVE_DEFERRED;
2147
2148	return true;
2149	}
2150
2151	#define HV_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS \| \
2152	MSI_FLAG_USE_DEF_CHIP_OPS \| \
2153	MSI_FLAG_PCI_MSI_MASK_PARENT)
2154	#define HV_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI \| \
2155	MSI_FLAG_PCI_MSIX \| \
2156	MSI_FLAG_PCI_MSIX_ALLOC_DYN \| \
2157	MSI_GENERIC_FLAGS_MASK)
2158
2159	static const struct msi_parent_ops hv_pcie_msi_parent_ops = {
2160	.required_flags = HV_PCIE_MSI_FLAGS_REQUIRED,
2161	.supported_flags = HV_PCIE_MSI_FLAGS_SUPPORTED,
2162	.bus_select_token = DOMAIN_BUS_PCI_MSI,
2163	.chip_flags = HV_MSI_CHIP_FLAGS,
2164	.prefix = "HV-",
2165	.init_dev_msi_info = hv_pcie_init_dev_msi_info,
2166	};
2167
2168	/* HW Interrupt Chip Descriptor */
2169	static struct irq_chip hv_msi_irq_chip = {
2170	.name = "Hyper-V PCIe MSI",
2171	.irq_compose_msi_msg = hv_compose_msi_msg,
2172	.irq_set_affinity = irq_chip_set_affinity_parent,
2173	.irq_ack = irq_chip_ack_parent,
2174	.irq_eoi = irq_chip_eoi_parent,
2175	.irq_mask = hv_irq_mask,
2176	.irq_unmask = hv_irq_unmask,
2177	};
2178
2179	static int hv_pcie_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs,
2180	void *arg)
2181	{
2182	/*
2183	* TODO: Allocating and populating struct tran_int_desc in hv_compose_msi_msg()
2184	* should be moved here.
2185	*/
2186	int ret;
2187
2188	ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, arg);
2189	if (ret < 0)
2190	return ret;
2191
2192	for (int i = 0; i < nr_irqs; i++) {
2193	irq_domain_set_hwirq_and_chip(d, virq + i, 0, &hv_msi_irq_chip, NULL);
2194	if (IS_ENABLED(CONFIG_X86))
2195	__irq_set_handler(virq + i, handle_edge_irq, 0, "edge");
2196	}
2197
2198	return 0;
2199	}
2200
2201	static void hv_pcie_domain_free(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs)
2202	{
2203	for (int i = 0; i < nr_irqs; i++)
2204	hv_msi_free(d, virq + i);
2205
2206	irq_domain_free_irqs_top(d, virq, nr_irqs);
2207	}
2208
2209	static const struct irq_domain_ops hv_pcie_domain_ops = {
2210	.alloc = hv_pcie_domain_alloc,
2211	.free = hv_pcie_domain_free,
2212	};
2213
2214	/**
2215	* hv_pcie_init_irq_domain() - Initialize IRQ domain
2216	* @hbus: The root PCI bus
2217	*
2218	* This function creates an IRQ domain which will be used for
2219	* interrupts from devices that have been passed through. These
2220	* devices only support MSI and MSI-X, not line-based interrupts
2221	* or simulations of line-based interrupts through PCIe's
2222	* fabric-layer messages. Because interrupts are remapped, we
2223	* can support multi-message MSI here.
2224	*
2225	* Return: '0' on success and error value on failure
2226	*/
2227	static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
2228	{
2229	struct irq_domain_info info = {
2230	.fwnode = hbus->fwnode,
2231	.ops = &hv_pcie_domain_ops,
2232	.host_data = hbus,
2233	.parent = hv_pci_get_root_domain(),
2234	};
2235
2236	hbus->irq_domain = msi_create_parent_irq_domain(&info, &hv_pcie_msi_parent_ops);
2237	if (!hbus->irq_domain) {
2238	dev_err(&hbus->hdev->device,
2239	"Failed to build an MSI IRQ domain\n");
2240	return -ENODEV;
2241	}
2242
2243	dev_set_msi_domain(&hbus->bridge->dev, hbus->irq_domain);
2244
2245	return 0;
2246	}
2247
2248	/**
2249	* get_bar_size() - Get the address space consumed by a BAR
2250	* @bar_val: Value that a BAR returned after -1 was written
2251	* to it.
2252	*
2253	* This function returns the size of the BAR, rounded up to 1
2254	* page. It has to be rounded up because the hypervisor's page
2255	* table entry that maps the BAR into the VM can't specify an
2256	* offset within a page. The invariant is that the hypervisor
2257	* must place any BARs of smaller than page length at the
2258	* beginning of a page.
2259	*
2260	* Return: Size in bytes of the consumed MMIO space.
2261	*/
2262	static u64 get_bar_size(u64 bar_val)
2263	{
2264	return round_up((1 + ~(bar_val & PCI_BASE_ADDRESS_MEM_MASK)),
2265	PAGE_SIZE);
2266	}
2267
2268	/**
2269	* survey_child_resources() - Total all MMIO requirements
2270	* @hbus: Root PCI bus, as understood by this driver
2271	*/
2272	static void survey_child_resources(struct hv_pcibus_device *hbus)
2273	{
2274	struct hv_pci_dev *hpdev;
2275	resource_size_t bar_size = 0;
2276	unsigned long flags;
2277	struct completion *event;
2278	u64 bar_val;
2279	int i;
2280
2281	/* If nobody is waiting on the answer, don't compute it. */
2282	event = xchg(&hbus->survey_event, NULL);
2283	if (!event)
2284	return;
2285
2286	/* If the answer has already been computed, go with it. */
2287	if (hbus->low_mmio_space \|\| hbus->high_mmio_space) {
2288	complete(event);
2289	return;
2290	}
2291
2292	spin_lock_irqsave(&hbus->device_list_lock, flags);
2293
2294	/*
2295	* Due to an interesting quirk of the PCI spec, all memory regions
2296	* for a child device are a power of 2 in size and aligned in memory,
2297	* so it's sufficient to just add them up without tracking alignment.
2298	*/
2299	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2300	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
2301	if (hpdev->probed_bar[i] & PCI_BASE_ADDRESS_SPACE_IO)
2302	dev_err(&hbus->hdev->device,
2303	"There's an I/O BAR in this list!\n");
2304
2305	if (hpdev->probed_bar[i] != 0) {
2306	/*
2307	* A probed BAR has all the upper bits set that
2308	* can be changed.
2309	*/
2310
2311	bar_val = hpdev->probed_bar[i];
2312	if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
2313	bar_val \|=
2314	((u64)hpdev->probed_bar[++i] << 32);
2315	else
2316	bar_val \|= 0xffffffff00000000ULL;
2317
2318	bar_size = get_bar_size(bar_val);
2319
2320	if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
2321	hbus->high_mmio_space += bar_size;
2322	else
2323	hbus->low_mmio_space += bar_size;
2324	}
2325	}
2326	}
2327
2328	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2329	complete(event);
2330	}
2331
2332	/**
2333	* prepopulate_bars() - Fill in BARs with defaults
2334	* @hbus: Root PCI bus, as understood by this driver
2335	*
2336	* The core PCI driver code seems much, much happier if the BARs
2337	* for a device have values upon first scan. So fill them in.
2338	* The algorithm below works down from large sizes to small,
2339	* attempting to pack the assignments optimally. The assumption,
2340	* enforced in other parts of the code, is that the beginning of
2341	* the memory-mapped I/O space will be aligned on the largest
2342	* BAR size.
2343	*/
2344	static void prepopulate_bars(struct hv_pcibus_device *hbus)
2345	{
2346	resource_size_t high_size = 0;
2347	resource_size_t low_size = 0;
2348	resource_size_t high_base = 0;
2349	resource_size_t low_base = 0;
2350	resource_size_t bar_size;
2351	struct hv_pci_dev *hpdev;
2352	unsigned long flags;
2353	u64 bar_val;
2354	u32 command;
2355	bool high;
2356	int i;
2357
2358	if (hbus->low_mmio_space) {
2359	low_size = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
2360	low_base = hbus->low_mmio_res->start;
2361	}
2362
2363	if (hbus->high_mmio_space) {
2364	high_size = 1ULL <<
2365	(63 - __builtin_clzll(hbus->high_mmio_space));
2366	high_base = hbus->high_mmio_res->start;
2367	}
2368
2369	spin_lock_irqsave(&hbus->device_list_lock, flags);
2370
2371	/*
2372	* Clear the memory enable bit, in case it's already set. This occurs
2373	* in the suspend path of hibernation, where the device is suspended,
2374	* resumed and suspended again: see hibernation_snapshot() and
2375	* hibernation_platform_enter().
2376	*
2377	* If the memory enable bit is already set, Hyper-V silently ignores
2378	* the below BAR updates, and the related PCI device driver can not
2379	* work, because reading from the device register(s) always returns
2380	* 0xFFFFFFFF (PCI_ERROR_RESPONSE).
2381	*/
2382	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2383	_hv_pcifront_read_config(hpdev, PCI_COMMAND, 2, &command);
2384	command &= ~PCI_COMMAND_MEMORY;
2385	_hv_pcifront_write_config(hpdev, PCI_COMMAND, 2, command);
2386	}
2387
2388	/* Pick addresses for the BARs. */
2389	do {
2390	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2391	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
2392	bar_val = hpdev->probed_bar[i];
2393	if (bar_val == 0)
2394	continue;
2395	high = bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64;
2396	if (high) {
2397	bar_val \|=
2398	((u64)hpdev->probed_bar[i + 1]
2399	<< 32);
2400	} else {
2401	bar_val \|= 0xffffffffULL << 32;
2402	}
2403	bar_size = get_bar_size(bar_val);
2404	if (high) {
2405	if (high_size != bar_size) {
2406	i++;
2407	continue;
2408	}
2409	_hv_pcifront_write_config(hpdev,
2410	PCI_BASE_ADDRESS_0 + (4 * i),
2411	4,
2412	(u32)(high_base & 0xffffff00));
2413	i++;
2414	_hv_pcifront_write_config(hpdev,
2415	PCI_BASE_ADDRESS_0 + (4 * i),
2416	4, (u32)(high_base >> 32));
2417	high_base += bar_size;
2418	} else {
2419	if (low_size != bar_size)
2420	continue;
2421	_hv_pcifront_write_config(hpdev,
2422	PCI_BASE_ADDRESS_0 + (4 * i),
2423	4,
2424	(u32)(low_base & 0xffffff00));
2425	low_base += bar_size;
2426	}
2427	}
2428	if (high_size <= 1 && low_size <= 1) {
2429	/*
2430	* No need to set the PCI_COMMAND_MEMORY bit as
2431	* the core PCI driver doesn't require the bit
2432	* to be pre-set. Actually here we intentionally
2433	* keep the bit off so that the PCI BAR probing
2434	* in the core PCI driver doesn't cause Hyper-V
2435	* to unnecessarily unmap/map the virtual BARs
2436	* from/to the physical BARs multiple times.
2437	* This reduces the VM boot time significantly
2438	* if the BAR sizes are huge.
2439	*/
2440	break;
2441	}
2442	}
2443
2444	high_size >>= 1;
2445	low_size >>= 1;
2446	} while (high_size \|\| low_size);
2447
2448	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2449	}
2450
2451	/*
2452	* Assign entries in sysfs pci slot directory.
2453	*
2454	* Note that this function does not need to lock the children list
2455	* because it is called from pci_devices_present_work which
2456	* is serialized with hv_eject_device_work because they are on the
2457	* same ordered workqueue. Therefore hbus->children list will not change
2458	* even when pci_create_slot sleeps.
2459	*/
2460	static void hv_pci_assign_slots(struct hv_pcibus_device *hbus)
2461	{
2462	struct hv_pci_dev *hpdev;
2463	char name[SLOT_NAME_SIZE];
2464	int slot_nr;
2465
2466	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2467	if (hpdev->pci_slot)
2468	continue;
2469
2470	slot_nr = PCI_SLOT(wslot_to_devfn(hpdev->desc.win_slot.slot));
2471	snprintf(name, SLOT_NAME_SIZE, "%u", hpdev->desc.ser);
2472	hpdev->pci_slot = pci_create_slot(hbus->bridge->bus, slot_nr,
2473	name, NULL);
2474	if (IS_ERR(hpdev->pci_slot)) {
2475	pr_warn("pci_create slot %s failed\n", name);
2476	hpdev->pci_slot = NULL;
2477	}
2478	}
2479	}
2480
2481	/*
2482	* Remove entries in sysfs pci slot directory.
2483	*/
2484	static void hv_pci_remove_slots(struct hv_pcibus_device *hbus)
2485	{
2486	struct hv_pci_dev *hpdev;
2487
2488	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2489	if (!hpdev->pci_slot)
2490	continue;
2491	pci_destroy_slot(hpdev->pci_slot);
2492	hpdev->pci_slot = NULL;
2493	}
2494	}
2495
2496	/*
2497	* Set NUMA node for the devices on the bus
2498	*/
2499	static void hv_pci_assign_numa_node(struct hv_pcibus_device *hbus)
2500	{
2501	struct pci_dev *dev;
2502	struct pci_bus *bus = hbus->bridge->bus;
2503	struct hv_pci_dev *hv_dev;
2504
2505	list_for_each_entry(dev, &bus->devices, bus_list) {
2506	hv_dev = get_pcichild_wslot(hbus, devfn_to_wslot(dev->devfn));
2507	if (!hv_dev)
2508	continue;
2509
2510	/*
2511	* If the Hyper-V host doesn't provide a NUMA node for the
2512	* device, default to node 0. With NUMA_NO_NODE the kernel
2513	* may spread work across NUMA nodes, which degrades
2514	* performance on Hyper-V.
2515	*/
2516	set_dev_node(&dev->dev, 0);
2517
2518	if (hv_dev->desc.flags & HV_PCI_DEVICE_FLAG_NUMA_AFFINITY &&
2519	hv_dev->desc.virtual_numa_node < num_possible_nodes())
2520	/*
2521	* The kernel may boot with some NUMA nodes offline
2522	* (e.g. in a KDUMP kernel) or with NUMA disabled via
2523	* "numa=off". In those cases, adjust the host provided
2524	* NUMA node to a valid NUMA node used by the kernel.
2525	*/
2526	set_dev_node(&dev->dev,
2527	numa_map_to_online_node(
2528	hv_dev->desc.virtual_numa_node));
2529
2530	put_pcichild(hv_dev);
2531	}
2532	}
2533
2534	/**
2535	* create_root_hv_pci_bus() - Expose a new root PCI bus
2536	* @hbus: Root PCI bus, as understood by this driver
2537	*
2538	* Return: 0 on success, -errno on failure
2539	*/
2540	static int create_root_hv_pci_bus(struct hv_pcibus_device *hbus)
2541	{
2542	int error;
2543	struct pci_host_bridge *bridge = hbus->bridge;
2544
2545	bridge->dev.parent = &hbus->hdev->device;
2546	bridge->sysdata = &hbus->sysdata;
2547	bridge->ops = &hv_pcifront_ops;
2548
2549	error = pci_scan_root_bus_bridge(bridge);
2550	if (error)
2551	return error;
2552
2553	pci_lock_rescan_remove();
2554	hv_pci_assign_numa_node(hbus);
2555	pci_bus_assign_resources(bridge->bus);
2556	hv_pci_assign_slots(hbus);
2557	pci_bus_add_devices(bridge->bus);
2558	pci_unlock_rescan_remove();
2559	hbus->state = hv_pcibus_installed;
2560	return 0;
2561	}
2562
2563	struct q_res_req_compl {
2564	struct completion host_event;
2565	struct hv_pci_dev *hpdev;
2566	};
2567
2568	/**
2569	* q_resource_requirements() - Query Resource Requirements
2570	* @context: The completion context.
2571	* @resp: The response that came from the host.
2572	* @resp_packet_size: The size in bytes of resp.
2573	*
2574	* This function is invoked on completion of a Query Resource
2575	* Requirements packet.
2576	*/
2577	static void q_resource_requirements(void context, struct pci_response resp,
2578	int resp_packet_size)
2579	{
2580	struct q_res_req_compl *completion = context;
2581	struct pci_q_res_req_response *q_res_req =
2582	(struct pci_q_res_req_response *)resp;
2583	s32 status;
2584	int i;
2585
2586	status = (resp_packet_size < sizeof(*q_res_req)) ? -1 : resp->status;
2587	if (status < 0) {
2588	dev_err(&completion->hpdev->hbus->hdev->device,
2589	"query resource requirements failed: %x\n",
2590	status);
2591	} else {
2592	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
2593	completion->hpdev->probed_bar[i] =
2594	q_res_req->probed_bar[i];
2595	}
2596	}
2597
2598	complete(&completion->host_event);
2599	}
2600
2601	/**
2602	* new_pcichild_device() - Create a new child device
2603	* @hbus: The internal struct tracking this root PCI bus.
2604	* @desc: The information supplied so far from the host
2605	* about the device.
2606	*
2607	* This function creates the tracking structure for a new child
2608	* device and kicks off the process of figuring out what it is.
2609	*
2610	* Return: Pointer to the new tracking struct
2611	*/
2612	static struct hv_pci_dev new_pcichild_device(struct hv_pcibus_device hbus,
2613	struct hv_pcidev_description *desc)
2614	{
2615	struct hv_pci_dev *hpdev;
2616	struct pci_child_message *res_req;
2617	struct q_res_req_compl comp_pkt;
2618	struct {
2619	struct pci_packet init_packet;
2620	u8 buffer[sizeof(struct pci_child_message)];
2621	} pkt;
2622	unsigned long flags;
2623	int ret;
2624
2625	hpdev = kzalloc_obj(*hpdev);
2626	if (!hpdev)
2627	return NULL;
2628
2629	hpdev->hbus = hbus;
2630
2631	memset(&pkt, 0, sizeof(pkt));
2632	init_completion(&comp_pkt.host_event);
2633	comp_pkt.hpdev = hpdev;
2634	pkt.init_packet.compl_ctxt = &comp_pkt;
2635	pkt.init_packet.completion_func = q_resource_requirements;
2636	res_req = (struct pci_child_message *)pkt.buffer;
2637	res_req->message_type.type = PCI_QUERY_RESOURCE_REQUIREMENTS;
2638	res_req->wslot.slot = desc->win_slot.slot;
2639
2640	ret = vmbus_sendpacket(hbus->hdev->channel, res_req,
2641	sizeof(struct pci_child_message),
2642	(unsigned long)&pkt.init_packet,
2643	VM_PKT_DATA_INBAND,
2644	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2645	if (ret)
2646	goto error;
2647
2648	if (wait_for_response(hbus->hdev, &comp_pkt.host_event,
2649	"PCI_QUERY_RESOURCE_REQUIREMENTS"))
2650	goto error;
2651
2652	hpdev->desc = *desc;
2653	refcount_set(&hpdev->refs, 1);
2654	get_pcichild(hpdev);
2655	spin_lock_irqsave(&hbus->device_list_lock, flags);
2656
2657	list_add_tail(&hpdev->list_entry, &hbus->children);
2658	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2659	return hpdev;
2660
2661	error:
2662	kfree(hpdev);
2663	return NULL;
2664	}
2665
2666	/**
2667	* get_pcichild_wslot() - Find device from slot
2668	* @hbus: Root PCI bus, as understood by this driver
2669	* @wslot: Location on the bus
2670	*
2671	* This function looks up a PCI device and returns the internal
2672	* representation of it. It acquires a reference on it, so that
2673	* the device won't be deleted while somebody is using it. The
2674	* caller is responsible for calling put_pcichild() to release
2675	* this reference.
2676	*
2677	* Return: Internal representation of a PCI device
2678	*/
2679	static struct hv_pci_dev get_pcichild_wslot(struct hv_pcibus_device hbus,
2680	u32 wslot)
2681	{
2682	unsigned long flags;
2683	struct hv_pci_dev iter, hpdev = NULL;
2684
2685	spin_lock_irqsave(&hbus->device_list_lock, flags);
2686	list_for_each_entry(iter, &hbus->children, list_entry) {
2687	if (iter->desc.win_slot.slot == wslot) {
2688	hpdev = iter;
2689	get_pcichild(hpdev);
2690	break;
2691	}
2692	}
2693	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2694
2695	return hpdev;
2696	}
2697
2698	/**
2699	* pci_devices_present_work() - Handle new list of child devices
2700	* @work: Work struct embedded in struct hv_dr_work
2701	*
2702	* "Bus Relations" is the Windows term for "children of this
2703	* bus." The terminology is preserved here for people trying to
2704	* debug the interaction between Hyper-V and Linux. This
2705	* function is called when the parent partition reports a list
2706	* of functions that should be observed under this PCI Express
2707	* port (bus).
2708	*
2709	* This function updates the list, and must tolerate being
2710	* called multiple times with the same information. The typical
2711	* number of child devices is one, with very atypical cases
2712	* involving three or four, so the algorithms used here can be
2713	* simple and inefficient.
2714	*
2715	* It must also treat the omission of a previously observed device as
2716	* notification that the device no longer exists.
2717	*
2718	* Note that this function is serialized with hv_eject_device_work(),
2719	* because both are pushed to the ordered workqueue hbus->wq.
2720	*/
2721	static void pci_devices_present_work(struct work_struct *work)
2722	{
2723	u32 child_no;
2724	bool found;
2725	struct hv_pcidev_description *new_desc;
2726	struct hv_pci_dev *hpdev;
2727	struct hv_pcibus_device *hbus;
2728	struct list_head removed;
2729	struct hv_dr_work *dr_wrk;
2730	struct hv_dr_state *dr = NULL;
2731	unsigned long flags;
2732
2733	dr_wrk = container_of(work, struct hv_dr_work, wrk);
2734	hbus = dr_wrk->bus;
2735	kfree(dr_wrk);
2736
2737	INIT_LIST_HEAD(&removed);
2738
2739	/* Pull this off the queue and process it if it was the last one. */
2740	spin_lock_irqsave(&hbus->device_list_lock, flags);
2741	while (!list_empty(&hbus->dr_list)) {
2742	dr = list_first_entry(&hbus->dr_list, struct hv_dr_state,
2743	list_entry);
2744	list_del(&dr->list_entry);
2745
2746	/* Throw this away if the list still has stuff in it. */
2747	if (!list_empty(&hbus->dr_list)) {
2748	kfree(dr);
2749	continue;
2750	}
2751	}
2752	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2753
2754	if (!dr)
2755	return;
2756
2757	mutex_lock(&hbus->state_lock);
2758
2759	/* First, mark all existing children as reported missing. */
2760	spin_lock_irqsave(&hbus->device_list_lock, flags);
2761	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2762	hpdev->reported_missing = true;
2763	}
2764	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2765
2766	/* Next, add back any reported devices. */
2767	for (child_no = 0; child_no < dr->device_count; child_no++) {
2768	found = false;
2769	new_desc = &dr->func[child_no];
2770
2771	spin_lock_irqsave(&hbus->device_list_lock, flags);
2772	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2773	if ((hpdev->desc.win_slot.slot == new_desc->win_slot.slot) &&
2774	(hpdev->desc.v_id == new_desc->v_id) &&
2775	(hpdev->desc.d_id == new_desc->d_id) &&
2776	(hpdev->desc.ser == new_desc->ser)) {
2777	hpdev->reported_missing = false;
2778	found = true;
2779	}
2780	}
2781	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2782
2783	if (!found) {
2784	hpdev = new_pcichild_device(hbus, new_desc);
2785	if (!hpdev)
2786	dev_err(&hbus->hdev->device,
2787	"couldn't record a child device.\n");
2788	}
2789	}
2790
2791	/* Move missing children to a list on the stack. */
2792	spin_lock_irqsave(&hbus->device_list_lock, flags);
2793	do {
2794	found = false;
2795	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2796	if (hpdev->reported_missing) {
2797	found = true;
2798	put_pcichild(hpdev);
2799	list_move_tail(&hpdev->list_entry, &removed);
2800	break;
2801	}
2802	}
2803	} while (found);
2804	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2805
2806	/* Delete everything that should no longer exist. */
2807	while (!list_empty(&removed)) {
2808	hpdev = list_first_entry(&removed, struct hv_pci_dev,
2809	list_entry);
2810	list_del(&hpdev->list_entry);
2811
2812	if (hpdev->pci_slot)
2813	pci_destroy_slot(hpdev->pci_slot);
2814
2815	put_pcichild(hpdev);
2816	}
2817
2818	switch (hbus->state) {
2819	case hv_pcibus_installed:
2820	/*
2821	* Tell the core to rescan bus
2822	* because there may have been changes.
2823	*/
2824	pci_lock_rescan_remove();
2825	pci_scan_child_bus(hbus->bridge->bus);
2826	hv_pci_assign_numa_node(hbus);
2827	hv_pci_assign_slots(hbus);
2828	pci_unlock_rescan_remove();
2829	break;
2830
2831	case hv_pcibus_init:
2832	case hv_pcibus_probed:
2833	survey_child_resources(hbus);
2834	break;
2835
2836	default:
2837	break;
2838	}
2839
2840	mutex_unlock(&hbus->state_lock);
2841
2842	kfree(dr);
2843	}
2844
2845	/**
2846	* hv_pci_start_relations_work() - Queue work to start device discovery
2847	* @hbus: Root PCI bus, as understood by this driver
2848	* @dr: The list of children returned from host
2849	*
2850	* Return: 0 on success, -errno on failure
2851	*/
2852	static int hv_pci_start_relations_work(struct hv_pcibus_device *hbus,
2853	struct hv_dr_state *dr)
2854	{
2855	struct hv_dr_work *dr_wrk;
2856	unsigned long flags;
2857	bool pending_dr;
2858
2859	if (hbus->state == hv_pcibus_removing) {
2860	dev_info(&hbus->hdev->device,
2861	"PCI VMBus BUS_RELATIONS: ignored\n");
2862	return -ENOENT;
2863	}
2864
2865	dr_wrk = kzalloc_obj(*dr_wrk, GFP_NOWAIT);
2866	if (!dr_wrk)
2867	return -ENOMEM;
2868
2869	INIT_WORK(&dr_wrk->wrk, pci_devices_present_work);
2870	dr_wrk->bus = hbus;
2871
2872	spin_lock_irqsave(&hbus->device_list_lock, flags);
2873	/*
2874	* If pending_dr is true, we have already queued a work,
2875	* which will see the new dr. Otherwise, we need to
2876	* queue a new work.
2877	*/
2878	pending_dr = !list_empty(&hbus->dr_list);
2879	list_add_tail(&dr->list_entry, &hbus->dr_list);
2880	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
2881
2882	if (pending_dr)
2883	kfree(dr_wrk);
2884	else
2885	queue_work(hbus->wq, &dr_wrk->wrk);
2886
2887	return 0;
2888	}
2889
2890	/**
2891	* hv_pci_devices_present() - Handle list of new children
2892	* @hbus: Root PCI bus, as understood by this driver
2893	* @relations: Packet from host listing children
2894	*
2895	* Process a new list of devices on the bus. The list of devices is
2896	* discovered by VSP and sent to us via VSP message PCI_BUS_RELATIONS,
2897	* whenever a new list of devices for this bus appears.
2898	*/
2899	static void hv_pci_devices_present(struct hv_pcibus_device *hbus,
2900	struct pci_bus_relations *relations)
2901	{
2902	struct hv_dr_state *dr;
2903	int i;
2904
2905	dr = kzalloc_flex(*dr, func, relations->device_count, GFP_NOWAIT);
2906	if (!dr)
2907	return;
2908
2909	dr->device_count = relations->device_count;
2910	for (i = 0; i < dr->device_count; i++) {
2911	dr->func[i].v_id = relations->func[i].v_id;
2912	dr->func[i].d_id = relations->func[i].d_id;
2913	dr->func[i].rev = relations->func[i].rev;
2914	dr->func[i].prog_intf = relations->func[i].prog_intf;
2915	dr->func[i].subclass = relations->func[i].subclass;
2916	dr->func[i].base_class = relations->func[i].base_class;
2917	dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2918	dr->func[i].win_slot = relations->func[i].win_slot;
2919	dr->func[i].ser = relations->func[i].ser;
2920	}
2921
2922	if (hv_pci_start_relations_work(hbus, dr))
2923	kfree(dr);
2924	}
2925
2926	/**
2927	* hv_pci_devices_present2() - Handle list of new children
2928	* @hbus: Root PCI bus, as understood by this driver
2929	* @relations: Packet from host listing children
2930	*
2931	* This function is the v2 version of hv_pci_devices_present()
2932	*/
2933	static void hv_pci_devices_present2(struct hv_pcibus_device *hbus,
2934	struct pci_bus_relations2 *relations)
2935	{
2936	struct hv_dr_state *dr;
2937	int i;
2938
2939	dr = kzalloc_flex(*dr, func, relations->device_count, GFP_NOWAIT);
2940	if (!dr)
2941	return;
2942
2943	dr->device_count = relations->device_count;
2944	for (i = 0; i < dr->device_count; i++) {
2945	dr->func[i].v_id = relations->func[i].v_id;
2946	dr->func[i].d_id = relations->func[i].d_id;
2947	dr->func[i].rev = relations->func[i].rev;
2948	dr->func[i].prog_intf = relations->func[i].prog_intf;
2949	dr->func[i].subclass = relations->func[i].subclass;
2950	dr->func[i].base_class = relations->func[i].base_class;
2951	dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2952	dr->func[i].win_slot = relations->func[i].win_slot;
2953	dr->func[i].ser = relations->func[i].ser;
2954	dr->func[i].flags = relations->func[i].flags;
2955	dr->func[i].virtual_numa_node =
2956	relations->func[i].virtual_numa_node;
2957	}
2958
2959	if (hv_pci_start_relations_work(hbus, dr))
2960	kfree(dr);
2961	}
2962
2963	/**
2964	* hv_eject_device_work() - Asynchronously handles ejection
2965	* @work: Work struct embedded in internal device struct
2966	*
2967	* This function handles ejecting a device. Windows will
2968	* attempt to gracefully eject a device, waiting 60 seconds to
2969	* hear back from the guest OS that this completed successfully.
2970	* If this timer expires, the device will be forcibly removed.
2971	*/
2972	static void hv_eject_device_work(struct work_struct *work)
2973	{
2974	struct pci_eject_response *ejct_pkt;
2975	struct hv_pcibus_device *hbus;
2976	struct hv_pci_dev *hpdev;
2977	struct pci_dev *pdev;
2978	unsigned long flags;
2979	int wslot;
2980	struct {
2981	struct pci_packet pkt;
2982	u8 buffer[sizeof(struct pci_eject_response)];
2983	} ctxt;
2984
2985	hpdev = container_of(work, struct hv_pci_dev, wrk);
2986	hbus = hpdev->hbus;
2987
2988	mutex_lock(&hbus->state_lock);
2989
2990	/*
2991	* Ejection can come before or after the PCI bus has been set up, so
2992	* attempt to find it and tear down the bus state, if it exists. This
2993	* must be done without constructs like pci_domain_nr(hbus->bridge->bus)
2994	* because hbus->bridge->bus may not exist yet.
2995	*/
2996	wslot = wslot_to_devfn(hpdev->desc.win_slot.slot);
2997	pdev = pci_get_domain_bus_and_slot(hbus->bridge->domain_nr, 0, wslot);
2998	if (pdev) {
2999	pci_lock_rescan_remove();
3000	pci_stop_and_remove_bus_device(pdev);
3001	pci_dev_put(pdev);
3002	pci_unlock_rescan_remove();
3003	}
3004
3005	spin_lock_irqsave(&hbus->device_list_lock, flags);
3006	list_del(&hpdev->list_entry);
3007	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
3008
3009	if (hpdev->pci_slot)
3010	pci_destroy_slot(hpdev->pci_slot);
3011
3012	memset(&ctxt, 0, sizeof(ctxt));
3013	ejct_pkt = (struct pci_eject_response *)ctxt.buffer;
3014	ejct_pkt->message_type.type = PCI_EJECTION_COMPLETE;
3015	ejct_pkt->wslot.slot = hpdev->desc.win_slot.slot;
3016	vmbus_sendpacket(hbus->hdev->channel, ejct_pkt,
3017	sizeof(*ejct_pkt), 0,
3018	VM_PKT_DATA_INBAND, 0);
3019
3020	/* For the get_pcichild() in hv_pci_eject_device() */
3021	put_pcichild(hpdev);
3022	/* For the two refs got in new_pcichild_device() */
3023	put_pcichild(hpdev);
3024	put_pcichild(hpdev);
3025	/* hpdev has been freed. Do not use it any more. */
3026
3027	mutex_unlock(&hbus->state_lock);
3028	}
3029
3030	/**
3031	* hv_pci_eject_device() - Handles device ejection
3032	* @hpdev: Internal device tracking struct
3033	*
3034	* This function is invoked when an ejection packet arrives. It
3035	* just schedules work so that we don't re-enter the packet
3036	* delivery code handling the ejection.
3037	*/
3038	static void hv_pci_eject_device(struct hv_pci_dev *hpdev)
3039	{
3040	struct hv_pcibus_device *hbus = hpdev->hbus;
3041	struct hv_device *hdev = hbus->hdev;
3042
3043	if (hbus->state == hv_pcibus_removing) {
3044	dev_info(&hdev->device, "PCI VMBus EJECT: ignored\n");
3045	return;
3046	}
3047
3048	get_pcichild(hpdev);
3049	INIT_WORK(&hpdev->wrk, hv_eject_device_work);
3050	queue_work(hbus->wq, &hpdev->wrk);
3051	}
3052
3053	/**
3054	* hv_pci_onchannelcallback() - Handles incoming packets
3055	* @context: Internal bus tracking struct
3056	*
3057	* This function is invoked whenever the host sends a packet to
3058	* this channel (which is private to this root PCI bus).
3059	*/
3060	static void hv_pci_onchannelcallback(void *context)
3061	{
3062	const int packet_size = 0x100;
3063	int ret;
3064	struct hv_pcibus_device *hbus = context;
3065	struct vmbus_channel *chan = hbus->hdev->channel;
3066	u32 bytes_recvd;
3067	u64 req_id, req_addr;
3068	struct vmpacket_descriptor *desc;
3069	unsigned char *buffer;
3070	int bufferlen = packet_size;
3071	struct pci_packet *comp_packet;
3072	struct pci_response *response;
3073	struct pci_incoming_message *new_message;
3074	struct pci_bus_relations *bus_rel;
3075	struct pci_bus_relations2 *bus_rel2;
3076	struct pci_dev_inval_block *inval;
3077	struct pci_dev_incoming *dev_message;
3078	struct hv_pci_dev *hpdev;
3079	unsigned long flags;
3080
3081	buffer = kmalloc(bufferlen, GFP_ATOMIC);
3082	if (!buffer)
3083	return;
3084
3085	while (1) {
3086	ret = vmbus_recvpacket_raw(chan, buffer, bufferlen,
3087	&bytes_recvd, &req_id);
3088
3089	if (ret == -ENOBUFS) {
3090	kfree(buffer);
3091	/* Handle large packet */
3092	bufferlen = bytes_recvd;
3093	buffer = kmalloc(bytes_recvd, GFP_ATOMIC);
3094	if (!buffer)
3095	return;
3096	continue;
3097	}
3098
3099	/* Zero length indicates there are no more packets. */
3100	if (ret \|\| !bytes_recvd)
3101	break;
3102
3103	/*
3104	* All incoming packets must be at least as large as a
3105	* response.
3106	*/
3107	if (bytes_recvd <= sizeof(struct pci_response))
3108	continue;
3109	desc = (struct vmpacket_descriptor *)buffer;
3110
3111	switch (desc->type) {
3112	case VM_PKT_COMP:
3113
3114	lock_requestor(chan, flags);
3115	req_addr = __vmbus_request_addr_match(chan, req_id,
3116	VMBUS_RQST_ADDR_ANY);
3117	if (req_addr == VMBUS_RQST_ERROR) {
3118	unlock_requestor(chan, flags);
3119	dev_err(&hbus->hdev->device,
3120	"Invalid transaction ID %llx\n",
3121	req_id);
3122	break;
3123	}
3124	comp_packet = (struct pci_packet *)req_addr;
3125	response = (struct pci_response *)buffer;
3126	/*
3127	* Call ->completion_func() within the critical section to make
3128	* sure that the packet pointer is still valid during the call:
3129	* here 'valid' means that there's a task still waiting for the
3130	* completion, and that the packet data is still on the waiting
3131	* task's stack. Cf. hv_compose_msi_msg().
3132	*/
3133	comp_packet->completion_func(comp_packet->compl_ctxt,
3134	response,
3135	bytes_recvd);
3136	unlock_requestor(chan, flags);
3137	break;
3138
3139	case VM_PKT_DATA_INBAND:
3140
3141	new_message = (struct pci_incoming_message *)buffer;
3142	switch (new_message->message_type.type) {
3143	case PCI_BUS_RELATIONS:
3144
3145	bus_rel = (struct pci_bus_relations *)buffer;
3146	if (bytes_recvd < sizeof(*bus_rel) \|\|
3147	bytes_recvd <
3148	struct_size(bus_rel, func,
3149	bus_rel->device_count)) {
3150	dev_err(&hbus->hdev->device,
3151	"bus relations too small\n");
3152	break;
3153	}
3154
3155	hv_pci_devices_present(hbus, bus_rel);
3156	break;
3157
3158	case PCI_BUS_RELATIONS2:
3159
3160	bus_rel2 = (struct pci_bus_relations2 *)buffer;
3161	if (bytes_recvd < sizeof(*bus_rel2) \|\|
3162	bytes_recvd <
3163	struct_size(bus_rel2, func,
3164	bus_rel2->device_count)) {
3165	dev_err(&hbus->hdev->device,
3166	"bus relations v2 too small\n");
3167	break;
3168	}
3169
3170	hv_pci_devices_present2(hbus, bus_rel2);
3171	break;
3172
3173	case PCI_EJECT:
3174
3175	dev_message = (struct pci_dev_incoming *)buffer;
3176	if (bytes_recvd < sizeof(*dev_message)) {
3177	dev_err(&hbus->hdev->device,
3178	"eject message too small\n");
3179	break;
3180	}
3181	hpdev = get_pcichild_wslot(hbus,
3182	dev_message->wslot.slot);
3183	if (hpdev) {
3184	hv_pci_eject_device(hpdev);
3185	put_pcichild(hpdev);
3186	}
3187	break;
3188
3189	case PCI_INVALIDATE_BLOCK:
3190
3191	inval = (struct pci_dev_inval_block *)buffer;
3192	if (bytes_recvd < sizeof(*inval)) {
3193	dev_err(&hbus->hdev->device,
3194	"invalidate message too small\n");
3195	break;
3196	}
3197	hpdev = get_pcichild_wslot(hbus,
3198	inval->wslot.slot);
3199	if (hpdev) {
3200	if (hpdev->block_invalidate) {
3201	hpdev->block_invalidate(
3202	hpdev->invalidate_context,
3203	inval->block_mask);
3204	}
3205	put_pcichild(hpdev);
3206	}
3207	break;
3208
3209	default:
3210	dev_warn(&hbus->hdev->device,
3211	"Unimplemented protocol message %x\n",
3212	new_message->message_type.type);
3213	break;
3214	}
3215	break;
3216
3217	default:
3218	dev_err(&hbus->hdev->device,
3219	"unhandled packet type %d, tid %llx len %d\n",
3220	desc->type, req_id, bytes_recvd);
3221	break;
3222	}
3223	}
3224
3225	kfree(buffer);
3226	}
3227
3228	/**
3229	* hv_pci_protocol_negotiation() - Set up protocol
3230	* @hdev: VMBus's tracking struct for this root PCI bus.
3231	* @version: Array of supported channel protocol versions in
3232	* the order of probing - highest go first.
3233	* @num_version: Number of elements in the version array.
3234	*
3235	* This driver is intended to support running on Windows 10
3236	* (server) and later versions. It will not run on earlier
3237	* versions, as they assume that many of the operations which
3238	* Linux needs accomplished with a spinlock held were done via
3239	* asynchronous messaging via VMBus. Windows 10 increases the
3240	* surface area of PCI emulation so that these actions can take
3241	* place by suspending a virtual processor for their duration.
3242	*
3243	* This function negotiates the channel protocol version,
3244	* failing if the host doesn't support the necessary protocol
3245	* level.
3246	*/
3247	static int hv_pci_protocol_negotiation(struct hv_device *hdev,
3248	enum pci_protocol_version_t version[],
3249	int num_version)
3250	{
3251	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3252	struct pci_version_request *version_req;
3253	struct hv_pci_compl comp_pkt;
3254	struct pci_packet *pkt;
3255	int ret;
3256	int i;
3257
3258	/*
3259	* Initiate the handshake with the host and negotiate
3260	* a version that the host can support. We start with the
3261	* highest version number and go down if the host cannot
3262	* support it.
3263	*/
3264	pkt = kzalloc(sizeof(pkt) + sizeof(version_req), GFP_KERNEL);
3265	if (!pkt)
3266	return -ENOMEM;
3267
3268	init_completion(&comp_pkt.host_event);
3269	pkt->completion_func = hv_pci_generic_compl;
3270	pkt->compl_ctxt = &comp_pkt;
3271	version_req = (struct pci_version_request *)(pkt + 1);
3272	version_req->message_type.type = PCI_QUERY_PROTOCOL_VERSION;
3273
3274	for (i = 0; i < num_version; i++) {
3275	version_req->protocol_version = version[i];
3276	ret = vmbus_sendpacket(hdev->channel, version_req,
3277	sizeof(struct pci_version_request),
3278	(unsigned long)pkt, VM_PKT_DATA_INBAND,
3279	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3280	if (!ret)
3281	ret = wait_for_response(hdev, &comp_pkt.host_event,
3282	"PCI_QUERY_PROTOCOL_VERSION");
3283
3284	if (ret) {
3285	dev_err(&hdev->device,
3286	"PCI Pass-through VSP failed to request version: %d",
3287	ret);
3288	goto exit;
3289	}
3290
3291	if (comp_pkt.completion_status >= 0) {
3292	hbus->protocol_version = version[i];
3293	dev_info(&hdev->device,
3294	"PCI VMBus probing: Using version %#x\n",
3295	hbus->protocol_version);
3296	goto exit;
3297	}
3298
3299	if (comp_pkt.completion_status != STATUS_REVISION_MISMATCH) {
3300	dev_err(&hdev->device,
3301	"PCI Pass-through VSP failed version request: %#x",
3302	comp_pkt.completion_status);
3303	ret = -EPROTO;
3304	goto exit;
3305	}
3306
3307	reinit_completion(&comp_pkt.host_event);
3308	}
3309
3310	dev_err(&hdev->device,
3311	"PCI pass-through VSP failed to find supported version");
3312	ret = -EPROTO;
3313
3314	exit:
3315	kfree(pkt);
3316	return ret;
3317	}
3318
3319	/**
3320	* hv_pci_free_bridge_windows() - Release memory regions for the
3321	* bus
3322	* @hbus: Root PCI bus, as understood by this driver
3323	*/
3324	static void hv_pci_free_bridge_windows(struct hv_pcibus_device *hbus)
3325	{
3326	/*
3327	* Set the resources back to the way they looked when they
3328	* were allocated by setting IORESOURCE_BUSY again.
3329	*/
3330
3331	if (hbus->low_mmio_space && hbus->low_mmio_res) {
3332	hbus->low_mmio_res->flags \|= IORESOURCE_BUSY;
3333	vmbus_free_mmio(hbus->low_mmio_res->start,
3334	resource_size(hbus->low_mmio_res));
3335	}
3336
3337	if (hbus->high_mmio_space && hbus->high_mmio_res) {
3338	hbus->high_mmio_res->flags \|= IORESOURCE_BUSY;
3339	vmbus_free_mmio(hbus->high_mmio_res->start,
3340	resource_size(hbus->high_mmio_res));
3341	}
3342	}
3343
3344	/**
3345	* hv_pci_allocate_bridge_windows() - Allocate memory regions
3346	* for the bus
3347	* @hbus: Root PCI bus, as understood by this driver
3348	*
3349	* This function calls vmbus_allocate_mmio(), which is itself a
3350	* bit of a compromise. Ideally, we might change the pnp layer
3351	* in the kernel such that it comprehends either PCI devices
3352	* which are "grandchildren of ACPI," with some intermediate bus
3353	* node (in this case, VMBus) or change it such that it
3354	* understands VMBus. The pnp layer, however, has been declared
3355	* deprecated, and not subject to change.
3356	*
3357	* The workaround, implemented here, is to ask VMBus to allocate
3358	* MMIO space for this bus. VMBus itself knows which ranges are
3359	* appropriate by looking at its own ACPI objects. Then, after
3360	* these ranges are claimed, they're modified to look like they
3361	* would have looked if the ACPI and pnp code had allocated
3362	* bridge windows. These descriptors have to exist in this form
3363	* in order to satisfy the code which will get invoked when the
3364	* endpoint PCI function driver calls request_mem_region() or
3365	* request_mem_region_exclusive().
3366	*
3367	* Return: 0 on success, -errno on failure
3368	*/
3369	static int hv_pci_allocate_bridge_windows(struct hv_pcibus_device *hbus)
3370	{
3371	resource_size_t align;
3372	int ret;
3373
3374	if (hbus->low_mmio_space) {
3375	align = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
3376	ret = vmbus_allocate_mmio(&hbus->low_mmio_res, hbus->hdev, 0,
3377	(u64)(u32)0xffffffff,
3378	hbus->low_mmio_space,
3379	align, false);
3380	if (ret) {
3381	dev_err(&hbus->hdev->device,
3382	"Need %#llx of low MMIO space. Consider reconfiguring the VM.\n",
3383	hbus->low_mmio_space);
3384	return ret;
3385	}
3386
3387	/* Modify this resource to become a bridge window. */
3388	hbus->low_mmio_res->flags \|= IORESOURCE_WINDOW;
3389	hbus->low_mmio_res->flags &= ~IORESOURCE_BUSY;
3390	pci_add_resource(&hbus->bridge->windows, hbus->low_mmio_res);
3391	}
3392
3393	if (hbus->high_mmio_space) {
3394	align = 1ULL << (63 - __builtin_clzll(hbus->high_mmio_space));
3395	ret = vmbus_allocate_mmio(&hbus->high_mmio_res, hbus->hdev,
3396	0x100000000, -1,
3397	hbus->high_mmio_space, align,
3398	false);
3399	if (ret) {
3400	dev_err(&hbus->hdev->device,
3401	"Need %#llx of high MMIO space. Consider reconfiguring the VM.\n",
3402	hbus->high_mmio_space);
3403	goto release_low_mmio;
3404	}
3405
3406	/* Modify this resource to become a bridge window. */
3407	hbus->high_mmio_res->flags \|= IORESOURCE_WINDOW;
3408	hbus->high_mmio_res->flags &= ~IORESOURCE_BUSY;
3409	pci_add_resource(&hbus->bridge->windows, hbus->high_mmio_res);
3410	}
3411
3412	return 0;
3413
3414	release_low_mmio:
3415	if (hbus->low_mmio_res) {
3416	vmbus_free_mmio(hbus->low_mmio_res->start,
3417	resource_size(hbus->low_mmio_res));
3418	}
3419
3420	return ret;
3421	}
3422
3423	/**
3424	* hv_allocate_config_window() - Find MMIO space for PCI Config
3425	* @hbus: Root PCI bus, as understood by this driver
3426	*
3427	* This function claims memory-mapped I/O space for accessing
3428	* configuration space for the functions on this bus.
3429	*
3430	* Return: 0 on success, -errno on failure
3431	*/
3432	static int hv_allocate_config_window(struct hv_pcibus_device *hbus)
3433	{
3434	int ret;
3435
3436	/*
3437	* Set up a region of MMIO space to use for accessing configuration
3438	* space.
3439	*/
3440	ret = vmbus_allocate_mmio(&hbus->mem_config, hbus->hdev, 0, -1,
3441	PCI_CONFIG_MMIO_LENGTH, 0x1000, false);
3442	if (ret)
3443	return ret;
3444
3445	/*
3446	* vmbus_allocate_mmio() gets used for allocating both device endpoint
3447	* resource claims (those which cannot be overlapped) and the ranges
3448	* which are valid for the children of this bus, which are intended
3449	* to be overlapped by those children. Set the flag on this claim
3450	* meaning that this region can't be overlapped.
3451	*/
3452
3453	hbus->mem_config->flags \|= IORESOURCE_BUSY;
3454
3455	return 0;
3456	}
3457
3458	static void hv_free_config_window(struct hv_pcibus_device *hbus)
3459	{
3460	vmbus_free_mmio(hbus->mem_config->start, PCI_CONFIG_MMIO_LENGTH);
3461	}
3462
3463	static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs);
3464
3465	/**
3466	* hv_pci_enter_d0() - Bring the "bus" into the D0 power state
3467	* @hdev: VMBus's tracking struct for this root PCI bus
3468	*
3469	* Return: 0 on success, -errno on failure
3470	*/
3471	static int hv_pci_enter_d0(struct hv_device *hdev)
3472	{
3473	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3474	struct pci_bus_d0_entry *d0_entry;
3475	struct hv_pci_compl comp_pkt;
3476	struct pci_packet *pkt;
3477	bool retry = true;
3478	int ret;
3479
3480	enter_d0_retry:
3481	/*
3482	* Tell the host that the bus is ready to use, and moved into the
3483	* powered-on state. This includes telling the host which region
3484	* of memory-mapped I/O space has been chosen for configuration space
3485	* access.
3486	*/
3487	pkt = kzalloc(sizeof(pkt) + sizeof(d0_entry), GFP_KERNEL);
3488	if (!pkt)
3489	return -ENOMEM;
3490
3491	init_completion(&comp_pkt.host_event);
3492	pkt->completion_func = hv_pci_generic_compl;
3493	pkt->compl_ctxt = &comp_pkt;
3494	d0_entry = (struct pci_bus_d0_entry *)(pkt + 1);
3495	d0_entry->message_type.type = PCI_BUS_D0ENTRY;
3496	d0_entry->mmio_base = hbus->mem_config->start;
3497
3498	ret = vmbus_sendpacket(hdev->channel, d0_entry, sizeof(*d0_entry),
3499	(unsigned long)pkt, VM_PKT_DATA_INBAND,
3500	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3501	if (!ret)
3502	ret = wait_for_response(hdev, &comp_pkt.host_event,
3503	"PCI_BUS_D0ENTRY");
3504
3505	if (ret)
3506	goto exit;
3507
3508	/*
3509	* In certain case (Kdump) the pci device of interest was
3510	* not cleanly shut down and resource is still held on host
3511	* side, the host could return invalid device status.
3512	* We need to explicitly request host to release the resource
3513	* and try to enter D0 again.
3514	*/
3515	if (comp_pkt.completion_status < 0 && retry) {
3516	retry = false;
3517
3518	dev_err(&hdev->device, "Retrying D0 Entry\n");
3519
3520	/*
3521	* Hv_pci_bus_exit() calls hv_send_resource_released()
3522	* to free up resources of its child devices.
3523	* In the kdump kernel we need to set the
3524	* wslot_res_allocated to 255 so it scans all child
3525	* devices to release resources allocated in the
3526	* normal kernel before panic happened.
3527	*/
3528	hbus->wslot_res_allocated = 255;
3529
3530	ret = hv_pci_bus_exit(hdev, true);
3531
3532	if (ret == 0) {
3533	kfree(pkt);
3534	goto enter_d0_retry;
3535	}
3536	dev_err(&hdev->device,
3537	"Retrying D0 failed with ret %d\n", ret);
3538	}
3539
3540	if (comp_pkt.completion_status < 0) {
3541	dev_err(&hdev->device,
3542	"PCI Pass-through VSP failed D0 Entry with status %x\n",
3543	comp_pkt.completion_status);
3544	ret = -EPROTO;
3545	goto exit;
3546	}
3547
3548	ret = 0;
3549
3550	exit:
3551	kfree(pkt);
3552	return ret;
3553	}
3554
3555	/**
3556	* hv_pci_query_relations() - Ask host to send list of child
3557	* devices
3558	* @hdev: VMBus's tracking struct for this root PCI bus
3559	*
3560	* Return: 0 on success, -errno on failure
3561	*/
3562	static int hv_pci_query_relations(struct hv_device *hdev)
3563	{
3564	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3565	struct pci_message message;
3566	struct completion comp;
3567	int ret;
3568
3569	/* Ask the host to send along the list of child devices */
3570	init_completion(&comp);
3571	if (cmpxchg(&hbus->survey_event, NULL, &comp))
3572	return -ENOTEMPTY;
3573
3574	memset(&message, 0, sizeof(message));
3575	message.type = PCI_QUERY_BUS_RELATIONS;
3576
3577	ret = vmbus_sendpacket(hdev->channel, &message, sizeof(message),
3578	0, VM_PKT_DATA_INBAND, 0);
3579	if (!ret)
3580	ret = wait_for_response(hdev, &comp,
3581	"PCI_QUERY_BUS_RELATIONS");
3582
3583	/*
3584	* In the case of fast device addition/removal, it's possible that
3585	* vmbus_sendpacket() or wait_for_response() returns -ENODEV but we
3586	* already got a PCI_BUS_RELATIONS* message from the host and the
3587	* channel callback already scheduled a work to hbus->wq, which can be
3588	* running pci_devices_present_work() -> survey_child_resources() ->
3589	* complete(&hbus->survey_event), even after hv_pci_query_relations()
3590	* exits and the stack variable 'comp' is no longer valid; as a result,
3591	* a hang or a page fault may happen when the complete() calls
3592	* raw_spin_lock_irqsave(). Flush hbus->wq before we exit from
3593	* hv_pci_query_relations() to avoid the issues. Note: if 'ret' is
3594	* -ENODEV, there can't be any more work item scheduled to hbus->wq
3595	* after the flush_workqueue(): see vmbus_onoffer_rescind() ->
3596	* vmbus_reset_channel_cb(), vmbus_rescind_cleanup() ->
3597	* channel->rescind = true.
3598	*/
3599	flush_workqueue(hbus->wq);
3600
3601	return ret;
3602	}
3603
3604	/**
3605	* hv_send_resources_allocated() - Report local resource choices
3606	* @hdev: VMBus's tracking struct for this root PCI bus
3607	*
3608	* The host OS is expecting to be sent a request as a message
3609	* which contains all the resources that the device will use.
3610	* The response contains those same resources, "translated"
3611	* which is to say, the values which should be used by the
3612	* hardware, when it delivers an interrupt. (MMIO resources are
3613	* used in local terms.) This is nice for Windows, and lines up
3614	* with the FDO/PDO split, which doesn't exist in Linux. Linux
3615	* is deeply expecting to scan an emulated PCI configuration
3616	* space. So this message is sent here only to drive the state
3617	* machine on the host forward.
3618	*
3619	* Return: 0 on success, -errno on failure
3620	*/
3621	static int hv_send_resources_allocated(struct hv_device *hdev)
3622	{
3623	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3624	struct pci_resources_assigned *res_assigned;
3625	struct pci_resources_assigned2 *res_assigned2;
3626	struct hv_pci_compl comp_pkt;
3627	struct hv_pci_dev *hpdev;
3628	struct pci_packet *pkt;
3629	size_t size_res;
3630	int wslot;
3631	int ret;
3632
3633	size_res = (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2)
3634	? sizeof(res_assigned) : sizeof(res_assigned2);
3635
3636	pkt = kmalloc(sizeof(*pkt) + size_res, GFP_KERNEL);
3637	if (!pkt)
3638	return -ENOMEM;
3639
3640	ret = 0;
3641
3642	for (wslot = 0; wslot < 256; wslot++) {
3643	hpdev = get_pcichild_wslot(hbus, wslot);
3644	if (!hpdev)
3645	continue;
3646
3647	memset(pkt, 0, sizeof(*pkt) + size_res);
3648	init_completion(&comp_pkt.host_event);
3649	pkt->completion_func = hv_pci_generic_compl;
3650	pkt->compl_ctxt = &comp_pkt;
3651
3652	if (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2) {
3653	res_assigned =
3654	(struct pci_resources_assigned *)(pkt + 1);
3655	res_assigned->message_type.type =
3656	PCI_RESOURCES_ASSIGNED;
3657	res_assigned->wslot.slot = hpdev->desc.win_slot.slot;
3658	} else {
3659	res_assigned2 =
3660	(struct pci_resources_assigned2 *)(pkt + 1);
3661	res_assigned2->message_type.type =
3662	PCI_RESOURCES_ASSIGNED2;
3663	res_assigned2->wslot.slot = hpdev->desc.win_slot.slot;
3664	}
3665	put_pcichild(hpdev);
3666
3667	ret = vmbus_sendpacket(hdev->channel, pkt + 1,
3668	size_res, (unsigned long)pkt,
3669	VM_PKT_DATA_INBAND,
3670	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3671	if (!ret)
3672	ret = wait_for_response(hdev, &comp_pkt.host_event,
3673	"PCI_RESOURCE_ASSIGNED");
3674	if (ret)
3675	break;
3676
3677	if (comp_pkt.completion_status < 0) {
3678	ret = -EPROTO;
3679	dev_err(&hdev->device,
3680	"resource allocated returned 0x%x",
3681	comp_pkt.completion_status);
3682	break;
3683	}
3684
3685	hbus->wslot_res_allocated = wslot;
3686	}
3687
3688	kfree(pkt);
3689	return ret;
3690	}
3691
3692	/**
3693	* hv_send_resources_released() - Report local resources
3694	* released
3695	* @hdev: VMBus's tracking struct for this root PCI bus
3696	*
3697	* Return: 0 on success, -errno on failure
3698	*/
3699	static int hv_send_resources_released(struct hv_device *hdev)
3700	{
3701	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3702	struct pci_child_message pkt;
3703	struct hv_pci_dev *hpdev;
3704	int wslot;
3705	int ret;
3706
3707	for (wslot = hbus->wslot_res_allocated; wslot >= 0; wslot--) {
3708	hpdev = get_pcichild_wslot(hbus, wslot);
3709	if (!hpdev)
3710	continue;
3711
3712	memset(&pkt, 0, sizeof(pkt));
3713	pkt.message_type.type = PCI_RESOURCES_RELEASED;
3714	pkt.wslot.slot = hpdev->desc.win_slot.slot;
3715
3716	put_pcichild(hpdev);
3717
3718	ret = vmbus_sendpacket(hdev->channel, &pkt, sizeof(pkt), 0,
3719	VM_PKT_DATA_INBAND, 0);
3720	if (ret)
3721	return ret;
3722
3723	hbus->wslot_res_allocated = wslot - 1;
3724	}
3725
3726	hbus->wslot_res_allocated = -1;
3727
3728	return 0;
3729	}
3730
3731	/**
3732	* hv_pci_probe() - New VMBus channel probe, for a root PCI bus
3733	* @hdev: VMBus's tracking struct for this root PCI bus
3734	* @dev_id: Identifies the device itself
3735	*
3736	* Return: 0 on success, -errno on failure
3737	*/
3738	static int hv_pci_probe(struct hv_device *hdev,
3739	const struct hv_vmbus_device_id *dev_id)
3740	{
3741	struct pci_host_bridge *bridge;
3742	struct hv_pcibus_device *hbus;
3743	int ret, dom;
3744	u16 dom_req;
3745	char *name;
3746
3747	bridge = devm_pci_alloc_host_bridge(&hdev->device, 0);
3748	if (!bridge)
3749	return -ENOMEM;
3750
3751	hbus = kzalloc_obj(*hbus);
3752	if (!hbus)
3753	return -ENOMEM;
3754
3755	hbus->bridge = bridge;
3756	mutex_init(&hbus->state_lock);
3757	hbus->state = hv_pcibus_init;
3758	hbus->wslot_res_allocated = -1;
3759
3760	/*
3761	* The PCI bus "domain" is what is called "segment" in ACPI and other
3762	* specs. Pull it from the instance ID, to get something usually
3763	* unique. In rare cases of collision, we will find out another number
3764	* not in use.
3765	*
3766	* Note that, since this code only runs in a Hyper-V VM, Hyper-V
3767	* together with this guest driver can guarantee that (1) The only
3768	* domain used by Gen1 VMs for something that looks like a physical
3769	* PCI bus (which is actually emulated by the hypervisor) is domain 0.
3770	* (2) There will be no overlap between domains (after fixing possible
3771	* collisions) in the same VM.
3772	*
3773	* Because Gen1 VMs use domain 0, don't allow picking domain 0 here,
3774	* even if bytes 4 and 5 of the instance GUID are both zero. For wider
3775	* userspace compatibility, limit the domain ID to a 16-bit value.
3776	*/
3777	dom_req = hdev->dev_instance.b[5] << 8 \| hdev->dev_instance.b[4];
3778	dom = pci_bus_find_emul_domain_nr(dom_req, 1, U16_MAX);
3779	if (dom < 0) {
3780	dev_err(&hdev->device,
3781	"Unable to use dom# 0x%x or other numbers", dom_req);
3782	ret = -EINVAL;
3783	goto free_bus;
3784	}
3785
3786	if (dom != dom_req)
3787	dev_info(&hdev->device,
3788	"PCI dom# 0x%x has collision, using 0x%x",
3789	dom_req, dom);
3790
3791	hbus->bridge->domain_nr = dom;
3792	#ifdef CONFIG_X86
3793	hbus->sysdata.domain = dom;
3794	hbus->use_calls = !!(ms_hyperv.hints & HV_X64_USE_MMIO_HYPERCALLS);
3795	#elif defined(CONFIG_ARM64)
3796	/*
3797	* Set the PCI bus parent to be the corresponding VMbus
3798	* device. Then the VMbus device will be assigned as the
3799	* ACPI companion in pcibios_root_bridge_prepare() and
3800	* pci_dma_configure() will propagate device coherence
3801	* information to devices created on the bus.
3802	*/
3803	hbus->sysdata.parent = hdev->device.parent;
3804	hbus->use_calls = false;
3805	#endif
3806
3807	hbus->hdev = hdev;
3808	INIT_LIST_HEAD(&hbus->children);
3809	INIT_LIST_HEAD(&hbus->dr_list);
3810	spin_lock_init(&hbus->config_lock);
3811	spin_lock_init(&hbus->device_list_lock);
3812	hbus->wq = alloc_ordered_workqueue("hv_pci_%x", 0,
3813	hbus->bridge->domain_nr);
3814	if (!hbus->wq) {
3815	ret = -ENOMEM;
3816	goto free_bus;
3817	}
3818
3819	hdev->channel->next_request_id_callback = vmbus_next_request_id;
3820	hdev->channel->request_addr_callback = vmbus_request_addr;
3821	hdev->channel->rqstor_size = HV_PCI_RQSTOR_SIZE;
3822
3823	ret = vmbus_open(hdev->channel, pci_ring_size, pci_ring_size, NULL, 0,
3824	hv_pci_onchannelcallback, hbus);
3825	if (ret)
3826	goto destroy_wq;
3827
3828	hv_set_drvdata(hdev, hbus);
3829
3830	ret = hv_pci_protocol_negotiation(hdev, pci_protocol_versions,
3831	ARRAY_SIZE(pci_protocol_versions));
3832	if (ret)
3833	goto close;
3834
3835	ret = hv_allocate_config_window(hbus);
3836	if (ret)
3837	goto close;
3838
3839	hbus->cfg_addr = ioremap(hbus->mem_config->start,
3840	PCI_CONFIG_MMIO_LENGTH);
3841	if (!hbus->cfg_addr) {
3842	dev_err(&hdev->device,
3843	"Unable to map a virtual address for config space\n");
3844	ret = -ENOMEM;
3845	goto free_config;
3846	}
3847
3848	name = kasprintf(GFP_KERNEL, "%pUL", &hdev->dev_instance);
3849	if (!name) {
3850	ret = -ENOMEM;
3851	goto unmap;
3852	}
3853
3854	hbus->fwnode = irq_domain_alloc_named_fwnode(name);
3855	kfree(name);
3856	if (!hbus->fwnode) {
3857	ret = -ENOMEM;
3858	goto unmap;
3859	}
3860
3861	ret = hv_pcie_init_irq_domain(hbus);
3862	if (ret)
3863	goto free_fwnode;
3864
3865	ret = hv_pci_query_relations(hdev);
3866	if (ret)
3867	goto free_irq_domain;
3868
3869	mutex_lock(&hbus->state_lock);
3870
3871	ret = hv_pci_enter_d0(hdev);
3872	if (ret)
3873	goto release_state_lock;
3874
3875	ret = hv_pci_allocate_bridge_windows(hbus);
3876	if (ret)
3877	goto exit_d0;
3878
3879	ret = hv_send_resources_allocated(hdev);
3880	if (ret)
3881	goto free_windows;
3882
3883	prepopulate_bars(hbus);
3884
3885	hbus->state = hv_pcibus_probed;
3886
3887	ret = create_root_hv_pci_bus(hbus);
3888	if (ret)
3889	goto free_windows;
3890
3891	mutex_unlock(&hbus->state_lock);
3892	return 0;
3893
3894	free_windows:
3895	hv_pci_free_bridge_windows(hbus);
3896	exit_d0:
3897	(void) hv_pci_bus_exit(hdev, true);
3898	release_state_lock:
3899	mutex_unlock(&hbus->state_lock);
3900	free_irq_domain:
3901	irq_domain_remove(hbus->irq_domain);
3902	free_fwnode:
3903	irq_domain_free_fwnode(hbus->fwnode);
3904	unmap:
3905	iounmap(hbus->cfg_addr);
3906	free_config:
3907	hv_free_config_window(hbus);
3908	close:
3909	vmbus_close(hdev->channel);
3910	destroy_wq:
3911	destroy_workqueue(hbus->wq);
3912	free_bus:
3913	kfree(hbus);
3914	return ret;
3915	}
3916
3917	static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs)
3918	{
3919	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
3920	struct vmbus_channel *chan = hdev->channel;
3921	struct {
3922	struct pci_packet teardown_packet;
3923	u8 buffer[sizeof(struct pci_message)];
3924	} pkt;
3925	struct pci_message *msg;
3926	struct hv_pci_compl comp_pkt;
3927	struct hv_pci_dev hpdev, tmp;
3928	unsigned long flags;
3929	u64 trans_id;
3930	int ret;
3931
3932	/*
3933	* After the host sends the RESCIND_CHANNEL message, it doesn't
3934	* access the per-channel ringbuffer any longer.
3935	*/
3936	if (chan->rescind)
3937	return 0;
3938
3939	if (!keep_devs) {
3940	struct list_head removed;
3941
3942	/* Move all present children to the list on stack */
3943	INIT_LIST_HEAD(&removed);
3944	spin_lock_irqsave(&hbus->device_list_lock, flags);
3945	list_for_each_entry_safe(hpdev, tmp, &hbus->children, list_entry)
3946	list_move_tail(&hpdev->list_entry, &removed);
3947	spin_unlock_irqrestore(&hbus->device_list_lock, flags);
3948
3949	/* Remove all children in the list */
3950	list_for_each_entry_safe(hpdev, tmp, &removed, list_entry) {
3951	list_del(&hpdev->list_entry);
3952	if (hpdev->pci_slot)
3953	pci_destroy_slot(hpdev->pci_slot);
3954	/* For the two refs got in new_pcichild_device() */
3955	put_pcichild(hpdev);
3956	put_pcichild(hpdev);
3957	}
3958	}
3959
3960	ret = hv_send_resources_released(hdev);
3961	if (ret) {
3962	dev_err(&hdev->device,
3963	"Couldn't send resources released packet(s)\n");
3964	return ret;
3965	}
3966
3967	memset(&pkt.teardown_packet, 0, sizeof(pkt.teardown_packet));
3968	init_completion(&comp_pkt.host_event);
3969	pkt.teardown_packet.completion_func = hv_pci_generic_compl;
3970	pkt.teardown_packet.compl_ctxt = &comp_pkt;
3971	msg = (struct pci_message *)pkt.buffer;
3972	msg->type = PCI_BUS_D0EXIT;
3973
3974	ret = vmbus_sendpacket_getid(chan, msg, sizeof(*msg),
3975	(unsigned long)&pkt.teardown_packet,
3976	&trans_id, VM_PKT_DATA_INBAND,
3977	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3978	if (ret)
3979	return ret;
3980
3981	if (wait_for_completion_timeout(&comp_pkt.host_event, 10 * HZ) == 0) {
3982	/*
3983	* The completion packet on the stack becomes invalid after
3984	* 'return'; remove the ID from the VMbus requestor if the
3985	* identifier is still mapped to/associated with the packet.
3986	*
3987	* Cf. hv_pci_onchannelcallback().
3988	*/
3989	vmbus_request_addr_match(chan, trans_id,
3990	(unsigned long)&pkt.teardown_packet);
3991	return -ETIMEDOUT;
3992	}
3993
3994	return 0;
3995	}
3996
3997	/**
3998	* hv_pci_remove() - Remove routine for this VMBus channel
3999	* @hdev: VMBus's tracking struct for this root PCI bus
4000	*/
4001	static void hv_pci_remove(struct hv_device *hdev)
4002	{
4003	struct hv_pcibus_device *hbus;
4004
4005	hbus = hv_get_drvdata(hdev);
4006	if (hbus->state == hv_pcibus_installed) {
4007	tasklet_disable(&hdev->channel->callback_event);
4008	hbus->state = hv_pcibus_removing;
4009	tasklet_enable(&hdev->channel->callback_event);
4010	destroy_workqueue(hbus->wq);
4011	hbus->wq = NULL;
4012	/*
4013	* At this point, no work is running or can be scheduled
4014	* on hbus-wq. We can't race with hv_pci_devices_present()
4015	* or hv_pci_eject_device(), it's safe to proceed.
4016	*/
4017
4018	/* Remove the bus from PCI's point of view. */
4019	pci_lock_rescan_remove();
4020	pci_stop_root_bus(hbus->bridge->bus);
4021	hv_pci_remove_slots(hbus);
4022	pci_remove_root_bus(hbus->bridge->bus);
4023	pci_unlock_rescan_remove();
4024	}
4025
4026	hv_pci_bus_exit(hdev, false);
4027
4028	vmbus_close(hdev->channel);
4029
4030	iounmap(hbus->cfg_addr);
4031	hv_free_config_window(hbus);
4032	hv_pci_free_bridge_windows(hbus);
4033	irq_domain_remove(hbus->irq_domain);
4034	irq_domain_free_fwnode(hbus->fwnode);
4035
4036	kfree(hbus);
4037	}
4038
4039	static int hv_pci_suspend(struct hv_device *hdev)
4040	{
4041	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
4042	enum hv_pcibus_state old_state;
4043	int ret;
4044
4045	/*
4046	* hv_pci_suspend() must make sure there are no pending work items
4047	* before calling vmbus_close(), since it runs in a process context
4048	* as a callback in dpm_suspend(). When it starts to run, the channel
4049	* callback hv_pci_onchannelcallback(), which runs in a tasklet
4050	* context, can be still running concurrently and scheduling new work
4051	* items onto hbus->wq in hv_pci_devices_present() and
4052	* hv_pci_eject_device(), and the work item handlers can access the
4053	* vmbus channel, which can be being closed by hv_pci_suspend(), e.g.
4054	* the work item handler pci_devices_present_work() ->
4055	* new_pcichild_device() writes to the vmbus channel.
4056	*
4057	* To eliminate the race, hv_pci_suspend() disables the channel
4058	* callback tasklet, sets hbus->state to hv_pcibus_removing, and
4059	* re-enables the tasklet. This way, when hv_pci_suspend() proceeds,
4060	* it knows that no new work item can be scheduled, and then it flushes
4061	* hbus->wq and safely closes the vmbus channel.
4062	*/
4063	tasklet_disable(&hdev->channel->callback_event);
4064
4065	/* Change the hbus state to prevent new work items. */
4066	old_state = hbus->state;
4067	if (hbus->state == hv_pcibus_installed)
4068	hbus->state = hv_pcibus_removing;
4069
4070	tasklet_enable(&hdev->channel->callback_event);
4071
4072	if (old_state != hv_pcibus_installed)
4073	return -EINVAL;
4074
4075	flush_workqueue(hbus->wq);
4076
4077	ret = hv_pci_bus_exit(hdev, true);
4078	if (ret)
4079	return ret;
4080
4081	vmbus_close(hdev->channel);
4082
4083	return 0;
4084	}
4085
4086	static int hv_pci_restore_msi_msg(struct pci_dev pdev, void arg)
4087	{
4088	struct irq_data *irq_data;
4089	struct msi_desc *entry;
4090
4091	if (!pdev->msi_enabled && !pdev->msix_enabled)
4092	return 0;
4093
4094	guard(msi_descs_lock)(&pdev->dev);
4095	msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) {
4096	irq_data = irq_get_irq_data(entry->irq);
4097	if (WARN_ON_ONCE(!irq_data))
4098	return -EINVAL;
4099	hv_compose_msi_msg(irq_data, &entry->msg);
4100	}
4101	return 0;
4102	}
4103
4104	/*
4105	* Upon resume, pci_restore_msi_state() -> ... -> __pci_write_msi_msg()
4106	* directly writes the MSI/MSI-X registers via MMIO, but since Hyper-V
4107	* doesn't trap and emulate the MMIO accesses, here hv_compose_msi_msg()
4108	* must be used to ask Hyper-V to re-create the IOMMU Interrupt Remapping
4109	* Table entries.
4110	*/
4111	static void hv_pci_restore_msi_state(struct hv_pcibus_device *hbus)
4112	{
4113	pci_walk_bus(hbus->bridge->bus, hv_pci_restore_msi_msg, NULL);
4114	}
4115
4116	static int hv_pci_resume(struct hv_device *hdev)
4117	{
4118	struct hv_pcibus_device *hbus = hv_get_drvdata(hdev);
4119	enum pci_protocol_version_t version[1];
4120	int ret;
4121
4122	hbus->state = hv_pcibus_init;
4123
4124	hdev->channel->next_request_id_callback = vmbus_next_request_id;
4125	hdev->channel->request_addr_callback = vmbus_request_addr;
4126	hdev->channel->rqstor_size = HV_PCI_RQSTOR_SIZE;
4127
4128	ret = vmbus_open(hdev->channel, pci_ring_size, pci_ring_size, NULL, 0,
4129	hv_pci_onchannelcallback, hbus);
4130	if (ret)
4131	return ret;
4132
4133	/* Only use the version that was in use before hibernation. */
4134	version[0] = hbus->protocol_version;
4135	ret = hv_pci_protocol_negotiation(hdev, version, 1);
4136	if (ret)
4137	goto out;
4138
4139	ret = hv_pci_query_relations(hdev);
4140	if (ret)
4141	goto out;
4142
4143	mutex_lock(&hbus->state_lock);
4144
4145	ret = hv_pci_enter_d0(hdev);
4146	if (ret)
4147	goto release_state_lock;
4148
4149	ret = hv_send_resources_allocated(hdev);
4150	if (ret)
4151	goto release_state_lock;
4152
4153	prepopulate_bars(hbus);
4154
4155	hv_pci_restore_msi_state(hbus);
4156
4157	hbus->state = hv_pcibus_installed;
4158	mutex_unlock(&hbus->state_lock);
4159	return 0;
4160
4161	release_state_lock:
4162	mutex_unlock(&hbus->state_lock);
4163	out:
4164	vmbus_close(hdev->channel);
4165	return ret;
4166	}
4167
4168	static const struct hv_vmbus_device_id hv_pci_id_table[] = {
4169	/* PCI Pass-through Class ID */
4170	/* 44C4F61D-4444-4400-9D52-802E27EDE19F */
4171	{ HV_PCIE_GUID, },
4172	{ },
4173	};
4174
4175	MODULE_DEVICE_TABLE(vmbus, hv_pci_id_table);
4176
4177	static struct hv_driver hv_pci_drv = {
4178	.name = "hv_pci",
4179	.id_table = hv_pci_id_table,
4180	.probe = hv_pci_probe,
4181	.remove = hv_pci_remove,
4182	.suspend = hv_pci_suspend,
4183	.resume = hv_pci_resume,
4184	.driver = {
4185	.probe_type = PROBE_PREFER_ASYNCHRONOUS,
4186	},
4187	};
4188
4189	static void __exit exit_hv_pci_drv(void)
4190	{
4191	vmbus_driver_unregister(&hv_pci_drv);
4192
4193	hvpci_block_ops.read_block = NULL;
4194	hvpci_block_ops.write_block = NULL;
4195	hvpci_block_ops.reg_blk_invalidate = NULL;
4196	}
4197
4198	static int __init init_hv_pci_drv(void)
4199	{
4200	int ret;
4201
4202	if (!hv_is_hyperv_initialized())
4203	return -ENODEV;
4204
4205	if (!hv_vmbus_exists())
4206	return -ENODEV;
4207
4208	ret = hv_pci_irqchip_init();
4209	if (ret)
4210	return ret;
4211
4212	/* Initialize PCI block r/w interface */
4213	hvpci_block_ops.read_block = hv_read_config_block;
4214	hvpci_block_ops.write_block = hv_write_config_block;
4215	hvpci_block_ops.reg_blk_invalidate = hv_register_block_invalidate;
4216
4217	return vmbus_driver_register(&hv_pci_drv);
4218	}
4219
4220	module_init(init_hv_pci_drv);
4221	module_exit(exit_hv_pci_drv);
4222
4223	MODULE_DESCRIPTION("Hyper-V PCI");
4224	MODULE_LICENSE("GPL v2");