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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
4 * Copyright (c) 2015, Google Inc.
5 */
6
7#ifndef __PHY_TEGRA_XUSB_H
8#define __PHY_TEGRA_XUSB_H
9
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/mutex.h>
13#include <linux/workqueue.h>
14
15#include <linux/usb/ch9.h>
16#include <linux/usb/otg.h>
17#include <linux/usb/role.h>
18
19/* legacy entry points for backwards-compatibility */
20int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
21int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
22
23struct phy;
24struct phy_provider;
25struct platform_device;
26struct regulator;
27
28/*
29 * lanes
30 */
31struct tegra_xusb_lane_soc {
32 const char *name;
33
34 unsigned int offset;
35 unsigned int shift;
36 unsigned int mask;
37
38 const char * const *funcs;
39 unsigned int num_funcs;
40
41 struct {
42 unsigned int misc_ctl2;
43 } regs;
44};
45
46struct tegra_xusb_lane {
47 const struct tegra_xusb_lane_soc *soc;
48 struct tegra_xusb_pad *pad;
49 struct device_node *np;
50 struct list_head list;
51 unsigned int function;
52 unsigned int index;
53};
54
55int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
56 struct device_node *np);
57
58struct tegra_xusb_usb3_lane {
59 struct tegra_xusb_lane base;
60};
61
62static inline struct tegra_xusb_usb3_lane *
63to_usb3_lane(struct tegra_xusb_lane *lane)
64{
65 return container_of(lane, struct tegra_xusb_usb3_lane, base);
66}
67
68struct tegra_xusb_usb2_lane {
69 struct tegra_xusb_lane base;
70
71 u32 hs_curr_level_offset;
72};
73
74static inline struct tegra_xusb_usb2_lane *
75to_usb2_lane(struct tegra_xusb_lane *lane)
76{
77 return container_of(lane, struct tegra_xusb_usb2_lane, base);
78}
79
80struct tegra_xusb_ulpi_lane {
81 struct tegra_xusb_lane base;
82};
83
84static inline struct tegra_xusb_ulpi_lane *
85to_ulpi_lane(struct tegra_xusb_lane *lane)
86{
87 return container_of(lane, struct tegra_xusb_ulpi_lane, base);
88}
89
90struct tegra_xusb_hsic_lane {
91 struct tegra_xusb_lane base;
92
93 u32 strobe_trim;
94 u32 rx_strobe_trim;
95 u32 rx_data_trim;
96 u32 tx_rtune_n;
97 u32 tx_rtune_p;
98 u32 tx_rslew_n;
99 u32 tx_rslew_p;
100 bool auto_term;
101};
102
103static inline struct tegra_xusb_hsic_lane *
104to_hsic_lane(struct tegra_xusb_lane *lane)
105{
106 return container_of(lane, struct tegra_xusb_hsic_lane, base);
107}
108
109struct tegra_xusb_pcie_lane {
110 struct tegra_xusb_lane base;
111};
112
113static inline struct tegra_xusb_pcie_lane *
114to_pcie_lane(struct tegra_xusb_lane *lane)
115{
116 return container_of(lane, struct tegra_xusb_pcie_lane, base);
117}
118
119struct tegra_xusb_sata_lane {
120 struct tegra_xusb_lane base;
121};
122
123static inline struct tegra_xusb_sata_lane *
124to_sata_lane(struct tegra_xusb_lane *lane)
125{
126 return container_of(lane, struct tegra_xusb_sata_lane, base);
127}
128
129struct tegra_xusb_lane_ops {
130 struct tegra_xusb_lane *(*probe)(struct tegra_xusb_pad *pad,
131 struct device_node *np,
132 unsigned int index);
133 void (*remove)(struct tegra_xusb_lane *lane);
134 void (*iddq_enable)(struct tegra_xusb_lane *lane);
135 void (*iddq_disable)(struct tegra_xusb_lane *lane);
136 int (*enable_phy_sleepwalk)(struct tegra_xusb_lane *lane, enum usb_device_speed speed);
137 int (*disable_phy_sleepwalk)(struct tegra_xusb_lane *lane);
138 int (*enable_phy_wake)(struct tegra_xusb_lane *lane);
139 int (*disable_phy_wake)(struct tegra_xusb_lane *lane);
140 bool (*remote_wake_detected)(struct tegra_xusb_lane *lane);
141};
142
143bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, const char *function);
144
145/*
146 * pads
147 */
148struct tegra_xusb_pad_soc;
149struct tegra_xusb_padctl;
150
151struct tegra_xusb_pad_ops {
152 struct tegra_xusb_pad *(*probe)(struct tegra_xusb_padctl *padctl,
153 const struct tegra_xusb_pad_soc *soc,
154 struct device_node *np);
155 void (*remove)(struct tegra_xusb_pad *pad);
156};
157
158struct tegra_xusb_pad_soc {
159 const char *name;
160
161 const struct tegra_xusb_lane_soc *lanes;
162 unsigned int num_lanes;
163
164 const struct tegra_xusb_pad_ops *ops;
165};
166
167struct tegra_xusb_pad {
168 const struct tegra_xusb_pad_soc *soc;
169 struct tegra_xusb_padctl *padctl;
170 struct phy_provider *provider;
171 struct phy **lanes;
172 struct device dev;
173
174 const struct tegra_xusb_lane_ops *ops;
175
176 struct list_head list;
177};
178
179static inline struct tegra_xusb_pad *to_tegra_xusb_pad(struct device *dev)
180{
181 return container_of(dev, struct tegra_xusb_pad, dev);
182}
183
184int tegra_xusb_pad_init(struct tegra_xusb_pad *pad,
185 struct tegra_xusb_padctl *padctl,
186 struct device_node *np);
187int tegra_xusb_pad_register(struct tegra_xusb_pad *pad,
188 const struct phy_ops *ops);
189void tegra_xusb_pad_unregister(struct tegra_xusb_pad *pad);
190
191struct tegra_xusb_usb3_pad {
192 struct tegra_xusb_pad base;
193
194 unsigned int enable;
195 struct mutex lock;
196};
197
198static inline struct tegra_xusb_usb3_pad *
199to_usb3_pad(struct tegra_xusb_pad *pad)
200{
201 return container_of(pad, struct tegra_xusb_usb3_pad, base);
202}
203
204struct tegra_xusb_usb2_pad {
205 struct tegra_xusb_pad base;
206
207 struct clk *clk;
208 unsigned int enable;
209 struct mutex lock;
210};
211
212static inline struct tegra_xusb_usb2_pad *
213to_usb2_pad(struct tegra_xusb_pad *pad)
214{
215 return container_of(pad, struct tegra_xusb_usb2_pad, base);
216}
217
218struct tegra_xusb_ulpi_pad {
219 struct tegra_xusb_pad base;
220};
221
222static inline struct tegra_xusb_ulpi_pad *
223to_ulpi_pad(struct tegra_xusb_pad *pad)
224{
225 return container_of(pad, struct tegra_xusb_ulpi_pad, base);
226}
227
228struct tegra_xusb_hsic_pad {
229 struct tegra_xusb_pad base;
230
231 struct regulator *supply;
232 struct clk *clk;
233};
234
235static inline struct tegra_xusb_hsic_pad *
236to_hsic_pad(struct tegra_xusb_pad *pad)
237{
238 return container_of(pad, struct tegra_xusb_hsic_pad, base);
239}
240
241struct tegra_xusb_pcie_pad {
242 struct tegra_xusb_pad base;
243
244 struct reset_control *rst;
245 struct clk *pll;
246
247 bool enable;
248};
249
250static inline struct tegra_xusb_pcie_pad *
251to_pcie_pad(struct tegra_xusb_pad *pad)
252{
253 return container_of(pad, struct tegra_xusb_pcie_pad, base);
254}
255
256struct tegra_xusb_sata_pad {
257 struct tegra_xusb_pad base;
258
259 struct reset_control *rst;
260 struct clk *pll;
261
262 bool enable;
263};
264
265static inline struct tegra_xusb_sata_pad *
266to_sata_pad(struct tegra_xusb_pad *pad)
267{
268 return container_of(pad, struct tegra_xusb_sata_pad, base);
269}
270
271/*
272 * ports
273 */
274struct tegra_xusb_port_ops;
275
276struct tegra_xusb_port {
277 struct tegra_xusb_padctl *padctl;
278 struct tegra_xusb_lane *lane;
279 unsigned int index;
280
281 struct list_head list;
282 struct device dev;
283
284 struct usb_role_switch *usb_role_sw;
285 struct work_struct usb_phy_work;
286 struct usb_phy usb_phy;
287
288 const struct tegra_xusb_port_ops *ops;
289};
290
291static inline struct tegra_xusb_port *to_tegra_xusb_port(struct device *dev)
292{
293 return container_of(dev, struct tegra_xusb_port, dev);
294}
295
296struct tegra_xusb_lane_map {
297 unsigned int port;
298 const char *type;
299 unsigned int index;
300 const char *func;
301};
302
303struct tegra_xusb_lane *
304tegra_xusb_port_find_lane(struct tegra_xusb_port *port,
305 const struct tegra_xusb_lane_map *map,
306 const char *function);
307
308struct tegra_xusb_port *
309tegra_xusb_find_port(struct tegra_xusb_padctl *padctl, const char *type,
310 unsigned int index);
311
312struct tegra_xusb_usb2_port {
313 struct tegra_xusb_port base;
314
315 struct regulator *supply;
316 enum usb_dr_mode mode;
317 bool internal;
318 int usb3_port_fake;
319};
320
321static inline struct tegra_xusb_usb2_port *
322to_usb2_port(struct tegra_xusb_port *port)
323{
324 return container_of(port, struct tegra_xusb_usb2_port, base);
325}
326
327struct tegra_xusb_usb2_port *
328tegra_xusb_find_usb2_port(struct tegra_xusb_padctl *padctl,
329 unsigned int index);
330void tegra_xusb_usb2_port_release(struct tegra_xusb_port *port);
331void tegra_xusb_usb2_port_remove(struct tegra_xusb_port *port);
332
333struct tegra_xusb_ulpi_port {
334 struct tegra_xusb_port base;
335
336 struct regulator *supply;
337 bool internal;
338};
339
340static inline struct tegra_xusb_ulpi_port *
341to_ulpi_port(struct tegra_xusb_port *port)
342{
343 return container_of(port, struct tegra_xusb_ulpi_port, base);
344}
345
346void tegra_xusb_ulpi_port_release(struct tegra_xusb_port *port);
347
348struct tegra_xusb_hsic_port {
349 struct tegra_xusb_port base;
350};
351
352static inline struct tegra_xusb_hsic_port *
353to_hsic_port(struct tegra_xusb_port *port)
354{
355 return container_of(port, struct tegra_xusb_hsic_port, base);
356}
357
358void tegra_xusb_hsic_port_release(struct tegra_xusb_port *port);
359
360struct tegra_xusb_usb3_port {
361 struct tegra_xusb_port base;
362 bool context_saved;
363 unsigned int port;
364 bool internal;
365 bool disable_gen2;
366
367 u32 tap1;
368 u32 amp;
369 u32 ctle_z;
370 u32 ctle_g;
371};
372
373static inline struct tegra_xusb_usb3_port *
374to_usb3_port(struct tegra_xusb_port *port)
375{
376 return container_of(port, struct tegra_xusb_usb3_port, base);
377}
378
379struct tegra_xusb_usb3_port *
380tegra_xusb_find_usb3_port(struct tegra_xusb_padctl *padctl,
381 unsigned int index);
382void tegra_xusb_usb3_port_release(struct tegra_xusb_port *port);
383
384struct tegra_xusb_port_ops {
385 void (*release)(struct tegra_xusb_port *port);
386 void (*remove)(struct tegra_xusb_port *port);
387 int (*enable)(struct tegra_xusb_port *port);
388 void (*disable)(struct tegra_xusb_port *port);
389 struct tegra_xusb_lane *(*map)(struct tegra_xusb_port *port);
390};
391
392/*
393 * pad controller
394 */
395struct tegra_xusb_padctl_soc;
396
397struct tegra_xusb_padctl_ops {
398 struct tegra_xusb_padctl *
399 (*probe)(struct device *dev,
400 const struct tegra_xusb_padctl_soc *soc);
401 void (*remove)(struct tegra_xusb_padctl *padctl);
402
403 int (*suspend_noirq)(struct tegra_xusb_padctl *padctl);
404 int (*resume_noirq)(struct tegra_xusb_padctl *padctl);
405 int (*usb3_save_context)(struct tegra_xusb_padctl *padctl,
406 unsigned int index);
407 int (*hsic_set_idle)(struct tegra_xusb_padctl *padctl,
408 unsigned int index, bool idle);
409 int (*usb3_set_lfps_detect)(struct tegra_xusb_padctl *padctl,
410 unsigned int index, bool enable);
411 int (*vbus_override)(struct tegra_xusb_padctl *padctl, bool set);
412 int (*utmi_port_reset)(struct phy *phy);
413 void (*utmi_pad_power_on)(struct phy *phy);
414 void (*utmi_pad_power_down)(struct phy *phy);
415};
416
417struct tegra_xusb_padctl_soc {
418 const struct tegra_xusb_pad_soc * const *pads;
419 unsigned int num_pads;
420
421 struct {
422 struct {
423 const struct tegra_xusb_port_ops *ops;
424 unsigned int count;
425 } usb2, ulpi, hsic, usb3;
426 } ports;
427
428 const struct tegra_xusb_padctl_ops *ops;
429
430 const char * const *supply_names;
431 unsigned int num_supplies;
432 bool supports_gen2;
433 bool need_fake_usb3_port;
434 bool poll_trk_completed;
435 bool trk_hw_mode;
436 bool trk_update_on_idle;
437 bool supports_lp_cfg_en;
438 bool has_per_pad_term;
439};
440
441struct tegra_xusb_padctl {
442 struct device *dev;
443 void __iomem *regs;
444 struct mutex lock;
445 struct reset_control *rst;
446
447 const struct tegra_xusb_padctl_soc *soc;
448
449 struct tegra_xusb_pad *pcie;
450 struct tegra_xusb_pad *sata;
451 struct tegra_xusb_pad *ulpi;
452 struct tegra_xusb_pad *usb2;
453 struct tegra_xusb_pad *hsic;
454
455 struct list_head ports;
456 struct list_head lanes;
457 struct list_head pads;
458
459 unsigned int enable;
460
461 struct clk *clk;
462
463 struct regulator_bulk_data *supplies;
464};
465
466static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
467 unsigned long offset)
468{
469 dev_dbg(padctl->dev, "%08lx < %08x\n", offset, value);
470 writel(value, padctl->regs + offset);
471}
472
473static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
474 unsigned long offset)
475{
476 u32 value = readl(padctl->regs + offset);
477 dev_dbg(padctl->dev, "%08lx > %08x\n", offset, value);
478 return value;
479}
480
481static inline u32 padctl_readl_poll(struct tegra_xusb_padctl *padctl,
482 unsigned long offset, u32 val, u32 mask,
483 int us)
484{
485 u32 regval;
486 int err;
487
488 err = readl_poll_timeout(padctl->regs + offset, regval,
489 (regval & mask) == val, 1, us);
490 if (err) {
491 dev_err(padctl->dev, "%08lx poll timeout > %08x\n", offset,
492 regval);
493 }
494
495 return err;
496}
497
498struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl,
499 const char *name,
500 unsigned int index);
501
502#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
503extern const struct tegra_xusb_padctl_soc tegra124_xusb_padctl_soc;
504#endif
505#if defined(CONFIG_ARCH_TEGRA_210_SOC)
506extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc;
507#endif
508#if defined(CONFIG_ARCH_TEGRA_186_SOC)
509extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc;
510#endif
511#if defined(CONFIG_ARCH_TEGRA_194_SOC)
512extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
513#endif
514#if defined(CONFIG_ARCH_TEGRA_234_SOC)
515extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc;
516#endif
517
518#endif /* __PHY_TEGRA_XUSB_H */