projects/linux·blob master · refs

2007 lines · 49.2 KiB

1/*
2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/list.h>
19#include <linux/interrupt.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/seq_file.h>
24
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29
30#include <linux/platform_data/pinctrl-single.h>
31
32#include "core.h"
33#include "devicetree.h"
34#include "pinconf.h"
35#include "pinmux.h"
36
37#define DRIVER_NAME "pinctrl-single"
38#define PCS_OFF_DISABLED ~0U
39
40/**
41 * struct pcs_func_vals - mux function register offset and value pair
42 * @reg: register virtual address
43 * @val: register value
44 * @mask: mask
45 */
46struct pcs_func_vals {
47 void __iomem *reg;
48 unsigned val;
49 unsigned mask;
50};
51
52/**
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
54 * and value, enable, disable, mask
55 * @param: config parameter
56 * @val: user input bits in the pinconf register
57 * @enable: enable bits in the pinconf register
58 * @disable: disable bits in the pinconf register
59 * @mask: mask bits in the register value
60 */
61struct pcs_conf_vals {
62 enum pin_config_param param;
63 unsigned val;
64 unsigned enable;
65 unsigned disable;
66 unsigned mask;
67};
68
69/**
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
71 * @name: property name in DTS file
72 * @param: config parameter
73 */
74struct pcs_conf_type {
75 const char *name;
76 enum pin_config_param param;
77};
78
79/**
80 * struct pcs_function - pinctrl function
81 * @name: pinctrl function name
82 * @vals: register and vals array
83 * @nvals: number of entries in vals array
84 * @conf: array of pin configurations
85 * @nconfs: number of pin configurations available
86 * @node: list node
87 */
88struct pcs_function {
89 const char *name;
90 struct pcs_func_vals *vals;
91 unsigned nvals;
92 struct pcs_conf_vals *conf;
93 int nconfs;
94 struct list_head node;
95};
96
97/**
98 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
99 * @offset: offset base of pins
100 * @npins: number pins with the same mux value of gpio function
101 * @gpiofunc: mux value of gpio function
102 * @node: list node
103 */
104struct pcs_gpiofunc_range {
105 unsigned offset;
106 unsigned npins;
107 unsigned gpiofunc;
108 struct list_head node;
109};
110
111/**
112 * struct pcs_data - wrapper for data needed by pinctrl framework
113 * @pa: pindesc array
114 * @cur: index to current element
115 *
116 * REVISIT: We should be able to drop this eventually by adding
117 * support for registering pins individually in the pinctrl
118 * framework for those drivers that don't need a static array.
119 */
120struct pcs_data {
121 struct pinctrl_pin_desc *pa;
122 int cur;
123};
124
125/**
126 * struct pcs_soc_data - SoC specific settings
127 * @flags: initial SoC specific PCS_FEAT_xxx values
128 * @irq: optional interrupt for the controller
129 * @irq_enable_mask: optional SoC specific interrupt enable mask
130 * @irq_status_mask: optional SoC specific interrupt status mask
131 * @rearm: optional SoC specific wake-up rearm function
132 */
133struct pcs_soc_data {
134 unsigned flags;
135 int irq;
136 unsigned irq_enable_mask;
137 unsigned irq_status_mask;
138 void (*rearm)(void);
139};
140
141/**
142 * struct pcs_device - pinctrl device instance
143 * @res: resources
144 * @base: virtual address of the controller
145 * @saved_vals: saved values for the controller
146 * @size: size of the ioremapped area
147 * @dev: device entry
148 * @np: device tree node
149 * @pctl: pin controller device
150 * @flags: mask of PCS_FEAT_xxx values
151 * @missing_nr_pinctrl_cells: for legacy binding, may go away
152 * @socdata: soc specific data
153 * @lock: spinlock for register access
154 * @mutex: mutex protecting the lists
155 * @width: bits per mux register
156 * @fmask: function register mask
157 * @fshift: function register shift
158 * @foff: value to turn mux off
159 * @fmax: max number of functions in fmask
160 * @bits_per_mux: number of bits per mux
161 * @bits_per_pin: number of bits per pin
162 * @pins: physical pins on the SoC
163 * @gpiofuncs: list of gpio functions
164 * @irqs: list of interrupt registers
165 * @chip: chip container for this instance
166 * @domain: IRQ domain for this instance
167 * @desc: pin controller descriptor
168 * @read: register read function to use
169 * @write: register write function to use
170 */
171struct pcs_device {
172 struct resource *res;
173 void __iomem *base;
174 void *saved_vals;
175 unsigned size;
176 struct device *dev;
177 struct device_node *np;
178 struct pinctrl_dev *pctl;
179 unsigned flags;
180#define PCS_CONTEXT_LOSS_OFF (1 << 3)
181#define PCS_QUIRK_SHARED_IRQ (1 << 2)
182#define PCS_FEAT_IRQ (1 << 1)
183#define PCS_FEAT_PINCONF (1 << 0)
184 struct property *missing_nr_pinctrl_cells;
185 struct pcs_soc_data socdata;
186 raw_spinlock_t lock;
187 struct mutex mutex;
188 unsigned width;
189 unsigned fmask;
190 unsigned fshift;
191 unsigned foff;
192 unsigned fmax;
193 bool bits_per_mux;
194 unsigned bits_per_pin;
195 struct pcs_data pins;
196 struct list_head gpiofuncs;
197 struct list_head irqs;
198 struct irq_chip chip;
199 struct irq_domain *domain;
200 struct pinctrl_desc desc;
201 unsigned (*read)(void __iomem *reg);
202 void (*write)(unsigned val, void __iomem *reg);
203};
204
205#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
206#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
207#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
208
209static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
210 unsigned long *config);
211static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
212 unsigned long *configs, unsigned num_configs);
213
214static enum pin_config_param pcs_bias[] = {
215 PIN_CONFIG_BIAS_PULL_DOWN,
216 PIN_CONFIG_BIAS_PULL_UP,
217};
218
219/*
220 * This lock class tells lockdep that irqchip core that this single
221 * pinctrl can be in a different category than its parents, so it won't
222 * report false recursion.
223 */
224static struct lock_class_key pcs_lock_class;
225
226/* Class for the IRQ request mutex */
227static struct lock_class_key pcs_request_class;
228
229/*
230 * REVISIT: Reads and writes could eventually use regmap or something
231 * generic. But at least on omaps, some mux registers are performance
232 * critical as they may need to be remuxed every time before and after
233 * idle. Adding tests for register access width for every read and
234 * write like regmap is doing is not desired, and caching the registers
235 * does not help in this case.
236 */
237
238static unsigned int pcs_readb(void __iomem *reg)
239{
240 return readb(reg);
241}
242
243static unsigned int pcs_readw(void __iomem *reg)
244{
245 return readw(reg);
246}
247
248static unsigned int pcs_readl(void __iomem *reg)
249{
250 return readl(reg);
251}
252
253static void pcs_writeb(unsigned int val, void __iomem *reg)
254{
255 writeb(val, reg);
256}
257
258static void pcs_writew(unsigned int val, void __iomem *reg)
259{
260 writew(val, reg);
261}
262
263static void pcs_writel(unsigned int val, void __iomem *reg)
264{
265 writel(val, reg);
266}
267
268static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
269 unsigned int pin)
270{
271 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
272
273 if (pcs->bits_per_mux) {
274 unsigned int pin_offset_bytes;
275
276 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
277 return (pin_offset_bytes / mux_bytes) * mux_bytes;
278 }
279
280 return pin * mux_bytes;
281}
282
283static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
284 unsigned int pin)
285{
286 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
287}
288
289static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
290 struct seq_file *s,
291 unsigned pin)
292{
293 struct pcs_device *pcs;
294 unsigned int val;
295 unsigned long offset;
296 size_t pa;
297
298 pcs = pinctrl_dev_get_drvdata(pctldev);
299
300 offset = pcs_pin_reg_offset_get(pcs, pin);
301 val = pcs->read(pcs->base + offset);
302
303 if (pcs->bits_per_mux)
304 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
305
306 pa = pcs->res->start + offset;
307
308 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
309}
310
311static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
312 struct pinctrl_map *map, unsigned num_maps)
313{
314 struct pcs_device *pcs;
315
316 pcs = pinctrl_dev_get_drvdata(pctldev);
317 devm_kfree(pcs->dev, map);
318}
319
320static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
321 struct device_node *np_config,
322 struct pinctrl_map **map, unsigned *num_maps);
323
324static const struct pinctrl_ops pcs_pinctrl_ops = {
325 .get_groups_count = pinctrl_generic_get_group_count,
326 .get_group_name = pinctrl_generic_get_group_name,
327 .get_group_pins = pinctrl_generic_get_group_pins,
328 .pin_dbg_show = pcs_pin_dbg_show,
329 .dt_node_to_map = pcs_dt_node_to_map,
330 .dt_free_map = pcs_dt_free_map,
331};
332
333static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
334 struct pcs_function **func)
335{
336 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
337 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
338 const struct pinctrl_setting_mux *setting;
339 const struct function_desc *function;
340 unsigned fselector;
341
342 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
343 setting = pdesc->mux_setting;
344 if (!setting)
345 return -ENOTSUPP;
346 fselector = setting->func;
347 function = pinmux_generic_get_function(pctldev, fselector);
348 if (!function)
349 return -EINVAL;
350 *func = function->data;
351 if (!(*func)) {
352 dev_err(pcs->dev, "%s could not find function%i\n",
353 __func__, fselector);
354 return -ENOTSUPP;
355 }
356 return 0;
357}
358
359static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
360 unsigned group)
361{
362 struct pcs_device *pcs;
363 const struct function_desc *function;
364 struct pcs_function *func;
365 int i;
366
367 pcs = pinctrl_dev_get_drvdata(pctldev);
368 /* If function mask is null, needn't enable it. */
369 if (!pcs->fmask)
370 return 0;
371 function = pinmux_generic_get_function(pctldev, fselector);
372 if (!function)
373 return -EINVAL;
374 func = function->data;
375 if (!func)
376 return -EINVAL;
377
378 dev_dbg(pcs->dev, "enabling %s function%i\n",
379 func->name, fselector);
380
381 for (i = 0; i < func->nvals; i++) {
382 struct pcs_func_vals *vals;
383 unsigned long flags;
384 unsigned val, mask;
385
386 vals = &func->vals[i];
387 raw_spin_lock_irqsave(&pcs->lock, flags);
388 val = pcs->read(vals->reg);
389
390 if (pcs->bits_per_mux)
391 mask = vals->mask;
392 else
393 mask = pcs->fmask;
394
395 val &= ~mask;
396 val |= (vals->val & mask);
397 pcs->write(val, vals->reg);
398 raw_spin_unlock_irqrestore(&pcs->lock, flags);
399 }
400
401 return 0;
402}
403
404static int pcs_request_gpio(struct pinctrl_dev *pctldev,
405 struct pinctrl_gpio_range *range, unsigned pin)
406{
407 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
408 struct pcs_gpiofunc_range *frange = NULL;
409 struct list_head *pos, *tmp;
410 unsigned data;
411
412 /* If function mask is null, return directly. */
413 if (!pcs->fmask)
414 return -ENOTSUPP;
415
416 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
417 u32 offset;
418
419 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
420 if (pin >= frange->offset + frange->npins
421 || pin < frange->offset)
422 continue;
423
424 offset = pcs_pin_reg_offset_get(pcs, pin);
425
426 if (pcs->bits_per_mux) {
427 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
428
429 data = pcs->read(pcs->base + offset);
430 data &= ~(pcs->fmask << pin_shift);
431 data |= frange->gpiofunc << pin_shift;
432 pcs->write(data, pcs->base + offset);
433 } else {
434 data = pcs->read(pcs->base + offset);
435 data &= ~pcs->fmask;
436 data |= frange->gpiofunc;
437 pcs->write(data, pcs->base + offset);
438 }
439 break;
440 }
441 return 0;
442}
443
444static const struct pinmux_ops pcs_pinmux_ops = {
445 .get_functions_count = pinmux_generic_get_function_count,
446 .get_function_name = pinmux_generic_get_function_name,
447 .get_function_groups = pinmux_generic_get_function_groups,
448 .set_mux = pcs_set_mux,
449 .gpio_request_enable = pcs_request_gpio,
450};
451
452/* Clear BIAS value */
453static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
454{
455 unsigned long config;
456 int i;
457 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
458 config = pinconf_to_config_packed(pcs_bias[i], 0);
459 pcs_pinconf_set(pctldev, pin, &config, 1);
460 }
461}
462
463/*
464 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
465 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
466 */
467static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
468{
469 unsigned long config;
470 int i;
471
472 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
473 config = pinconf_to_config_packed(pcs_bias[i], 0);
474 if (!pcs_pinconf_get(pctldev, pin, &config))
475 goto out;
476 }
477 return true;
478out:
479 return false;
480}
481
482static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
483 unsigned pin, unsigned long *config)
484{
485 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
486 struct pcs_function *func;
487 enum pin_config_param param;
488 unsigned offset = 0, data = 0, i, j;
489 int ret;
490
491 ret = pcs_get_function(pctldev, pin, &func);
492 if (ret)
493 return ret;
494
495 for (i = 0; i < func->nconfs; i++) {
496 param = pinconf_to_config_param(*config);
497 if (param == PIN_CONFIG_BIAS_DISABLE) {
498 if (pcs_pinconf_bias_disable(pctldev, pin)) {
499 *config = 0;
500 return 0;
501 } else {
502 return -ENOTSUPP;
503 }
504 } else if (param != func->conf[i].param) {
505 continue;
506 }
507
508 offset = pin * (pcs->width / BITS_PER_BYTE);
509 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
510 switch (func->conf[i].param) {
511 /* 4 parameters */
512 case PIN_CONFIG_BIAS_PULL_DOWN:
513 case PIN_CONFIG_BIAS_PULL_UP:
514 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
515 if ((data != func->conf[i].enable) ||
516 (data == func->conf[i].disable))
517 return -ENOTSUPP;
518 *config = 0;
519 break;
520 /* 2 parameters */
521 case PIN_CONFIG_INPUT_SCHMITT:
522 for (j = 0; j < func->nconfs; j++) {
523 switch (func->conf[j].param) {
524 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
525 if (data != func->conf[j].enable)
526 return -ENOTSUPP;
527 break;
528 default:
529 break;
530 }
531 }
532 *config = data;
533 break;
534 case PIN_CONFIG_DRIVE_STRENGTH:
535 case PIN_CONFIG_SLEW_RATE:
536 case PIN_CONFIG_MODE_LOW_POWER:
537 case PIN_CONFIG_INPUT_ENABLE:
538 default:
539 *config = data;
540 break;
541 }
542 return 0;
543 }
544 return -ENOTSUPP;
545}
546
547static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
548 unsigned pin, unsigned long *configs,
549 unsigned num_configs)
550{
551 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
552 struct pcs_function *func;
553 unsigned offset = 0, shift = 0, i, data;
554 u32 arg;
555 int j, ret;
556 enum pin_config_param param;
557
558 ret = pcs_get_function(pctldev, pin, &func);
559 if (ret)
560 return ret;
561
562 for (j = 0; j < num_configs; j++) {
563 param = pinconf_to_config_param(configs[j]);
564
565 /* BIAS_DISABLE has no entry in the func->conf table */
566 if (param == PIN_CONFIG_BIAS_DISABLE) {
567 /* This just disables all bias entries */
568 pcs_pinconf_clear_bias(pctldev, pin);
569 continue;
570 }
571
572 for (i = 0; i < func->nconfs; i++) {
573 if (param != func->conf[i].param)
574 continue;
575
576 offset = pin * (pcs->width / BITS_PER_BYTE);
577 data = pcs->read(pcs->base + offset);
578 arg = pinconf_to_config_argument(configs[j]);
579 switch (param) {
580 /* 2 parameters */
581 case PIN_CONFIG_INPUT_SCHMITT:
582 case PIN_CONFIG_DRIVE_STRENGTH:
583 case PIN_CONFIG_SLEW_RATE:
584 case PIN_CONFIG_MODE_LOW_POWER:
585 case PIN_CONFIG_INPUT_ENABLE:
586 shift = ffs(func->conf[i].mask) - 1;
587 data &= ~func->conf[i].mask;
588 data |= (arg << shift) & func->conf[i].mask;
589 break;
590 /* 4 parameters */
591 case PIN_CONFIG_BIAS_PULL_DOWN:
592 case PIN_CONFIG_BIAS_PULL_UP:
593 if (arg) {
594 pcs_pinconf_clear_bias(pctldev, pin);
595 data = pcs->read(pcs->base + offset);
596 }
597 fallthrough;
598 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
599 data &= ~func->conf[i].mask;
600 if (arg)
601 data |= func->conf[i].enable;
602 else
603 data |= func->conf[i].disable;
604 break;
605 default:
606 return -ENOTSUPP;
607 }
608 pcs->write(data, pcs->base + offset);
609
610 break;
611 }
612 if (i >= func->nconfs)
613 return -ENOTSUPP;
614 } /* for each config */
615
616 return 0;
617}
618
619static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
620 unsigned group, unsigned long *config)
621{
622 unsigned long old = 0;
623 const unsigned *pins;
624 unsigned npins;
625 int i, ret;
626
627 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
628 if (ret)
629 return ret;
630 for (i = 0; i < npins; i++) {
631 if (pcs_pinconf_get(pctldev, pins[i], config))
632 return -ENOTSUPP;
633 /* configs do not match between two pins */
634 if (i && (old != *config))
635 return -ENOTSUPP;
636 old = *config;
637 }
638 return 0;
639}
640
641static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
642 unsigned group, unsigned long *configs,
643 unsigned num_configs)
644{
645 const unsigned *pins;
646 unsigned npins;
647 int i, ret;
648
649 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
650 if (ret)
651 return ret;
652 for (i = 0; i < npins; i++) {
653 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
654 return -ENOTSUPP;
655 }
656 return 0;
657}
658
659static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
660 struct seq_file *s, unsigned pin)
661{
662}
663
664static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
665 struct seq_file *s, unsigned selector)
666{
667}
668
669static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
670 struct seq_file *s,
671 unsigned long config)
672{
673 pinconf_generic_dump_config(pctldev, s, config);
674}
675
676static const struct pinconf_ops pcs_pinconf_ops = {
677 .pin_config_get = pcs_pinconf_get,
678 .pin_config_set = pcs_pinconf_set,
679 .pin_config_group_get = pcs_pinconf_group_get,
680 .pin_config_group_set = pcs_pinconf_group_set,
681 .pin_config_dbg_show = pcs_pinconf_dbg_show,
682 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
683 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
684 .is_generic = true,
685};
686
687/**
688 * pcs_add_pin() - add a pin to the static per controller pin array
689 * @pcs: pcs driver instance
690 * @offset: register offset from base
691 */
692static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
693{
694 struct pcs_soc_data *pcs_soc = &pcs->socdata;
695 struct pinctrl_pin_desc *pin;
696 int i;
697
698 i = pcs->pins.cur;
699 if (i >= pcs->desc.npins) {
700 dev_err(pcs->dev, "too many pins, max %i\n",
701 pcs->desc.npins);
702 return -ENOMEM;
703 }
704
705 if (pcs_soc->irq_enable_mask) {
706 unsigned val;
707
708 val = pcs->read(pcs->base + offset);
709 if (val & pcs_soc->irq_enable_mask) {
710 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
711 (unsigned long)pcs->res->start + offset, val);
712 val &= ~pcs_soc->irq_enable_mask;
713 pcs->write(val, pcs->base + offset);
714 }
715 }
716
717 pin = &pcs->pins.pa[i];
718 pin->number = i;
719 pcs->pins.cur++;
720
721 return i;
722}
723
724/**
725 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
726 * @pcs: pcs driver instance
727 *
728 * In case of errors, resources are freed in pcs_free_resources.
729 *
730 * If your hardware needs holes in the address space, then just set
731 * up multiple driver instances.
732 */
733static int pcs_allocate_pin_table(struct pcs_device *pcs)
734{
735 int mux_bytes, nr_pins, i;
736
737 mux_bytes = pcs->width / BITS_PER_BYTE;
738
739 if (pcs->bits_per_mux && pcs->fmask) {
740 pcs->bits_per_pin = fls(pcs->fmask);
741 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
742 } else {
743 nr_pins = pcs->size / mux_bytes;
744 }
745
746 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
747 pcs->pins.pa = devm_kcalloc(pcs->dev,
748 nr_pins, sizeof(*pcs->pins.pa),
749 GFP_KERNEL);
750 if (!pcs->pins.pa)
751 return -ENOMEM;
752
753 pcs->desc.pins = pcs->pins.pa;
754 pcs->desc.npins = nr_pins;
755
756 for (i = 0; i < pcs->desc.npins; i++) {
757 unsigned offset;
758 int res;
759
760 offset = pcs_pin_reg_offset_get(pcs, i);
761 res = pcs_add_pin(pcs, offset);
762 if (res < 0) {
763 dev_err(pcs->dev, "error adding pins: %i\n", res);
764 return res;
765 }
766 }
767
768 return 0;
769}
770
771/**
772 * pcs_add_function() - adds a new function to the function list
773 * @pcs: pcs driver instance
774 * @fcn: new function allocated
775 * @name: name of the function
776 * @vals: array of mux register value pairs used by the function
777 * @nvals: number of mux register value pairs
778 * @pgnames: array of pingroup names for the function
779 * @npgnames: number of pingroup names
780 *
781 * Caller must take care of locking.
782 */
783static int pcs_add_function(struct pcs_device *pcs,
784 struct pcs_function **fcn,
785 const char *name,
786 struct pcs_func_vals *vals,
787 unsigned int nvals,
788 const char **pgnames,
789 unsigned int npgnames)
790{
791 struct pcs_function *function;
792 int selector;
793
794 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
795 if (!function)
796 return -ENOMEM;
797
798 function->vals = vals;
799 function->nvals = nvals;
800 function->name = name;
801
802 selector = pinmux_generic_add_function(pcs->pctl, name,
803 pgnames, npgnames,
804 function);
805 if (selector < 0) {
806 devm_kfree(pcs->dev, function);
807 *fcn = NULL;
808 } else {
809 *fcn = function;
810 }
811
812 return selector;
813}
814
815/**
816 * pcs_get_pin_by_offset() - get a pin index based on the register offset
817 * @pcs: pcs driver instance
818 * @offset: register offset from the base
819 *
820 * Note that this is OK as long as the pins are in a static array.
821 */
822static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
823{
824 unsigned index;
825
826 if (offset >= pcs->size) {
827 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
828 offset, pcs->size);
829 return -EINVAL;
830 }
831
832 if (pcs->bits_per_mux)
833 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
834 else
835 index = offset / (pcs->width / BITS_PER_BYTE);
836
837 return index;
838}
839
840/*
841 * check whether data matches enable bits or disable bits
842 * Return value: 1 for matching enable bits, 0 for matching disable bits,
843 * and negative value for matching failure.
844 */
845static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
846{
847 int ret = -EINVAL;
848
849 if (data == enable)
850 ret = 1;
851 else if (data == disable)
852 ret = 0;
853 return ret;
854}
855
856static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
857 unsigned value, unsigned enable, unsigned disable,
858 unsigned mask)
859{
860 (*conf)->param = param;
861 (*conf)->val = value;
862 (*conf)->enable = enable;
863 (*conf)->disable = disable;
864 (*conf)->mask = mask;
865 (*conf)++;
866}
867
868static void add_setting(unsigned long **setting, enum pin_config_param param,
869 unsigned arg)
870{
871 **setting = pinconf_to_config_packed(param, arg);
872 (*setting)++;
873}
874
875/* add pinconf setting with 2 parameters */
876static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
877 const char *name, enum pin_config_param param,
878 struct pcs_conf_vals **conf, unsigned long **settings)
879{
880 unsigned value[2], shift;
881 int ret;
882
883 ret = of_property_read_u32_array(np, name, value, 2);
884 if (ret)
885 return;
886 /* set value & mask */
887 value[0] &= value[1];
888 shift = ffs(value[1]) - 1;
889 /* skip enable & disable */
890 add_config(conf, param, value[0], 0, 0, value[1]);
891 add_setting(settings, param, value[0] >> shift);
892}
893
894/* add pinconf setting with 4 parameters */
895static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
896 const char *name, enum pin_config_param param,
897 struct pcs_conf_vals **conf, unsigned long **settings)
898{
899 unsigned value[4];
900 int ret;
901
902 /* value to set, enable, disable, mask */
903 ret = of_property_read_u32_array(np, name, value, 4);
904 if (ret)
905 return;
906 if (!value[3]) {
907 dev_err(pcs->dev, "mask field of the property can't be 0\n");
908 return;
909 }
910 value[0] &= value[3];
911 value[1] &= value[3];
912 value[2] &= value[3];
913 ret = pcs_config_match(value[0], value[1], value[2]);
914 if (ret < 0)
915 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
916 add_config(conf, param, value[0], value[1], value[2], value[3]);
917 add_setting(settings, param, ret);
918}
919
920static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
921 struct pcs_function *func,
922 struct pinctrl_map **map)
923
924{
925 struct pinctrl_map *m = *map;
926 int i = 0, nconfs = 0;
927 unsigned long *settings = NULL, *s = NULL;
928 struct pcs_conf_vals *conf = NULL;
929 static const struct pcs_conf_type prop2[] = {
930 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
931 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
932 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, },
933 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
934 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
935 };
936 static const struct pcs_conf_type prop4[] = {
937 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
938 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
939 { "pinctrl-single,input-schmitt-enable",
940 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
941 };
942
943 /* If pinconf isn't supported, don't parse properties in below. */
944 if (!PCS_HAS_PINCONF)
945 return -ENOTSUPP;
946
947 /* cacluate how much properties are supported in current node */
948 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
949 if (of_property_present(np, prop2[i].name))
950 nconfs++;
951 }
952 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
953 if (of_property_present(np, prop4[i].name))
954 nconfs++;
955 }
956 if (!nconfs)
957 return -ENOTSUPP;
958
959 func->conf = devm_kcalloc(pcs->dev,
960 nconfs, sizeof(struct pcs_conf_vals),
961 GFP_KERNEL);
962 if (!func->conf)
963 return -ENOMEM;
964 func->nconfs = nconfs;
965 conf = &(func->conf[0]);
966 m++;
967 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
968 GFP_KERNEL);
969 if (!settings)
970 return -ENOMEM;
971 s = &settings[0];
972
973 for (i = 0; i < ARRAY_SIZE(prop2); i++)
974 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
975 &conf, &s);
976 for (i = 0; i < ARRAY_SIZE(prop4); i++)
977 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
978 &conf, &s);
979 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
980 m->data.configs.group_or_pin = np->name;
981 m->data.configs.configs = settings;
982 m->data.configs.num_configs = nconfs;
983 return 0;
984}
985
986/**
987 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
988 * @pcs: pinctrl driver instance
989 * @np: device node of the mux entry
990 * @map: map entry
991 * @num_maps: number of map
992 * @pgnames: pingroup names
993 *
994 * Note that this binding currently supports only sets of one register + value.
995 *
996 * Also note that this driver tries to avoid understanding pin and function
997 * names because of the extra bloat they would cause especially in the case of
998 * a large number of pins. This driver just sets what is specified for the board
999 * in the .dts file. Further user space debugging tools can be developed to
1000 * decipher the pin and function names using debugfs.
1001 *
1002 * If you are concerned about the boot time, set up the static pins in
1003 * the bootloader, and only set up selected pins as device tree entries.
1004 */
1005static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1006 struct device_node *np,
1007 struct pinctrl_map **map,
1008 unsigned *num_maps,
1009 const char **pgnames)
1010{
1011 const char *name = "pinctrl-single,pins";
1012 struct pcs_func_vals *vals;
1013 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1014 struct pcs_function *function = NULL;
1015
1016 rows = pinctrl_count_index_with_args(np, name);
1017 if (rows <= 0) {
1018 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1019 return -EINVAL;
1020 }
1021
1022 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1023 if (!vals)
1024 return -ENOMEM;
1025
1026 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1027 if (!pins)
1028 goto free_vals;
1029
1030 for (i = 0; i < rows; i++) {
1031 struct of_phandle_args pinctrl_spec;
1032 unsigned int offset;
1033 int pin;
1034
1035 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1036 if (res)
1037 return res;
1038
1039 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1040 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1041 pinctrl_spec.args_count);
1042 break;
1043 }
1044
1045 offset = pinctrl_spec.args[0];
1046 vals[found].reg = pcs->base + offset;
1047
1048 switch (pinctrl_spec.args_count) {
1049 case 2:
1050 vals[found].val = pinctrl_spec.args[1];
1051 break;
1052 case 3:
1053 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1054 break;
1055 }
1056
1057 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1058 pinctrl_spec.np, offset, vals[found].val);
1059
1060 pin = pcs_get_pin_by_offset(pcs, offset);
1061 if (pin < 0) {
1062 dev_err(pcs->dev,
1063 "could not add functions for %pOFn %ux\n",
1064 np, offset);
1065 break;
1066 }
1067 pins[found++] = pin;
1068 }
1069
1070 pgnames[0] = np->name;
1071 mutex_lock(&pcs->mutex);
1072 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1073 pgnames, 1);
1074 if (fsel < 0) {
1075 res = fsel;
1076 goto free_pins;
1077 }
1078
1079 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1080 if (gsel < 0) {
1081 res = gsel;
1082 goto free_function;
1083 }
1084
1085 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1086 (*map)->data.mux.group = np->name;
1087 (*map)->data.mux.function = np->name;
1088
1089 if (PCS_HAS_PINCONF && function) {
1090 res = pcs_parse_pinconf(pcs, np, function, map);
1091 if (res == 0)
1092 *num_maps = 2;
1093 else if (res == -ENOTSUPP)
1094 *num_maps = 1;
1095 else
1096 goto free_pingroups;
1097 } else {
1098 *num_maps = 1;
1099 }
1100 mutex_unlock(&pcs->mutex);
1101
1102 return 0;
1103
1104free_pingroups:
1105 pinctrl_generic_remove_group(pcs->pctl, gsel);
1106 *num_maps = 1;
1107free_function:
1108 pinmux_generic_remove_function(pcs->pctl, fsel);
1109free_pins:
1110 mutex_unlock(&pcs->mutex);
1111 devm_kfree(pcs->dev, pins);
1112
1113free_vals:
1114 devm_kfree(pcs->dev, vals);
1115
1116 return res;
1117}
1118
1119static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1120 struct device_node *np,
1121 struct pinctrl_map **map,
1122 unsigned *num_maps,
1123 const char **pgnames)
1124{
1125 const char *name = "pinctrl-single,bits";
1126 struct pcs_func_vals *vals;
1127 int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
1128 int npins_in_row;
1129 struct pcs_function *function = NULL;
1130
1131 rows = pinctrl_count_index_with_args(np, name);
1132 if (rows <= 0) {
1133 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1134 return -EINVAL;
1135 }
1136
1137 if (PCS_HAS_PINCONF) {
1138 dev_err(pcs->dev, "pinconf not supported\n");
1139 return -ENOTSUPP;
1140 }
1141
1142 npins_in_row = pcs->width / pcs->bits_per_pin;
1143
1144 vals = devm_kzalloc(pcs->dev,
1145 array3_size(rows, npins_in_row, sizeof(*vals)),
1146 GFP_KERNEL);
1147 if (!vals)
1148 return -ENOMEM;
1149
1150 pins = devm_kzalloc(pcs->dev,
1151 array3_size(rows, npins_in_row, sizeof(*pins)),
1152 GFP_KERNEL);
1153 if (!pins)
1154 goto free_vals;
1155
1156 for (i = 0; i < rows; i++) {
1157 struct of_phandle_args pinctrl_spec;
1158 unsigned offset, val;
1159 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1160 unsigned pin_num_from_lsb;
1161 int pin;
1162
1163 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1164 if (res)
1165 return res;
1166
1167 if (pinctrl_spec.args_count < 3) {
1168 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1169 pinctrl_spec.args_count);
1170 break;
1171 }
1172
1173 /* Index plus two value cells */
1174 offset = pinctrl_spec.args[0];
1175 val = pinctrl_spec.args[1];
1176 mask = pinctrl_spec.args[2];
1177
1178 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1179 pinctrl_spec.np, offset, val, mask);
1180
1181 /* Parse pins in each row from LSB */
1182 while (mask) {
1183 bit_pos = __ffs(mask);
1184 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1185 mask_pos = ((pcs->fmask) << bit_pos);
1186 val_pos = val & mask_pos;
1187 submask = mask & mask_pos;
1188
1189 if ((mask & mask_pos) == 0) {
1190 dev_err(pcs->dev,
1191 "Invalid mask for %pOFn at 0x%x\n",
1192 np, offset);
1193 break;
1194 }
1195
1196 mask &= ~mask_pos;
1197
1198 if (submask != mask_pos) {
1199 dev_warn(pcs->dev,
1200 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1201 submask, np, offset);
1202 continue;
1203 }
1204
1205 vals[found].mask = submask;
1206 vals[found].reg = pcs->base + offset;
1207 vals[found].val = val_pos;
1208
1209 pin = pcs_get_pin_by_offset(pcs, offset);
1210 if (pin < 0) {
1211 dev_err(pcs->dev,
1212 "could not add functions for %pOFn %ux\n",
1213 np, offset);
1214 break;
1215 }
1216 pins[found++] = pin + pin_num_from_lsb;
1217 }
1218 }
1219
1220 pgnames[0] = np->name;
1221 mutex_lock(&pcs->mutex);
1222 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1223 pgnames, 1);
1224 if (fsel < 0) {
1225 res = fsel;
1226 goto free_pins;
1227 }
1228
1229 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1230 if (res < 0)
1231 goto free_function;
1232
1233 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1234 (*map)->data.mux.group = np->name;
1235 (*map)->data.mux.function = np->name;
1236
1237 *num_maps = 1;
1238 mutex_unlock(&pcs->mutex);
1239
1240 return 0;
1241
1242free_function:
1243 pinmux_generic_remove_function(pcs->pctl, fsel);
1244free_pins:
1245 mutex_unlock(&pcs->mutex);
1246 devm_kfree(pcs->dev, pins);
1247
1248free_vals:
1249 devm_kfree(pcs->dev, vals);
1250
1251 return res;
1252}
1253/**
1254 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1255 * @pctldev: pinctrl instance
1256 * @np_config: device tree pinmux entry
1257 * @map: array of map entries
1258 * @num_maps: number of maps
1259 */
1260static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1261 struct device_node *np_config,
1262 struct pinctrl_map **map, unsigned *num_maps)
1263{
1264 struct pcs_device *pcs;
1265 const char **pgnames;
1266 int ret;
1267
1268 pcs = pinctrl_dev_get_drvdata(pctldev);
1269
1270 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1271 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1272 if (!*map)
1273 return -ENOMEM;
1274
1275 *num_maps = 0;
1276
1277 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1278 if (!pgnames) {
1279 ret = -ENOMEM;
1280 goto free_map;
1281 }
1282
1283 if (pcs->bits_per_mux) {
1284 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1285 num_maps, pgnames);
1286 if (ret < 0) {
1287 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1288 np_config);
1289 goto free_pgnames;
1290 }
1291 } else {
1292 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1293 num_maps, pgnames);
1294 if (ret < 0) {
1295 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1296 np_config);
1297 goto free_pgnames;
1298 }
1299 }
1300
1301 return 0;
1302
1303free_pgnames:
1304 devm_kfree(pcs->dev, pgnames);
1305free_map:
1306 devm_kfree(pcs->dev, *map);
1307
1308 return ret;
1309}
1310
1311/**
1312 * pcs_irq_free() - free interrupt
1313 * @pcs: pcs driver instance
1314 */
1315static void pcs_irq_free(struct pcs_device *pcs)
1316{
1317 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1318
1319 if (pcs_soc->irq < 0)
1320 return;
1321
1322 if (pcs->domain)
1323 irq_domain_remove(pcs->domain);
1324
1325 if (PCS_QUIRK_HAS_SHARED_IRQ)
1326 free_irq(pcs_soc->irq, pcs_soc);
1327 else
1328 irq_set_chained_handler(pcs_soc->irq, NULL);
1329}
1330
1331/**
1332 * pcs_free_resources() - free memory used by this driver
1333 * @pcs: pcs driver instance
1334 */
1335static void pcs_free_resources(struct pcs_device *pcs)
1336{
1337 pcs_irq_free(pcs);
1338
1339#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1340 if (pcs->missing_nr_pinctrl_cells)
1341 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1342#endif
1343}
1344
1345static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1346{
1347 const char *propname = "pinctrl-single,gpio-range";
1348 const char *cellname = "#pinctrl-single,gpio-range-cells";
1349 struct of_phandle_args gpiospec;
1350 struct pcs_gpiofunc_range *range;
1351 int ret, i;
1352
1353 for (i = 0; ; i++) {
1354 ret = of_parse_phandle_with_args(node, propname, cellname,
1355 i, &gpiospec);
1356 /* Do not treat it as error. Only treat it as end condition. */
1357 if (ret) {
1358 ret = 0;
1359 break;
1360 }
1361 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1362 if (!range) {
1363 of_node_put(gpiospec.np);
1364 ret = -ENOMEM;
1365 break;
1366 }
1367 range->offset = gpiospec.args[0];
1368 range->npins = gpiospec.args[1];
1369 range->gpiofunc = gpiospec.args[2];
1370 mutex_lock(&pcs->mutex);
1371 list_add_tail(&range->node, &pcs->gpiofuncs);
1372 mutex_unlock(&pcs->mutex);
1373 of_node_put(gpiospec.np);
1374 }
1375 return ret;
1376}
1377
1378/**
1379 * struct pcs_interrupt
1380 * @reg: virtual address of interrupt register
1381 * @hwirq: hardware irq number
1382 * @irq: virtual irq number
1383 * @node: list node
1384 */
1385struct pcs_interrupt {
1386 void __iomem *reg;
1387 irq_hw_number_t hwirq;
1388 unsigned int irq;
1389 struct list_head node;
1390};
1391
1392/**
1393 * pcs_irq_set() - enables or disables an interrupt
1394 * @pcs_soc: SoC specific settings
1395 * @irq: interrupt
1396 * @enable: enable or disable the interrupt
1397 *
1398 * Note that this currently assumes one interrupt per pinctrl
1399 * register that is typically used for wake-up events.
1400 */
1401static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1402 int irq, const bool enable)
1403{
1404 struct pcs_device *pcs;
1405 struct list_head *pos;
1406 unsigned mask;
1407
1408 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1409 list_for_each(pos, &pcs->irqs) {
1410 struct pcs_interrupt *pcswi;
1411 unsigned soc_mask;
1412
1413 pcswi = list_entry(pos, struct pcs_interrupt, node);
1414 if (irq != pcswi->irq)
1415 continue;
1416
1417 soc_mask = pcs_soc->irq_enable_mask;
1418 raw_spin_lock(&pcs->lock);
1419 mask = pcs->read(pcswi->reg);
1420 if (enable)
1421 mask |= soc_mask;
1422 else
1423 mask &= ~soc_mask;
1424 pcs->write(mask, pcswi->reg);
1425
1426 /* flush posted write */
1427 mask = pcs->read(pcswi->reg);
1428 raw_spin_unlock(&pcs->lock);
1429 }
1430
1431 if (pcs_soc->rearm)
1432 pcs_soc->rearm();
1433}
1434
1435/**
1436 * pcs_irq_mask() - mask pinctrl interrupt
1437 * @d: interrupt data
1438 */
1439static void pcs_irq_mask(struct irq_data *d)
1440{
1441 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1442
1443 pcs_irq_set(pcs_soc, d->irq, false);
1444}
1445
1446/**
1447 * pcs_irq_unmask() - unmask pinctrl interrupt
1448 * @d: interrupt data
1449 */
1450static void pcs_irq_unmask(struct irq_data *d)
1451{
1452 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1453
1454 pcs_irq_set(pcs_soc, d->irq, true);
1455}
1456
1457/**
1458 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1459 * @d: interrupt data
1460 * @state: wake-up state
1461 *
1462 * Note that this should be called only for suspend and resume.
1463 * For runtime PM, the wake-up events should be enabled by default.
1464 */
1465static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1466{
1467 if (state)
1468 pcs_irq_unmask(d);
1469 else
1470 pcs_irq_mask(d);
1471
1472 return 0;
1473}
1474
1475/**
1476 * pcs_irq_handle() - common interrupt handler
1477 * @pcs_soc: SoC specific settings
1478 *
1479 * Note that this currently assumes we have one interrupt bit per
1480 * mux register. This interrupt is typically used for wake-up events.
1481 * For more complex interrupts different handlers can be specified.
1482 */
1483static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1484{
1485 struct pcs_device *pcs;
1486 struct list_head *pos;
1487 int count = 0;
1488
1489 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1490 list_for_each(pos, &pcs->irqs) {
1491 struct pcs_interrupt *pcswi;
1492 unsigned mask;
1493
1494 pcswi = list_entry(pos, struct pcs_interrupt, node);
1495 raw_spin_lock(&pcs->lock);
1496 mask = pcs->read(pcswi->reg);
1497 raw_spin_unlock(&pcs->lock);
1498 if (mask & pcs_soc->irq_status_mask) {
1499 generic_handle_domain_irq(pcs->domain,
1500 pcswi->hwirq);
1501 count++;
1502 }
1503 }
1504
1505 return count;
1506}
1507
1508/**
1509 * pcs_irq_handler() - handler for the shared interrupt case
1510 * @irq: interrupt
1511 * @d: data
1512 *
1513 * Use this for cases where multiple instances of
1514 * pinctrl-single share a single interrupt like on omaps.
1515 */
1516static irqreturn_t pcs_irq_handler(int irq, void *d)
1517{
1518 struct pcs_soc_data *pcs_soc = d;
1519
1520 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1521}
1522
1523/**
1524 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1525 * @desc: interrupt descriptor
1526 *
1527 * Use this if you have a separate interrupt for each
1528 * pinctrl-single instance.
1529 */
1530static void pcs_irq_chain_handler(struct irq_desc *desc)
1531{
1532 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1533 struct irq_chip *chip;
1534
1535 chip = irq_desc_get_chip(desc);
1536 chained_irq_enter(chip, desc);
1537 pcs_irq_handle(pcs_soc);
1538 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1539 chained_irq_exit(chip, desc);
1540}
1541
1542static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1543 irq_hw_number_t hwirq)
1544{
1545 struct pcs_soc_data *pcs_soc = d->host_data;
1546 struct pcs_device *pcs;
1547 struct pcs_interrupt *pcswi;
1548
1549 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1550 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1551 if (!pcswi)
1552 return -ENOMEM;
1553
1554 pcswi->reg = pcs->base + hwirq;
1555 pcswi->hwirq = hwirq;
1556 pcswi->irq = irq;
1557
1558 mutex_lock(&pcs->mutex);
1559 list_add_tail(&pcswi->node, &pcs->irqs);
1560 mutex_unlock(&pcs->mutex);
1561
1562 irq_set_chip_data(irq, pcs_soc);
1563 irq_set_chip_and_handler(irq, &pcs->chip,
1564 handle_level_irq);
1565 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1566 irq_set_noprobe(irq);
1567
1568 return 0;
1569}
1570
1571static const struct irq_domain_ops pcs_irqdomain_ops = {
1572 .map = pcs_irqdomain_map,
1573 .xlate = irq_domain_xlate_onecell,
1574};
1575
1576/**
1577 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1578 * @pcs: pcs driver instance
1579 * @np: device node pointer
1580 */
1581static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1582 struct device_node *np)
1583{
1584 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1585 const char *name = "pinctrl";
1586 int num_irqs;
1587
1588 if (!pcs_soc->irq_enable_mask ||
1589 !pcs_soc->irq_status_mask) {
1590 pcs_soc->irq = -1;
1591 return -EINVAL;
1592 }
1593
1594 INIT_LIST_HEAD(&pcs->irqs);
1595 pcs->chip.name = name;
1596 pcs->chip.irq_ack = pcs_irq_mask;
1597 pcs->chip.irq_mask = pcs_irq_mask;
1598 pcs->chip.irq_unmask = pcs_irq_unmask;
1599 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1600
1601 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1602 int res;
1603
1604 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1605 IRQF_SHARED | IRQF_NO_SUSPEND |
1606 IRQF_NO_THREAD,
1607 name, pcs_soc);
1608 if (res) {
1609 pcs_soc->irq = -1;
1610 return res;
1611 }
1612 } else {
1613 irq_set_chained_handler_and_data(pcs_soc->irq,
1614 pcs_irq_chain_handler,
1615 pcs_soc);
1616 }
1617
1618 /*
1619 * We can use the register offset as the hardirq
1620 * number as irq_domain_create_simple maps them lazily.
1621 * This way we can easily support more than one
1622 * interrupt per function if needed.
1623 */
1624 num_irqs = pcs->size;
1625
1626 pcs->domain = irq_domain_create_simple(of_fwnode_handle(np),
1627 num_irqs, 0,
1628 &pcs_irqdomain_ops,
1629 pcs_soc);
1630 if (!pcs->domain) {
1631 pcs_irq_free(pcs);
1632 pcs_soc->irq = -1;
1633 return -EINVAL;
1634 }
1635
1636 return 0;
1637}
1638
1639static int pcs_save_context(struct pcs_device *pcs)
1640{
1641 int i, mux_bytes;
1642 u64 *regsl;
1643 u32 *regsw;
1644 u16 *regshw;
1645
1646 mux_bytes = pcs->width / BITS_PER_BYTE;
1647
1648 if (!pcs->saved_vals) {
1649 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1650 if (!pcs->saved_vals)
1651 return -ENOMEM;
1652 }
1653
1654 switch (pcs->width) {
1655 case 64:
1656 regsl = pcs->saved_vals;
1657 for (i = 0; i < pcs->size; i += mux_bytes)
1658 *regsl++ = pcs->read(pcs->base + i);
1659 break;
1660 case 32:
1661 regsw = pcs->saved_vals;
1662 for (i = 0; i < pcs->size; i += mux_bytes)
1663 *regsw++ = pcs->read(pcs->base + i);
1664 break;
1665 case 16:
1666 regshw = pcs->saved_vals;
1667 for (i = 0; i < pcs->size; i += mux_bytes)
1668 *regshw++ = pcs->read(pcs->base + i);
1669 break;
1670 }
1671
1672 return 0;
1673}
1674
1675static void pcs_restore_context(struct pcs_device *pcs)
1676{
1677 int i, mux_bytes;
1678 u64 *regsl;
1679 u32 *regsw;
1680 u16 *regshw;
1681
1682 mux_bytes = pcs->width / BITS_PER_BYTE;
1683
1684 switch (pcs->width) {
1685 case 64:
1686 regsl = pcs->saved_vals;
1687 for (i = 0; i < pcs->size; i += mux_bytes)
1688 pcs->write(*regsl++, pcs->base + i);
1689 break;
1690 case 32:
1691 regsw = pcs->saved_vals;
1692 for (i = 0; i < pcs->size; i += mux_bytes)
1693 pcs->write(*regsw++, pcs->base + i);
1694 break;
1695 case 16:
1696 regshw = pcs->saved_vals;
1697 for (i = 0; i < pcs->size; i += mux_bytes)
1698 pcs->write(*regshw++, pcs->base + i);
1699 break;
1700 }
1701}
1702
1703static int pinctrl_single_suspend_noirq(struct device *dev)
1704{
1705 struct pcs_device *pcs = dev_get_drvdata(dev);
1706
1707 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1708 int ret;
1709
1710 ret = pcs_save_context(pcs);
1711 if (ret < 0)
1712 return ret;
1713 }
1714
1715 return pinctrl_force_sleep(pcs->pctl);
1716}
1717
1718static int pinctrl_single_resume_noirq(struct device *dev)
1719{
1720 struct pcs_device *pcs = dev_get_drvdata(dev);
1721
1722 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1723 pcs_restore_context(pcs);
1724
1725 return pinctrl_force_default(pcs->pctl);
1726}
1727
1728static DEFINE_NOIRQ_DEV_PM_OPS(pinctrl_single_pm_ops,
1729 pinctrl_single_suspend_noirq,
1730 pinctrl_single_resume_noirq);
1731
1732/**
1733 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1734 * @pcs: pinctrl driver instance
1735 * @np: device tree node
1736 * @cells: number of cells
1737 *
1738 * Handle legacy binding with no #pinctrl-cells. This should be
1739 * always two pinctrl-single,bit-per-mux and one for others.
1740 * At some point we may want to consider removing this.
1741 */
1742static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1743 struct device_node *np,
1744 int cells)
1745{
1746 struct property *p;
1747 const char *name = "#pinctrl-cells";
1748 int error;
1749 u32 val;
1750
1751 error = of_property_read_u32(np, name, &val);
1752 if (!error)
1753 return 0;
1754
1755 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1756 name, cells);
1757
1758 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1759 if (!p)
1760 return -ENOMEM;
1761
1762 p->length = sizeof(__be32);
1763 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1764 if (!p->value)
1765 return -ENOMEM;
1766 *(__be32 *)p->value = cpu_to_be32(cells);
1767
1768 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1769 if (!p->name)
1770 return -ENOMEM;
1771
1772 pcs->missing_nr_pinctrl_cells = p;
1773
1774#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1775 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1776#endif
1777
1778 return error;
1779}
1780
1781static int pcs_probe(struct platform_device *pdev)
1782{
1783 struct device_node *np = pdev->dev.of_node;
1784 struct pcs_pdata *pdata;
1785 struct resource *res;
1786 struct pcs_device *pcs;
1787 const struct pcs_soc_data *soc;
1788 int ret;
1789
1790 soc = of_device_get_match_data(&pdev->dev);
1791 if (WARN_ON(!soc))
1792 return -EINVAL;
1793
1794 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1795 if (!pcs)
1796 return -ENOMEM;
1797
1798 pcs->dev = &pdev->dev;
1799 pcs->np = np;
1800 raw_spin_lock_init(&pcs->lock);
1801 mutex_init(&pcs->mutex);
1802 INIT_LIST_HEAD(&pcs->gpiofuncs);
1803 pcs->flags = soc->flags;
1804 memcpy(&pcs->socdata, soc, sizeof(*soc));
1805
1806 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1807 &pcs->width);
1808 if (ret) {
1809 dev_err(pcs->dev, "register width not specified\n");
1810
1811 return ret;
1812 }
1813
1814 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1815 &pcs->fmask);
1816 if (!ret) {
1817 pcs->fshift = __ffs(pcs->fmask);
1818 pcs->fmax = pcs->fmask >> pcs->fshift;
1819 } else {
1820 /* If mask property doesn't exist, function mux is invalid. */
1821 pcs->fmask = 0;
1822 pcs->fshift = 0;
1823 pcs->fmax = 0;
1824 }
1825
1826 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1827 &pcs->foff);
1828 if (ret)
1829 pcs->foff = PCS_OFF_DISABLED;
1830
1831 pcs->bits_per_mux = of_property_read_bool(np,
1832 "pinctrl-single,bit-per-mux");
1833 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1834 pcs->bits_per_mux ? 2 : 1);
1835 if (ret) {
1836 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1837
1838 return ret;
1839 }
1840
1841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1842 if (!res) {
1843 dev_err(pcs->dev, "could not get resource\n");
1844 return -ENODEV;
1845 }
1846
1847 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1848 resource_size(res), DRIVER_NAME);
1849 if (!pcs->res) {
1850 dev_err(pcs->dev, "could not get mem_region\n");
1851 return -EBUSY;
1852 }
1853
1854 pcs->size = resource_size(pcs->res);
1855 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1856 if (!pcs->base) {
1857 dev_err(pcs->dev, "could not ioremap\n");
1858 return -ENODEV;
1859 }
1860
1861 platform_set_drvdata(pdev, pcs);
1862
1863 switch (pcs->width) {
1864 case 8:
1865 pcs->read = pcs_readb;
1866 pcs->write = pcs_writeb;
1867 break;
1868 case 16:
1869 pcs->read = pcs_readw;
1870 pcs->write = pcs_writew;
1871 break;
1872 case 32:
1873 pcs->read = pcs_readl;
1874 pcs->write = pcs_writel;
1875 break;
1876 default:
1877 break;
1878 }
1879
1880 pcs->desc.name = DRIVER_NAME;
1881 pcs->desc.pctlops = &pcs_pinctrl_ops;
1882 pcs->desc.pmxops = &pcs_pinmux_ops;
1883 if (PCS_HAS_PINCONF)
1884 pcs->desc.confops = &pcs_pinconf_ops;
1885 pcs->desc.owner = THIS_MODULE;
1886
1887 ret = pcs_allocate_pin_table(pcs);
1888 if (ret < 0)
1889 goto free;
1890
1891 ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl);
1892 if (ret) {
1893 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1894 goto free;
1895 }
1896
1897 ret = pcs_add_gpio_func(np, pcs);
1898 if (ret < 0)
1899 goto free;
1900
1901 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1902 if (pcs->socdata.irq)
1903 pcs->flags |= PCS_FEAT_IRQ;
1904
1905 /* We still need auxdata for some omaps for PRM interrupts */
1906 pdata = dev_get_platdata(&pdev->dev);
1907 if (pdata) {
1908 if (pdata->rearm)
1909 pcs->socdata.rearm = pdata->rearm;
1910 if (pdata->irq) {
1911 pcs->socdata.irq = pdata->irq;
1912 pcs->flags |= PCS_FEAT_IRQ;
1913 }
1914 }
1915
1916 if (PCS_HAS_IRQ) {
1917 ret = pcs_irq_init_chained_handler(pcs, np);
1918 if (ret < 0)
1919 dev_warn(pcs->dev, "initialized with no interrupts\n");
1920 }
1921
1922 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1923
1924 ret = pinctrl_enable(pcs->pctl);
1925 if (ret)
1926 goto free;
1927
1928 return 0;
1929free:
1930 pcs_free_resources(pcs);
1931
1932 return ret;
1933}
1934
1935static void pcs_remove(struct platform_device *pdev)
1936{
1937 struct pcs_device *pcs = platform_get_drvdata(pdev);
1938
1939 pcs_free_resources(pcs);
1940}
1941
1942static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1943 .flags = PCS_QUIRK_SHARED_IRQ,
1944 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1945 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1946};
1947
1948static const struct pcs_soc_data pinctrl_single_dra7 = {
1949 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1950 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1951};
1952
1953static const struct pcs_soc_data pinctrl_single_am437x = {
1954 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1955 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1956 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1957};
1958
1959static const struct pcs_soc_data pinctrl_single_am654 = {
1960 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1961 .irq_enable_mask = (1 << 29), /* WKUP_EN */
1962 .irq_status_mask = (1 << 30), /* WKUP_EVT */
1963};
1964
1965static const struct pcs_soc_data pinctrl_single_loss_off = {
1966 .flags = PCS_CONTEXT_LOSS_OFF,
1967};
1968
1969static const struct pcs_soc_data pinctrl_single = {
1970};
1971
1972static const struct pcs_soc_data pinconf_single = {
1973 .flags = PCS_FEAT_PINCONF,
1974};
1975
1976static const struct of_device_id pcs_of_match[] = {
1977 { .compatible = "brcm,bcm7038-padconf", .data = &pinctrl_single_loss_off },
1978 { .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single },
1979 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1980 { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
1981 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1982 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1983 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1984 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1985 { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_loss_off },
1986 { .compatible = "ti,am62l-padconf", .data = &pinctrl_single_loss_off },
1987 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1988 { .compatible = "pinconf-single", .data = &pinconf_single },
1989 { },
1990};
1991MODULE_DEVICE_TABLE(of, pcs_of_match);
1992
1993static struct platform_driver pcs_driver = {
1994 .probe = pcs_probe,
1995 .remove = pcs_remove,
1996 .driver = {
1997 .name = DRIVER_NAME,
1998 .of_match_table = pcs_of_match,
1999 .pm = pm_sleep_ptr(&pinctrl_single_pm_ops),
2000 },
2001};
2002
2003module_platform_driver(pcs_driver);
2004
2005MODULE_AUTHOR("Tony Lindgren <[email protected]>");
2006MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2007MODULE_LICENSE("GPL v2");