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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2019 Nuvoton Technology corporation.
3
4#include <linux/auxiliary_bus.h>
5#include <linux/delay.h>
6#include <linux/err.h>
7#include <linux/io.h>
8#include <linux/init.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/property.h>
12#include <linux/reboot.h>
13#include <linux/reset-controller.h>
14#include <linux/slab.h>
15#include <linux/spinlock.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18#include <linux/of_address.h>
19
20#include <soc/nuvoton/clock-npcm8xx.h>
21
22/* NPCM7xx GCR registers */
23#define NPCM_MDLR_OFFSET 0x7C
24#define NPCM7XX_MDLR_USBD0 BIT(9)
25#define NPCM7XX_MDLR_USBD1 BIT(8)
26#define NPCM7XX_MDLR_USBD2_4 BIT(21)
27#define NPCM7XX_MDLR_USBD5_9 BIT(22)
28
29/* NPCM8xx MDLR bits */
30#define NPCM8XX_MDLR_USBD0_3 BIT(9)
31#define NPCM8XX_MDLR_USBD4_7 BIT(22)
32#define NPCM8XX_MDLR_USBD8 BIT(24)
33#define NPCM8XX_MDLR_USBD9 BIT(21)
34
35#define NPCM_USB1PHYCTL_OFFSET 0x140
36#define NPCM_USB2PHYCTL_OFFSET 0x144
37#define NPCM_USB3PHYCTL_OFFSET 0x148
38#define NPCM_USBXPHYCTL_RS BIT(28)
39
40/* NPCM7xx Reset registers */
41#define NPCM_SWRSTR 0x14
42#define NPCM_SWRST BIT(2)
43
44#define NPCM_IPSRST1 0x20
45#define NPCM_IPSRST1_USBD1 BIT(5)
46#define NPCM_IPSRST1_USBD2 BIT(8)
47#define NPCM_IPSRST1_USBD3 BIT(25)
48#define NPCM_IPSRST1_USBD4 BIT(22)
49#define NPCM_IPSRST1_USBD5 BIT(23)
50#define NPCM_IPSRST1_USBD6 BIT(24)
51
52#define NPCM_IPSRST2 0x24
53#define NPCM_IPSRST2_USB_HOST BIT(26)
54
55#define NPCM_IPSRST3 0x34
56#define NPCM_IPSRST3_USBD0 BIT(4)
57#define NPCM_IPSRST3_USBD7 BIT(5)
58#define NPCM_IPSRST3_USBD8 BIT(6)
59#define NPCM_IPSRST3_USBD9 BIT(7)
60#define NPCM_IPSRST3_USBPHY1 BIT(24)
61#define NPCM_IPSRST3_USBPHY2 BIT(25)
62
63#define NPCM_IPSRST4 0x74
64#define NPCM_IPSRST4_USBPHY3 BIT(25)
65#define NPCM_IPSRST4_USB_HOST2 BIT(31)
66
67#define NPCM_RC_RESETS_PER_REG 32
68#define NPCM_MASK_RESETS GENMASK(4, 0)
69
70enum {
71 BMC_NPCM7XX = 0,
72 BMC_NPCM8XX,
73};
74
75static const u32 npxm7xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3};
76static const u32 npxm8xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3,
77 NPCM_IPSRST4};
78
79struct npcm_reset_info {
80 u32 bmc_id;
81 u32 num_ipsrst;
82 const u32 *ipsrst;
83};
84
85static const struct npcm_reset_info npxm7xx_reset_info[] = {
86 {.bmc_id = BMC_NPCM7XX, .num_ipsrst = 3, .ipsrst = npxm7xx_ipsrst}};
87static const struct npcm_reset_info npxm8xx_reset_info[] = {
88 {.bmc_id = BMC_NPCM8XX, .num_ipsrst = 4, .ipsrst = npxm8xx_ipsrst}};
89
90struct npcm_rc_data {
91 struct reset_controller_dev rcdev;
92 const struct npcm_reset_info *info;
93 struct regmap *gcr_regmap;
94 u32 sw_reset_number;
95 struct device *dev;
96 void __iomem *base;
97 spinlock_t lock;
98};
99
100#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
101
102static int npcm_rc_restart(struct sys_off_data *data)
103{
104 struct npcm_rc_data *rc = data->cb_data;
105
106 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
107 mdelay(1000);
108
109 pr_emerg("%s: unable to restart system\n", __func__);
110
111 return NOTIFY_DONE;
112}
113
114static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
115 unsigned long id, bool set)
116{
117 struct npcm_rc_data *rc = to_rc_data(rcdev);
118 unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
119 unsigned int ctrl_offset = id >> 8;
120 unsigned long flags;
121 u32 stat;
122
123 spin_lock_irqsave(&rc->lock, flags);
124 stat = readl(rc->base + ctrl_offset);
125 if (set)
126 writel(stat | rst_bit, rc->base + ctrl_offset);
127 else
128 writel(stat & ~rst_bit, rc->base + ctrl_offset);
129 spin_unlock_irqrestore(&rc->lock, flags);
130
131 return 0;
132}
133
134static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
135{
136 return npcm_rc_setclear_reset(rcdev, id, true);
137}
138
139static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
140 unsigned long id)
141{
142 return npcm_rc_setclear_reset(rcdev, id, false);
143}
144
145static int npcm_rc_status(struct reset_controller_dev *rcdev,
146 unsigned long id)
147{
148 struct npcm_rc_data *rc = to_rc_data(rcdev);
149 unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
150 unsigned int ctrl_offset = id >> 8;
151
152 return (readl(rc->base + ctrl_offset) & rst_bit);
153}
154
155static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
156 const struct of_phandle_args *reset_spec)
157{
158 struct npcm_rc_data *rc = to_rc_data(rcdev);
159 unsigned int offset, bit;
160 bool offset_found = false;
161 int off_num;
162
163 offset = reset_spec->args[0];
164 for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) {
165 if (offset == rc->info->ipsrst[off_num]) {
166 offset_found = true;
167 break;
168 }
169 }
170
171 if (!offset_found) {
172 dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
173 return -EINVAL;
174 }
175
176 bit = reset_spec->args[1];
177 if (bit >= NPCM_RC_RESETS_PER_REG) {
178 dev_err(rcdev->dev, "Error reset number (%d)\n", bit);
179 return -EINVAL;
180 }
181
182 return (offset << 8) | bit;
183}
184
185static const struct of_device_id npcm_rc_match[] = {
186 { .compatible = "nuvoton,npcm750-reset", .data = &npxm7xx_reset_info},
187 { .compatible = "nuvoton,npcm845-reset", .data = &npxm8xx_reset_info},
188 { }
189};
190
191static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
192{
193 u32 mdlr, iprst1, iprst2, iprst3;
194 u32 ipsrst1_bits = 0;
195 u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
196 u32 ipsrst3_bits = 0;
197
198 /* checking which USB device is enabled */
199 regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
200 if (!(mdlr & NPCM7XX_MDLR_USBD0))
201 ipsrst3_bits |= NPCM_IPSRST3_USBD0;
202 if (!(mdlr & NPCM7XX_MDLR_USBD1))
203 ipsrst1_bits |= NPCM_IPSRST1_USBD1;
204 if (!(mdlr & NPCM7XX_MDLR_USBD2_4))
205 ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
206 NPCM_IPSRST1_USBD3 |
207 NPCM_IPSRST1_USBD4);
208 if (!(mdlr & NPCM7XX_MDLR_USBD0)) {
209 ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
210 NPCM_IPSRST1_USBD6);
211 ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
212 NPCM_IPSRST3_USBD8 |
213 NPCM_IPSRST3_USBD9);
214 }
215
216 /* assert reset USB PHY and USB devices */
217 iprst1 = readl(rc->base + NPCM_IPSRST1);
218 iprst2 = readl(rc->base + NPCM_IPSRST2);
219 iprst3 = readl(rc->base + NPCM_IPSRST3);
220
221 iprst1 |= ipsrst1_bits;
222 iprst2 |= ipsrst2_bits;
223 iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
224 NPCM_IPSRST3_USBPHY2);
225
226 writel(iprst1, rc->base + NPCM_IPSRST1);
227 writel(iprst2, rc->base + NPCM_IPSRST2);
228 writel(iprst3, rc->base + NPCM_IPSRST3);
229
230 /* clear USB PHY RS bit */
231 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
232 NPCM_USBXPHYCTL_RS, 0);
233 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
234 NPCM_USBXPHYCTL_RS, 0);
235
236 /* deassert reset USB PHY */
237 iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
238 writel(iprst3, rc->base + NPCM_IPSRST3);
239
240 udelay(50);
241
242 /* set USB PHY RS bit */
243 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
244 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
245 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
246 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
247
248 /* deassert reset USB devices*/
249 iprst1 &= ~ipsrst1_bits;
250 iprst2 &= ~ipsrst2_bits;
251 iprst3 &= ~ipsrst3_bits;
252
253 writel(iprst1, rc->base + NPCM_IPSRST1);
254 writel(iprst2, rc->base + NPCM_IPSRST2);
255 writel(iprst3, rc->base + NPCM_IPSRST3);
256}
257
258static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
259{
260 u32 mdlr, iprst1, iprst2, iprst3, iprst4;
261 u32 ipsrst1_bits = 0;
262 u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
263 u32 ipsrst3_bits = 0;
264 u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3;
265
266 /* checking which USB device is enabled */
267 regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
268 if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) {
269 ipsrst3_bits |= NPCM_IPSRST3_USBD0;
270 ipsrst1_bits |= (NPCM_IPSRST1_USBD1 |
271 NPCM_IPSRST1_USBD2 |
272 NPCM_IPSRST1_USBD3);
273 }
274 if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) {
275 ipsrst1_bits |= (NPCM_IPSRST1_USBD4 |
276 NPCM_IPSRST1_USBD5 |
277 NPCM_IPSRST1_USBD6);
278 ipsrst3_bits |= NPCM_IPSRST3_USBD7;
279 }
280
281 if (!(mdlr & NPCM8XX_MDLR_USBD8))
282 ipsrst3_bits |= NPCM_IPSRST3_USBD8;
283 if (!(mdlr & NPCM8XX_MDLR_USBD9))
284 ipsrst3_bits |= NPCM_IPSRST3_USBD9;
285
286 /* assert reset USB PHY and USB devices */
287 iprst1 = readl(rc->base + NPCM_IPSRST1);
288 iprst2 = readl(rc->base + NPCM_IPSRST2);
289 iprst3 = readl(rc->base + NPCM_IPSRST3);
290 iprst4 = readl(rc->base + NPCM_IPSRST4);
291
292 iprst1 |= ipsrst1_bits;
293 iprst2 |= ipsrst2_bits;
294 iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
295 NPCM_IPSRST3_USBPHY2);
296 iprst4 |= ipsrst4_bits;
297
298 writel(iprst1, rc->base + NPCM_IPSRST1);
299 writel(iprst2, rc->base + NPCM_IPSRST2);
300 writel(iprst3, rc->base + NPCM_IPSRST3);
301 writel(iprst4, rc->base + NPCM_IPSRST4);
302
303 /* clear USB PHY RS bit */
304 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
305 NPCM_USBXPHYCTL_RS, 0);
306 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
307 NPCM_USBXPHYCTL_RS, 0);
308 regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
309 NPCM_USBXPHYCTL_RS, 0);
310
311 /* deassert reset USB PHY */
312 iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
313 writel(iprst3, rc->base + NPCM_IPSRST3);
314 iprst4 &= ~NPCM_IPSRST4_USBPHY3;
315 writel(iprst4, rc->base + NPCM_IPSRST4);
316
317 /* set USB PHY RS bit */
318 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
319 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
320 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
321 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
322 regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
323 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
324
325 /* deassert reset USB devices*/
326 iprst1 &= ~ipsrst1_bits;
327 iprst2 &= ~ipsrst2_bits;
328 iprst3 &= ~ipsrst3_bits;
329 iprst4 &= ~ipsrst4_bits;
330
331 writel(iprst1, rc->base + NPCM_IPSRST1);
332 writel(iprst2, rc->base + NPCM_IPSRST2);
333 writel(iprst3, rc->base + NPCM_IPSRST3);
334 writel(iprst4, rc->base + NPCM_IPSRST4);
335}
336
337/*
338 * The following procedure should be observed in USB PHY, USB device and
339 * USB host initialization at BMC boot
340 */
341static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
342{
343 struct device *dev = &pdev->dev;
344
345 rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
346 if (IS_ERR(rc->gcr_regmap)) {
347 dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n");
348 dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n");
349 rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
350 if (IS_ERR(rc->gcr_regmap)) {
351 dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr");
352 return PTR_ERR(rc->gcr_regmap);
353 }
354 }
355
356 rc->info = device_get_match_data(dev);
357 switch (rc->info->bmc_id) {
358 case BMC_NPCM7XX:
359 npcm_usb_reset_npcm7xx(rc);
360 break;
361 case BMC_NPCM8XX:
362 npcm_usb_reset_npcm8xx(rc);
363 break;
364 default:
365 return -ENODEV;
366 }
367
368 return 0;
369}
370
371static const struct reset_control_ops npcm_rc_ops = {
372 .assert = npcm_rc_assert,
373 .deassert = npcm_rc_deassert,
374 .status = npcm_rc_status,
375};
376
377static void npcm_clock_unregister_adev(void *_adev)
378{
379 struct auxiliary_device *adev = _adev;
380
381 auxiliary_device_delete(adev);
382 auxiliary_device_uninit(adev);
383}
384
385static void npcm_clock_adev_release(struct device *dev)
386{
387 struct auxiliary_device *adev = to_auxiliary_dev(dev);
388 struct npcm_clock_adev *rdev = to_npcm_clock_adev(adev);
389
390 kfree(rdev);
391}
392
393static struct auxiliary_device *npcm_clock_adev_alloc(struct npcm_rc_data *rst_data, char *clk_name)
394{
395 struct npcm_clock_adev *rdev;
396 struct auxiliary_device *adev;
397 int ret;
398
399 rdev = kzalloc_obj(*rdev);
400 if (!rdev)
401 return ERR_PTR(-ENOMEM);
402
403 rdev->base = rst_data->base;
404
405 adev = &rdev->adev;
406 adev->name = clk_name;
407 adev->dev.parent = rst_data->dev;
408 adev->dev.release = npcm_clock_adev_release;
409 adev->id = 555u;
410
411 ret = auxiliary_device_init(adev);
412 if (ret) {
413 kfree(rdev);
414 return ERR_PTR(ret);
415 }
416
417 return adev;
418}
419
420static int npcm8xx_clock_controller_register(struct npcm_rc_data *rst_data, char *clk_name)
421{
422 struct auxiliary_device *adev;
423 int ret;
424
425 adev = npcm_clock_adev_alloc(rst_data, clk_name);
426 if (IS_ERR(adev))
427 return PTR_ERR(adev);
428
429 ret = auxiliary_device_add(adev);
430 if (ret) {
431 auxiliary_device_uninit(adev);
432 return ret;
433 }
434
435 return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev);
436}
437
438static int npcm_rc_probe(struct platform_device *pdev)
439{
440 struct npcm_rc_data *rc;
441 int ret;
442
443 rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
444 if (!rc)
445 return -ENOMEM;
446
447 rc->base = devm_platform_ioremap_resource(pdev, 0);
448 if (IS_ERR(rc->base))
449 return PTR_ERR(rc->base);
450
451 spin_lock_init(&rc->lock);
452
453 rc->rcdev.owner = THIS_MODULE;
454 rc->rcdev.ops = &npcm_rc_ops;
455 rc->rcdev.of_node = pdev->dev.of_node;
456 rc->rcdev.of_reset_n_cells = 2;
457 rc->rcdev.of_xlate = npcm_reset_xlate;
458 rc->dev = &pdev->dev;
459
460 ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
461 if (ret) {
462 dev_err(&pdev->dev, "unable to register device\n");
463 return ret;
464 }
465
466 if (npcm_usb_reset(pdev, rc))
467 dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
468
469 if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
470 &rc->sw_reset_number)) {
471 if (rc->sw_reset_number && rc->sw_reset_number < 5) {
472 ret = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, 192,
473 npcm_rc_restart, rc);
474 if (ret) {
475 dev_warn(&pdev->dev, "failed to register restart handler\n");
476 return ret;
477 }
478 }
479 }
480
481 switch (rc->info->bmc_id) {
482 case BMC_NPCM8XX:
483 return npcm8xx_clock_controller_register(rc, "clk-npcm8xx");
484 default:
485 return 0;
486 }
487}
488
489static struct platform_driver npcm_rc_driver = {
490 .probe = npcm_rc_probe,
491 .driver = {
492 .name = "npcm-reset",
493 .of_match_table = npcm_rc_match,
494 .suppress_bind_attrs = true,
495 },
496};
497builtin_platform_driver(npcm_rc_driver);