projects/linux·blob master · refs

621 lines · 16.6 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * RTC Driver for X-Powers AC100
4 *
5 * Copyright (c) 2016 Chen-Yu Tsai
6 *
7 * Chen-Yu Tsai <[email protected]>
8 */
9
10#include <linux/bcd.h>
11#include <linux/clk-provider.h>
12#include <linux/device.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/mfd/ac100.h>
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <linux/rtc.h>
22#include <linux/types.h>
23
24/* Control register */
25#define AC100_RTC_CTRL_24HOUR BIT(0)
26
27/* Clock output register bits */
28#define AC100_CLKOUT_PRE_DIV_SHIFT 5
29#define AC100_CLKOUT_PRE_DIV_WIDTH 3
30#define AC100_CLKOUT_MUX_SHIFT 4
31#define AC100_CLKOUT_MUX_WIDTH 1
32#define AC100_CLKOUT_DIV_SHIFT 1
33#define AC100_CLKOUT_DIV_WIDTH 3
34#define AC100_CLKOUT_EN BIT(0)
35
36/* RTC */
37#define AC100_RTC_SEC_MASK GENMASK(6, 0)
38#define AC100_RTC_MIN_MASK GENMASK(6, 0)
39#define AC100_RTC_HOU_MASK GENMASK(5, 0)
40#define AC100_RTC_WEE_MASK GENMASK(2, 0)
41#define AC100_RTC_DAY_MASK GENMASK(5, 0)
42#define AC100_RTC_MON_MASK GENMASK(4, 0)
43#define AC100_RTC_YEA_MASK GENMASK(7, 0)
44#define AC100_RTC_YEA_LEAP BIT(15)
45#define AC100_RTC_UPD_TRIGGER BIT(15)
46
47/* Alarm (wall clock) */
48#define AC100_ALM_INT_ENABLE BIT(0)
49
50#define AC100_ALM_SEC_MASK GENMASK(6, 0)
51#define AC100_ALM_MIN_MASK GENMASK(6, 0)
52#define AC100_ALM_HOU_MASK GENMASK(5, 0)
53#define AC100_ALM_WEE_MASK GENMASK(2, 0)
54#define AC100_ALM_DAY_MASK GENMASK(5, 0)
55#define AC100_ALM_MON_MASK GENMASK(4, 0)
56#define AC100_ALM_YEA_MASK GENMASK(7, 0)
57#define AC100_ALM_ENABLE_FLAG BIT(15)
58#define AC100_ALM_UPD_TRIGGER BIT(15)
59
60/*
61 * The year parameter passed to the driver is usually an offset relative to
62 * the year 1900. This macro is used to convert this offset to another one
63 * relative to the minimum year allowed by the hardware.
64 *
65 * The year range is 1970 - 2069. This range is selected to match Allwinner's
66 * driver.
67 */
68#define AC100_YEAR_MIN 1970
69#define AC100_YEAR_MAX 2069
70#define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
71
72struct ac100_clkout {
73 struct clk_hw hw;
74 struct regmap *regmap;
75 u8 offset;
76};
77
78#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)
79
80#define AC100_RTC_32K_NAME "ac100-rtc-32k"
81#define AC100_RTC_32K_RATE 32768
82#define AC100_CLKOUT_NUM 3
83
84static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
85 "ac100-cko1-rtc",
86 "ac100-cko2-rtc",
87 "ac100-cko3-rtc",
88};
89
90struct ac100_rtc_dev {
91 struct rtc_device *rtc;
92 struct device *dev;
93 struct regmap *regmap;
94 int irq;
95 unsigned long alarm;
96
97 struct clk_hw *rtc_32k_clk;
98 struct ac100_clkout clks[AC100_CLKOUT_NUM];
99 struct clk_hw_onecell_data *clk_data;
100};
101
102/*
103 * Clock controls for 3 clock output pins
104 */
105
106static const struct clk_div_table ac100_clkout_prediv[] = {
107 { .val = 0, .div = 1 },
108 { .val = 1, .div = 2 },
109 { .val = 2, .div = 4 },
110 { .val = 3, .div = 8 },
111 { .val = 4, .div = 16 },
112 { .val = 5, .div = 32 },
113 { .val = 6, .div = 64 },
114 { .val = 7, .div = 122 },
115 { },
116};
117
118/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
119static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
120 unsigned long prate)
121{
122 struct ac100_clkout *clk = to_ac100_clkout(hw);
123 unsigned int reg, div;
124
125 regmap_read(clk->regmap, clk->offset, &reg);
126
127 /* Handle pre-divider first */
128 if (prate != AC100_RTC_32K_RATE) {
129 div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
130 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
131 prate = divider_recalc_rate(hw, prate, div,
132 ac100_clkout_prediv, 0,
133 AC100_CLKOUT_PRE_DIV_WIDTH);
134 }
135
136 div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
137 (BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
138 return divider_recalc_rate(hw, prate, div, NULL,
139 CLK_DIVIDER_POWER_OF_TWO,
140 AC100_CLKOUT_DIV_WIDTH);
141}
142
143static int ac100_clkout_determine_rate(struct clk_hw *hw,
144 struct clk_rate_request *req)
145{
146 int i, ret, num_parents = clk_hw_get_num_parents(hw);
147 struct clk_hw *best_parent = NULL;
148 unsigned long best = 0;
149
150 for (i = 0; i < num_parents; i++) {
151 struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
152 unsigned long prate;
153
154 /*
155 * The clock has two parents, one is a fixed clock which is
156 * internally registered by the ac100 driver. The other parent
157 * is a clock from the codec side of the chip, which we
158 * properly declare and reference in the devicetree and is
159 * not implemented in any driver right now.
160 * If the clock core looks for the parent of that second
161 * missing clock, it can't find one that is registered and
162 * returns NULL.
163 * So we end up in a situation where clk_hw_get_num_parents
164 * returns the amount of clocks we can be parented to, but
165 * clk_hw_get_parent_by_index will not return the orphan
166 * clocks.
167 * Thus we need to check if the parent exists before
168 * we get the parent rate, so we could use the RTC
169 * without waiting for the codec to be supported.
170 */
171 if (!parent)
172 continue;
173
174 prate = clk_hw_get_rate(parent);
175
176 if (prate == AC100_RTC_32K_RATE) {
177 struct clk_rate_request div_req = *req;
178
179 div_req.best_parent_rate = prate;
180
181 ret = divider_determine_rate(hw, &div_req, NULL,
182 AC100_CLKOUT_DIV_WIDTH,
183 CLK_DIVIDER_POWER_OF_TWO);
184 if (ret != 0 || div_req.rate > req->rate) {
185 continue;
186 } else if (req->rate - div_req.rate < req->rate - best) {
187 best = div_req.rate;
188 best_parent = parent;
189 }
190 } else {
191 int j;
192
193 for (j = 0; ac100_clkout_prediv[j].div; j++) {
194 struct clk_rate_request div_req = *req;
195 unsigned long tmp_prate;
196
197 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[j].div);
198 div_req.best_parent_rate = tmp_prate;
199
200 ret = divider_determine_rate(hw, &div_req, NULL,
201 AC100_CLKOUT_DIV_WIDTH,
202 CLK_DIVIDER_POWER_OF_TWO);
203 if (ret != 0 || div_req.rate > req->rate) {
204 continue;
205 } else if (req->rate - div_req.rate < req->rate - best) {
206 best = div_req.rate;
207 best_parent = parent;
208 }
209 }
210 }
211 }
212
213 if (!best)
214 return -EINVAL;
215
216 req->best_parent_hw = best_parent;
217 req->best_parent_rate = clk_hw_get_rate(best_parent);
218 req->rate = best;
219
220 return 0;
221}
222
223static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
224 unsigned long prate)
225{
226 struct ac100_clkout *clk = to_ac100_clkout(hw);
227 int div = 0, pre_div = 0;
228
229 do {
230 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
231 prate, NULL, AC100_CLKOUT_DIV_WIDTH,
232 CLK_DIVIDER_POWER_OF_TWO);
233 if (div >= 0)
234 break;
235 } while (prate != AC100_RTC_32K_RATE &&
236 ac100_clkout_prediv[++pre_div].div);
237
238 if (div < 0)
239 return div;
240
241 pre_div = ac100_clkout_prediv[pre_div].val;
242
243 regmap_update_bits(clk->regmap, clk->offset,
244 ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
245 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
246 (div - 1) << AC100_CLKOUT_DIV_SHIFT |
247 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
248
249 return 0;
250}
251
252static int ac100_clkout_prepare(struct clk_hw *hw)
253{
254 struct ac100_clkout *clk = to_ac100_clkout(hw);
255
256 return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
257 AC100_CLKOUT_EN);
258}
259
260static void ac100_clkout_unprepare(struct clk_hw *hw)
261{
262 struct ac100_clkout *clk = to_ac100_clkout(hw);
263
264 regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
265}
266
267static int ac100_clkout_is_prepared(struct clk_hw *hw)
268{
269 struct ac100_clkout *clk = to_ac100_clkout(hw);
270 unsigned int reg;
271
272 regmap_read(clk->regmap, clk->offset, &reg);
273
274 return reg & AC100_CLKOUT_EN;
275}
276
277static u8 ac100_clkout_get_parent(struct clk_hw *hw)
278{
279 struct ac100_clkout *clk = to_ac100_clkout(hw);
280 unsigned int reg;
281
282 regmap_read(clk->regmap, clk->offset, &reg);
283
284 return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
285}
286
287static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
288{
289 struct ac100_clkout *clk = to_ac100_clkout(hw);
290
291 return regmap_update_bits(clk->regmap, clk->offset,
292 BIT(AC100_CLKOUT_MUX_SHIFT),
293 index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
294}
295
296static const struct clk_ops ac100_clkout_ops = {
297 .prepare = ac100_clkout_prepare,
298 .unprepare = ac100_clkout_unprepare,
299 .is_prepared = ac100_clkout_is_prepared,
300 .recalc_rate = ac100_clkout_recalc_rate,
301 .determine_rate = ac100_clkout_determine_rate,
302 .get_parent = ac100_clkout_get_parent,
303 .set_parent = ac100_clkout_set_parent,
304 .set_rate = ac100_clkout_set_rate,
305};
306
307static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
308{
309 struct device_node *np = chip->dev->of_node;
310 const char *parents[2] = {AC100_RTC_32K_NAME};
311 int i, ret;
312
313 chip->clk_data = devm_kzalloc(chip->dev,
314 struct_size(chip->clk_data, hws,
315 AC100_CLKOUT_NUM),
316 GFP_KERNEL);
317 if (!chip->clk_data)
318 return -ENOMEM;
319
320 chip->clk_data->num = AC100_CLKOUT_NUM;
321
322 chip->rtc_32k_clk = devm_clk_hw_register_fixed_rate(chip->dev,
323 AC100_RTC_32K_NAME,
324 NULL, 0,
325 AC100_RTC_32K_RATE);
326 if (IS_ERR(chip->rtc_32k_clk)) {
327 ret = PTR_ERR(chip->rtc_32k_clk);
328 dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
329 ret);
330 return ret;
331 }
332
333 parents[1] = of_clk_get_parent_name(np, 0);
334 if (!parents[1]) {
335 dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
336 return -EINVAL;
337 }
338
339 for (i = 0; i < AC100_CLKOUT_NUM; i++) {
340 struct ac100_clkout *clk = &chip->clks[i];
341 struct clk_init_data init = {
342 .name = ac100_clkout_names[i],
343 .ops = &ac100_clkout_ops,
344 .parent_names = parents,
345 .num_parents = ARRAY_SIZE(parents),
346 .flags = 0,
347 };
348
349 of_property_read_string_index(np, "clock-output-names",
350 i, &init.name);
351 clk->regmap = chip->regmap;
352 clk->offset = AC100_CLKOUT_CTRL1 + i;
353 clk->hw.init = &init;
354
355 ret = devm_clk_hw_register(chip->dev, &clk->hw);
356 if (ret) {
357 dev_err(chip->dev, "Failed to register clk '%s': %d\n",
358 init.name, ret);
359 return ret;
360 }
361
362 chip->clk_data->hws[i] = &clk->hw;
363 }
364
365 return devm_of_clk_add_hw_provider(chip->dev, of_clk_hw_onecell_get,
366 chip->clk_data);
367}
368
369/*
370 * RTC related bits
371 */
372static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)
373{
374 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
375 struct regmap *regmap = chip->regmap;
376 u16 reg[7];
377 int ret;
378
379 ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
380 if (ret)
381 return ret;
382
383 rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
384 rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
385 rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
386 rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
387 rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
388 rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
389 rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
390 AC100_YEAR_OFF;
391
392 return 0;
393}
394
395static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
396{
397 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
398 struct regmap *regmap = chip->regmap;
399 int year;
400 u16 reg[8];
401
402 /* our RTC has a limited year range... */
403 year = rtc_tm->tm_year - AC100_YEAR_OFF;
404 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
405 dev_err(dev, "rtc only supports year in range %d - %d\n",
406 AC100_YEAR_MIN, AC100_YEAR_MAX);
407 return -EINVAL;
408 }
409
410 /* convert to BCD */
411 reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK;
412 reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK;
413 reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK;
414 reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK;
415 reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK;
416 reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
417 reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK;
418 /* trigger write */
419 reg[7] = AC100_RTC_UPD_TRIGGER;
420
421 /* Is it a leap year? */
422 if (is_leap_year(year + AC100_YEAR_OFF + 1900))
423 reg[6] |= AC100_RTC_YEA_LEAP;
424
425 return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
426}
427
428static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
429{
430 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
431 struct regmap *regmap = chip->regmap;
432 unsigned int val;
433
434 val = en ? AC100_ALM_INT_ENABLE : 0;
435
436 return regmap_write(regmap, AC100_ALM_INT_ENA, val);
437}
438
439static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
440{
441 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
442 struct regmap *regmap = chip->regmap;
443 struct rtc_time *alrm_tm = &alrm->time;
444 u16 reg[7];
445 unsigned int val;
446 int ret;
447
448 ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
449 if (ret)
450 return ret;
451
452 alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);
453
454 ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
455 if (ret)
456 return ret;
457
458 alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
459 alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
460 alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
461 alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
462 alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
463 alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
464 alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
465 AC100_YEAR_OFF;
466
467 return 0;
468}
469
470static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
471{
472 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
473 struct regmap *regmap = chip->regmap;
474 struct rtc_time *alrm_tm = &alrm->time;
475 u16 reg[8];
476 int year;
477 int ret;
478
479 /* our alarm has a limited year range... */
480 year = alrm_tm->tm_year - AC100_YEAR_OFF;
481 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
482 dev_err(dev, "alarm only supports year in range %d - %d\n",
483 AC100_YEAR_MIN, AC100_YEAR_MAX);
484 return -EINVAL;
485 }
486
487 /* convert to BCD */
488 reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) |
489 AC100_ALM_ENABLE_FLAG;
490 reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) |
491 AC100_ALM_ENABLE_FLAG;
492 reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) |
493 AC100_ALM_ENABLE_FLAG;
494 /* Do not enable weekday alarm */
495 reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
496 reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) |
497 AC100_ALM_ENABLE_FLAG;
498 reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) |
499 AC100_ALM_ENABLE_FLAG;
500 reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) |
501 AC100_ALM_ENABLE_FLAG;
502 /* trigger write */
503 reg[7] = AC100_ALM_UPD_TRIGGER;
504
505 ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
506 if (ret)
507 return ret;
508
509 return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
510}
511
512static irqreturn_t ac100_rtc_irq(int irq, void *data)
513{
514 struct ac100_rtc_dev *chip = data;
515 struct regmap *regmap = chip->regmap;
516 unsigned int val = 0;
517 int ret;
518
519 rtc_lock(chip->rtc);
520
521 /* read status */
522 ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
523 if (ret)
524 goto out;
525
526 if (val & AC100_ALM_INT_ENABLE) {
527 /* signal rtc framework */
528 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
529
530 /* clear status */
531 ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
532 if (ret)
533 goto out;
534
535 /* disable interrupt */
536 ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
537 if (ret)
538 goto out;
539 }
540
541out:
542 rtc_unlock(chip->rtc);
543 return IRQ_HANDLED;
544}
545
546static const struct rtc_class_ops ac100_rtc_ops = {
547 .read_time = ac100_rtc_get_time,
548 .set_time = ac100_rtc_set_time,
549 .read_alarm = ac100_rtc_get_alarm,
550 .set_alarm = ac100_rtc_set_alarm,
551 .alarm_irq_enable = ac100_rtc_alarm_irq_enable,
552};
553
554static int ac100_rtc_probe(struct platform_device *pdev)
555{
556 struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
557 struct ac100_rtc_dev *chip;
558 int ret;
559
560 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
561 if (!chip)
562 return -ENOMEM;
563
564 platform_set_drvdata(pdev, chip);
565 chip->dev = &pdev->dev;
566 chip->regmap = ac100->regmap;
567
568 chip->irq = platform_get_irq(pdev, 0);
569 if (chip->irq < 0)
570 return chip->irq;
571
572 chip->rtc = devm_rtc_allocate_device(&pdev->dev);
573 if (IS_ERR(chip->rtc))
574 return PTR_ERR(chip->rtc);
575
576 chip->rtc->ops = &ac100_rtc_ops;
577
578 ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
579 ac100_rtc_irq,
580 IRQF_SHARED | IRQF_ONESHOT,
581 dev_name(&pdev->dev), chip);
582 if (ret) {
583 dev_err(&pdev->dev, "Could not request IRQ\n");
584 return ret;
585 }
586
587 /* always use 24 hour mode */
588 regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
589 AC100_RTC_CTRL_24HOUR);
590
591 /* disable counter alarm interrupt */
592 regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);
593
594 /* clear counter alarm pending interrupts */
595 regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);
596
597 ret = ac100_rtc_register_clks(chip);
598 if (ret)
599 return ret;
600
601 return devm_rtc_register_device(chip->rtc);
602}
603
604static const struct of_device_id ac100_rtc_match[] = {
605 { .compatible = "x-powers,ac100-rtc" },
606 { },
607};
608MODULE_DEVICE_TABLE(of, ac100_rtc_match);
609
610static struct platform_driver ac100_rtc_driver = {
611 .probe = ac100_rtc_probe,
612 .driver = {
613 .name = "ac100-rtc",
614 .of_match_table = of_match_ptr(ac100_rtc_match),
615 },
616};
617module_platform_driver(ac100_rtc_driver);
618
619MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
620MODULE_AUTHOR("Chen-Yu Tsai <[email protected]>");
621MODULE_LICENSE("GPL v2");